OpenWrt – Rev 1

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--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -38,7 +38,7 @@ unsigned int ath79_soc_rev;
 void __iomem *ath79_pll_base;
 void __iomem *ath79_reset_base;
 EXPORT_SYMBOL_GPL(ath79_reset_base);
-static void __iomem *ath79_ddr_base;
+void __iomem *ath79_ddr_base;
 static void __iomem *ath79_ddr_wb_flush_base;
 static void __iomem *ath79_ddr_pci_win_base;
 
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -32,7 +32,7 @@
 #define AR71XX_SPI_SIZE                0x01000000
 
 #define AR71XX_DDR_CTRL_BASE   (AR71XX_APB_BASE + 0x00000000)
-#define AR71XX_DDR_CTRL_SIZE   0x100
+#define AR71XX_DDR_CTRL_SIZE   0x200
 #define AR71XX_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
 #define AR71XX_UART_SIZE       0x100
 #define AR71XX_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
@@ -229,6 +229,9 @@
 #define QCA953X_DDR_REG_FLUSH_PCIE     0xa8
 #define QCA953X_DDR_REG_FLUSH_WMAC     0xac
 
+#define QCA955X_DDR_CTL_CONFIG         0x108
+#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC        BIT(23)
+
 /*
  * PLL block
  */
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -165,6 +165,27 @@ static void qca953x_wmac_setup(void)
        ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
 }
 
+static int ar955x_wmac_reset(void)
+{
+       int i;
+
+       /* Try to wait for WMAC DDR activity to stop */
+       for (i = 0; i < 10; i++) {
+               if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
+                     QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
+                       break;
+
+               udelay(10);
+       }
+
+       ath79_device_reset_set(QCA955X_RESET_RTC);
+       udelay(10);
+       ath79_device_reset_clear(QCA955X_RESET_RTC);
+       udelay(10);
+
+       return 0;
+}
+
 static void qca955x_wmac_setup(void)
 {
        u32 t;
@@ -181,6 +202,8 @@ static void qca955x_wmac_setup(void)
                ath79_wmac_data.is_clk_25mhz = false;
        else
                ath79_wmac_data.is_clk_25mhz = true;
+
+       ath79_wmac_data.external_reset = ar955x_wmac_reset;
 }
 
 #define AR93XX_WMAC_SIZE \
--- a/arch/mips/ath79/common.h
+++ b/arch/mips/ath79/common.h
@@ -19,6 +19,8 @@
 #define ATH79_MEM_SIZE_MIN     (2 * 1024 * 1024)
 #define ATH79_MEM_SIZE_MAX     (256 * 1024 * 1024)
 
+extern void __iomem *ath79_ddr_base;
+
 void ath79_clocks_init(void);
 unsigned long ath79_get_sys_clk_rate(const char *id);