OpenWrt – Diff between revs 2 and 3

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Line 35... Line 35...
35   35  
36 #ifndef MT6575_SD_H 36 #ifndef MT6575_SD_H
Line 37... Line 37...
37 #define MT6575_SD_H 37 #define MT6575_SD_H
-   38  
38   39 #include <linux/bitops.h>
Line 39... Line 40...
39 #include <linux/bitops.h> 40 #include <linux/interrupt.h>
Line 40... Line 41...
40 #include <linux/mmc/host.h> 41 #include <linux/mmc/host.h>
41   42  
42 // #include <mach/mt6575_reg_base.h> /* --- by chhung */ 43 // #include <mach/mt6575_reg_base.h> /* --- by chhung */
43   44  
Line 44... Line 45...
44 /*--------------------------------------------------------------------------*/ 45 /*--------------------------------------------------------------------------*/
45 /* Common Macro */ 46 /* Common Macro */
46 /*--------------------------------------------------------------------------*/ 47 /*--------------------------------------------------------------------------*/
47 #define REG_ADDR(x) (base + OFFSET_##x) 48 #define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
Line 86... Line 87...
86   87  
87 #define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */ 88 #define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
Line 88... Line 89...
88 #define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */ 89 #define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
89   90  
90 enum { 91 enum {
91 RESP_NONE = 0, 92 RESP_NONE = 0,
92 RESP_R1, 93 RESP_R1,
93 RESP_R2, 94 RESP_R2,
94 RESP_R3, 95 RESP_R3,
95 RESP_R4, 96 RESP_R4,
96 RESP_R5, 97 RESP_R5,
97 RESP_R6, 98 RESP_R6,
98 RESP_R7, 99 RESP_R7,
Line 99... Line 100...
99 RESP_R1B 100 RESP_R1B
100 }; 101 };
101   102  
Line 251... Line 252...
251 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 252 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
252 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 253 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
253 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 254 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
254 #define MSDC_PS_DAT (0xff << 16) /* R */ 255 #define MSDC_PS_DAT (0xff << 16) /* R */
255 #define MSDC_PS_CMD (0x1 << 24) /* R */ 256 #define MSDC_PS_CMD (0x1 << 24) /* R */
256 #define MSDC_PS_WP (0x1UL << 31) /* R */ 257 #define MSDC_PS_WP (0x1UL<< 31) /* R */
Line 257... Line 258...
257   258  
258 /* MSDC_INT mask */ 259 /* MSDC_INT mask */
259 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 260 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
260 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 261 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
Line 292... Line 293...
292 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 293 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
Line 293... Line 294...
293   294  
294 /* MSDC_FIFOCS mask */ 295 /* MSDC_FIFOCS mask */
295 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 296 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
296 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 297 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
Line 297... Line 298...
297 #define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */ 298 #define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
298   299  
299 /* SDC_CFG mask */ 300 /* SDC_CFG mask */
300 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 301 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
301 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 302 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
302 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 303 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
303 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 304 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
304 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 305 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
Line 305... Line 306...
305 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 306 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
306 #define SDC_CFG_DTOC (0xffUL << 24) /* RW */ 307 #define SDC_CFG_DTOC (0xffUL << 24) /* RW */
Line 312... Line 313...
312 #define SDC_CMD_DTYP (0x3 << 11) /* RW */ 313 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
313 #define SDC_CMD_DTYP (0x3 << 11) /* RW */ 314 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
314 #define SDC_CMD_RW (0x1 << 13) /* RW */ 315 #define SDC_CMD_RW (0x1 << 13) /* RW */
315 #define SDC_CMD_STOP (0x1 << 14) /* RW */ 316 #define SDC_CMD_STOP (0x1 << 14) /* RW */
316 #define SDC_CMD_GOIRQ (0x1 << 15) /* RW */ 317 #define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
317 #define SDC_CMD_BLKLEN (0xfff << 16) /* RW */ 318 #define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
318 #define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */ 319 #define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
319 #define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */ 320 #define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
Line 320... Line 321...
320   321  
321 /* SDC_STS mask */ 322 /* SDC_STS mask */
Line 394... Line 395...
394 #define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */ 395 #define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
395 #define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */ 396 #define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
396 #define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */ 397 #define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
397 #define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */ 398 #define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
398 #define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */ 399 #define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
399 #define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */ 400 #define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
Line 400... Line 401...
400   401  
401 /* MSDC_PAD_CTL1 mask */ 402 /* MSDC_PAD_CTL1 mask */
402 #define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */ 403 #define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
403 #define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */ 404 #define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
404 #define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */ 405 #define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
405 #define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */ 406 #define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
406 #define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */ 407 #define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
407 #define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */ 408 #define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
408 #define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */ 409 #define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
409 #define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */ 410 #define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
Line 410... Line 411...
410 #define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */ 411 #define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
411   412  
412 /* MSDC_PAD_CTL2 mask */ 413 /* MSDC_PAD_CTL2 mask */
413 #define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */ 414 #define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
414 #define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */ 415 #define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
415 #define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */ 416 #define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
416 #define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */ 417 #define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
417 #define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */ 418 #define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
418 #define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */ 419 #define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
419 #define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */ 420 #define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
Line 420... Line 421...
420 #define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */ 421 #define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
421 #define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */ 422 #define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
422   423  
423 /* MSDC_PAD_TUNE mask */ 424 /* MSDC_PAD_TUNE mask */
Line 436... Line 437...
436 #define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */ 437 #define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
437 #define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */ 438 #define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
438 #define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */ 439 #define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
439 #define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */ 440 #define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
Line 440... Line 441...
440   441  
441 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10) 442 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
442 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 443 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
443 #define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6) 444 #define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
444 #define CARD_READY_FOR_DATA (1 << 8) 445 #define CARD_READY_FOR_DATA (1<<8)
Line 445... Line 446...
445 #define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) 446 #define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
446   447  
447 /*--------------------------------------------------------------------------*/ 448 /*--------------------------------------------------------------------------*/
448 /* Descriptor Structure */ 449 /* Descriptor Structure */
449 /*--------------------------------------------------------------------------*/ 450 /*--------------------------------------------------------------------------*/
450 struct gpd { 451 typedef struct {
451 u32 hwo:1; /* could be changed by hw */ 452 u32 hwo:1; /* could be changed by hw */
452 u32 bdp:1; 453 u32 bdp:1;
453 u32 rsv0:6; 454 u32 rsv0:6;
454 u32 chksum:8; 455 u32 chksum:8;
455 u32 intr:1; 456 u32 intr:1;
456 u32 rsv1:15; 457 u32 rsv1:15;
457 void *next; 458 void *next;
458 void *ptr; 459 void *ptr;
459 u32 buflen:16; 460 u32 buflen:16;
460 u32 extlen:8; 461 u32 extlen:8;
461 u32 rsv2:8; 462 u32 rsv2:8;
462 u32 arg; 463 u32 arg;
463 u32 blknum; 464 u32 blknum;
464 u32 cmd; 465 u32 cmd;
465 }; 466 } gpd_t;
466   467  
467 struct bd { 468 typedef struct {
468 u32 eol:1; 469 u32 eol:1;
469 u32 rsv0:7; 470 u32 rsv0:7;
470 u32 chksum:8; 471 u32 chksum:8;
471 u32 rsv1:1; 472 u32 rsv1:1;
472 u32 blkpad:1; 473 u32 blkpad:1;
473 u32 dwpad:1; 474 u32 dwpad:1;
474 u32 rsv2:13; 475 u32 rsv2:13;
475 void *next; 476 void *next;
476 void *ptr; 477 void *ptr;
477 u32 buflen:16; 478 u32 buflen:16;
Line 478... Line 479...
478 u32 rsv3:16; 479 u32 rsv3:16;
479 }; 480 } bd_t;
480   481  
Line 833... Line 793...
833   793 } msdc_version_reg;
834 struct msdc_eco_ver_reg { 794 typedef struct {
835 u32 val; 795 u32 val;
836 }; 796 } msdc_eco_ver_reg;
837   797  
838 struct msdc_regs { 798 struct msdc_regs {
839 struct msdc_cfg_reg msdc_cfg; /* base+0x00h */ 799 msdc_cfg_reg msdc_cfg; /* base+0x00h */
840 struct msdc_iocon_reg msdc_iocon; /* base+0x04h */ 800 msdc_iocon_reg msdc_iocon; /* base+0x04h */
841 struct msdc_ps_reg msdc_ps; /* base+0x08h */ 801 msdc_ps_reg msdc_ps; /* base+0x08h */
842 struct msdc_int_reg msdc_int; /* base+0x0ch */ 802 msdc_int_reg msdc_int; /* base+0x0ch */
843 struct msdc_inten_reg msdc_inten; /* base+0x10h */ 803 msdc_inten_reg msdc_inten; /* base+0x10h */
844 struct msdc_fifocs_reg msdc_fifocs; /* base+0x14h */ 804 msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
845 struct msdc_txdat_reg msdc_txdat; /* base+0x18h */ 805 msdc_txdat_reg msdc_txdat; /* base+0x18h */
846 struct msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */ 806 msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
847 u32 rsv1[4]; 807 u32 rsv1[4];
848 struct sdc_cfg_reg sdc_cfg; /* base+0x30h */ 808 sdc_cfg_reg sdc_cfg; /* base+0x30h */
849 struct sdc_cmd_reg sdc_cmd; /* base+0x34h */ 809 sdc_cmd_reg sdc_cmd; /* base+0x34h */
850 struct sdc_arg_reg sdc_arg; /* base+0x38h */ 810 sdc_arg_reg sdc_arg; /* base+0x38h */
851 struct sdc_sts_reg sdc_sts; /* base+0x3ch */ 811 sdc_sts_reg sdc_sts; /* base+0x3ch */
852 struct sdc_resp0_reg sdc_resp0; /* base+0x40h */ 812 sdc_resp0_reg sdc_resp0; /* base+0x40h */
853 struct sdc_resp1_reg sdc_resp1; /* base+0x44h */ 813 sdc_resp1_reg sdc_resp1; /* base+0x44h */
854 struct sdc_resp2_reg sdc_resp2; /* base+0x48h */ 814 sdc_resp2_reg sdc_resp2; /* base+0x48h */
855 struct sdc_resp3_reg sdc_resp3; /* base+0x4ch */ 815 sdc_resp3_reg sdc_resp3; /* base+0x4ch */
856 struct sdc_blknum_reg sdc_blknum; /* base+0x50h */ 816 sdc_blknum_reg sdc_blknum; /* base+0x50h */
857 u32 rsv2[1]; 817 u32 rsv2[1];
858 struct sdc_csts_reg sdc_csts; /* base+0x58h */ 818 sdc_csts_reg sdc_csts; /* base+0x58h */
859 struct sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */ 819 sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
860 struct sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */ 820 sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
861 u32 rsv3[3]; 821 u32 rsv3[3];
862 struct emmc_cfg0_reg emmc_cfg0; /* base+0x70h */ 822 emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
863 struct emmc_cfg1_reg emmc_cfg1; /* base+0x74h */ 823 emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
864 struct emmc_sts_reg emmc_sts; /* base+0x78h */ 824 emmc_sts_reg emmc_sts; /* base+0x78h */
865 struct emmc_iocon_reg emmc_iocon; /* base+0x7ch */ 825 emmc_iocon_reg emmc_iocon; /* base+0x7ch */
866 struct msdc_acmd_resp_reg acmd_resp; /* base+0x80h */ 826 msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
867 struct msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */ 827 msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
868 struct msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */ 828 msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
869 u32 rsv4[1]; 829 u32 rsv4[1];
870 struct msdc_dma_sa_reg dma_sa; /* base+0x90h */ 830 msdc_dma_sa_reg dma_sa; /* base+0x90h */
871 struct msdc_dma_ca_reg dma_ca; /* base+0x94h */ 831 msdc_dma_ca_reg dma_ca; /* base+0x94h */
872 struct msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */ 832 msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
873 struct msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */ 833 msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
874 struct msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */ 834 msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
875 struct msdc_dbg_out_reg dbg_out; /* base+0xa4h */ 835 msdc_dbg_out_reg dbg_out; /* base+0xa4h */
876 u32 rsv5[2]; 836 u32 rsv5[2];
877 u32 patch0; /* base+0xb0h */ 837 u32 patch0; /* base+0xb0h */
878 u32 patch1; /* base+0xb4h */ 838 u32 patch1; /* base+0xb4h */
879 u32 rsv6[10]; 839 u32 rsv6[10];
880 struct msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */ 840 msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
881 struct msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */ 841 msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
882 struct msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */ 842 msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
883 struct msdc_pad_tune_reg pad_tune; /* base+0xech */ 843 msdc_pad_tune_reg pad_tune; /* base+0xech */
884 struct msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */ 844 msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
-   845 msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
-   846 msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
-   847 u32 rsv7[1];
-   848 msdc_version_reg version; /* base+0x100h */
-   849 msdc_eco_ver_reg eco_ver; /* base+0x104h */
-   850 };
-   851  
885 struct msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */ 852 struct scatterlist_ex {
-   853 u32 cmd;
-   854 u32 arg;
-   855 u32 sglen;
-   856 struct scatterlist *sg;
-   857 };
Line 886... Line 858...
886 struct msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */ 858  
-   859 #define DMA_FLAG_NONE (0x00000000)
-   860 #define DMA_FLAG_EN_CHKSUM (0x00000001)
887 u32 rsv7[1]; 861 #define DMA_FLAG_PAD_BLOCK (0x00000002)
-   862 #define DMA_FLAG_PAD_DWORD (0x00000004)
888 struct msdc_version_reg version; /* base+0x100h */ 863  
-   864 struct msdc_dma {
889 struct msdc_eco_ver_reg eco_ver; /* base+0x104h */ 865 u32 flags; /* flags */
-   866 u32 xfersz; /* xfer size in bytes */
-   867 u32 sglen; /* size of scatter list */
-   868 u32 blklen; /* block size */
-   869 struct scatterlist *sg; /* I/O scatter list */
-   870 struct scatterlist_ex *esg; /* extended I/O scatter list */
-   871 u8 mode; /* dma mode */
-   872 u8 burstsz; /* burst size */
890 }; 873 u8 intr; /* dma done interrupt */
891   874 u8 padding; /* padding */
892 struct msdc_dma { 875 u32 cmd; /* enhanced mode command */
893 u32 sglen; /* size of scatter list */ 876 u32 arg; /* enhanced mode arg */
894 struct scatterlist *sg; /* I/O scatter list */ 877 u32 rsp; /* enhanced mode command response */
-   878 u32 autorsp; /* auto command response */
-   879  
895 u8 mode; /* dma mode */ 880 gpd_t *gpd; /* pointer to gpd array */
Line 896... Line 881...
896   881 bd_t *bd; /* pointer to bd array */
897 struct gpd *gpd; /* pointer to gpd array */ -  
898 struct bd *bd; /* pointer to bd array */ -  
899 dma_addr_t gpd_addr; /* the physical address of gpd array */ -  
900 dma_addr_t bd_addr; /* the physical address of bd array */ -  
901 }; -  
902   -  
903 struct msdc_host { -  
904 struct msdc_hw *hw; -  
905   -  
906 struct mmc_host *mmc; /* mmc structure */ -  
907 struct mmc_command *cmd; -  
908 struct mmc_data *data; -  
909 struct mmc_request *mrq; -  
910 int cmd_rsp; -  
911   -  
912 int error; -  
913 spinlock_t lock; /* mutex */ -  
914 struct semaphore sem; -  
915   -  
916 u32 blksz; /* host block size */ -  
917 void __iomem *base; /* host base address */ -  
918 int id; /* host id */ -  
919 int pwr_ref; /* core power reference count */ -  
920   -  
921 u32 xfer_size; /* total transferred size */ -  
922   -  
923 struct msdc_dma dma; /* dma channel */ -  
924 u32 dma_xfer_size; /* dma transfer size in bytes */ -  
925   -  
926 u32 timeout_ns; /* data timeout ns */ -  
927 u32 timeout_clks; /* data timeout clks */ -  
928   -  
929 int irq; /* host interrupt */ -  
930   -  
931 struct delayed_work card_delaywork; -  
932   -  
933 struct completion cmd_done; -  
934 struct completion xfer_done; -  
935 struct pm_message pm_state; -  
936   -  
937 u32 mclk; /* mmc subsystem clock */ -  
938 u32 hclk; /* host clock speed */ -  
939 u32 sclk; /* SD/MS clock speed */ -  
940 u8 core_clkon; /* Host core clock on ? */ -  
941 u8 card_clkon; /* Card clock on ? */ -  
942 u8 core_power; /* core power */ -  
943 u8 power_mode; /* host power mode */ -  
944 u8 card_inserted; /* card inserted ? */ -  
945 u8 suspend; /* host suspended ? */ -  
946 u8 app_cmd; /* for app command */ -  
947 u32 app_cmd_arg; -  
948 }; -  
949   882 dma_addr_t gpd_addr; /* the physical address of gpd array */
950 #define sdr_read8(reg) readb(reg) 883 dma_addr_t bd_addr; /* the physical address of bd array */
951 #define sdr_read32(reg) readl(reg) -  
952 #define sdr_write8(reg, val) writeb(val, reg) -  
953 #define sdr_write32(reg, val) writel(val, reg) -  
954   -  
Line -... Line 884...
-   884 u32 used_gpd; /* the number of used gpd elements */
-   885 u32 used_bd; /* the number of used bd elements */
-   886 };
-   887  
-   888 struct msdc_host
-   889 {
-   890 struct msdc_hw *hw;
-   891  
-   892 struct mmc_host *mmc; /* mmc structure */
955 static inline void sdr_set_bits(void __iomem *reg, u32 bs) 893 struct mmc_command *cmd;
-   894 struct mmc_data *data;
-   895 struct mmc_request *mrq;
-   896 int cmd_rsp;
-   897 int cmd_rsp_done;
-   898 int cmd_r1b_done;
-   899  
-   900 int error;
-   901 spinlock_t lock; /* mutex */
-   902 struct semaphore sem;
-   903  
-   904 u32 blksz; /* host block size */
-   905 u32 base; /* host base address */
-   906 int id; /* host id */
-   907 int pwr_ref; /* core power reference count */
-   908  
-   909 u32 xfer_size; /* total transferred size */
-   910  
-   911 struct msdc_dma dma; /* dma channel */
-   912 u32 dma_addr; /* dma transfer address */
-   913 u32 dma_left_size; /* dma transfer left size */
-   914 u32 dma_xfer_size; /* dma transfer size in bytes */
956 { 915 int dma_xfer; /* dma transfer mode */
-   916  
-   917 u32 timeout_ns; /* data timeout ns */
957 u32 val = readl(reg); 918 u32 timeout_clks; /* data timeout clks */
-   919  
-   920 atomic_t abort; /* abort transfer */
-   921  
Line 958... Line 922...
958   922 int irq; /* host interrupt */
959 val |= bs; 923  
-   924 struct tasklet_struct card_tasklet;
-   925 #if 0
-   926 struct work_struct card_workqueue;
-   927 #else
-   928 struct delayed_work card_delaywork;
-   929 #endif
-   930  
-   931 struct completion cmd_done;
-   932 struct completion xfer_done;
-   933 struct pm_message pm_state;
-   934  
-   935 u32 mclk; /* mmc subsystem clock */
-   936 u32 hclk; /* host clock speed */
-   937 u32 sclk; /* SD/MS clock speed */
-   938 u8 core_clkon; /* Host core clock on ? */
960 writel(val, reg); 939 u8 card_clkon; /* Card clock on ? */
Line 961... Line 940...
961 } 940 u8 core_power; /* core power */
962   941 u8 power_mode; /* host power mode */
963 static inline void sdr_clr_bits(void __iomem *reg, u32 bs) 942 u8 card_inserted; /* card inserted ? */
964 { -  
965 u32 val = readl(reg); -  
966   -  
967 val &= ~bs; -  
968 writel(val, reg); -  
Line -... Line 943...
-   943 u8 suspend; /* host suspended ? */
-   944 u8 reserved;
969 } 945 u8 app_cmd; /* for app command */
-   946 u32 app_cmd_arg;
-   947 u64 starttime;
970   948 };
971 static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val) 949  
-   950 static inline unsigned int uffs(unsigned int x)
-   951 {
-   952 unsigned int r = 1;
972 { 953  
-   954 if (!x)
-   955 return 0;
-   956 if (!(x & 0xffff)) {
-   957 x >>= 16;
-   958 r += 16;
-   959 }
-   960 if (!(x & 0xff)) {
-   961 x >>= 8;
-   962 r += 8;
-   963 }
-   964 if (!(x & 0xf)) {
-   965 x >>= 4;
973 unsigned int tv = readl(reg); 966 r += 4;
-   967 }
-   968 if (!(x & 3)) {
-   969 x >>= 2;
-   970 r += 2;
-   971 }
-   972 if (!(x & 1)) {
-   973 x >>= 1;
-   974 r += 1;
-   975 }
-   976 return r;
-   977 }
-   978 #define sdr_read8(reg) __raw_readb(reg)
-   979 #define sdr_read16(reg) __raw_readw(reg)
-   980 #define sdr_read32(reg) __raw_readl(reg)
-   981 #define sdr_write8(reg,val) __raw_writeb(val,reg)
-   982 #define sdr_write16(reg,val) __raw_writew(val,reg)
-   983 #define sdr_write32(reg,val) __raw_writel(val,reg)
-   984  
-   985 #define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
-   986 #define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
-   987  
-   988 #define sdr_set_field(reg,field,val) \
Line 974... Line 989...
974   989 do { \
-   990 volatile unsigned int tv = sdr_read32(reg); \