OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
Line 7... Line 7...
7   7  
8 / { 8 / {
9 compatible = "zbtlink,zbt-wg2626", "mediatek,mt7621-soc"; 9 compatible = "zbtlink,zbt-wg2626", "mediatek,mt7621-soc";
Line 10... Line -...
10 model = "ZBT-WG2626"; -  
11   -  
12 aliases { -  
13 led-boot = &led_status; -  
14 led-failsafe = &led_status; -  
15 led-running = &led_status; -  
16 led-upgrade = &led_status; -  
17 }; 10 model = "ZBT-WG2626";
18   11  
19 memory@0 { 12 memory@0 {
20 device_type = "memory"; 13 device_type = "memory";
Line 29... Line 22...
29 i2c@900 { 22 i2c@900 {
30 status = "okay"; 23 status = "okay";
31 }; 24 };
32 }; 25 };
Line 33... Line 26...
33   26  
34 keys { 27 gpio-keys-polled {
-   28 compatible = "gpio-keys-polled";
-   29 #address-cells = <1>;
35 compatible = "gpio-keys-polled"; 30 #size-cells = <0>;
Line 36... Line 31...
36 poll-interval = <20>; 31 poll-interval = <20>;
37   32  
38 reset { 33 reset {
39 label = "reset"; 34 label = "reset";
40 gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; 35 gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
41 linux,code = <KEY_RESTART>; 36 linux,code = <KEY_RESTART>;
Line 42... Line 37...
42 }; 37 };
43 }; 38 };
Line 44... Line 39...
44   39  
45 leds { 40 gpio-leds {
46 compatible = "gpio-leds"; 41 compatible = "gpio-leds";
47   42  
48 led_status: status { 43 status {
49 label = "zbt-wg2626:green:status"; 44 label = "zbt-wg2626:green:status";
Line 58... Line 53...
58   53  
59 &spi0 { 54 &spi0 {
Line 60... Line 55...
60 status = "okay"; 55 status = "okay";
-   56  
-   57 m25p80@0 {
61   58 #address-cells = <1>;
62 m25p80@0 { 59 #size-cells = <1>;
63 compatible = "jedec,spi-nor"; 60 compatible = "jedec,spi-nor";
-   61 reg = <0>;
-   62 spi-max-frequency = <10000000>;
-   63 m25p,chunked-io = <32>;
-   64  
-   65 partition@0 {
-   66 label = "u-boot";
-   67 reg = <0x0 0x30000>;
-   68 read-only;
-   69 };
-   70  
-   71 partition@30000 {
-   72 label = "u-boot-env";
-   73 reg = <0x30000 0x10000>;
Line 64... Line -...
64 reg = <0>; -  
65 spi-max-frequency = <10000000>; -  
66   -  
67 partitions { -  
68 compatible = "fixed-partitions"; -  
69 #address-cells = <1>; -  
70 #size-cells = <1>; -  
71   -  
72 partition@0 { -  
73 label = "u-boot"; -  
74 reg = <0x0 0x30000>; -  
75 read-only; -  
76 }; -  
77   -  
78 partition@30000 { -  
79 label = "u-boot-env"; -  
80 reg = <0x30000 0x10000>; -  
81 read-only; 74 read-only;
82 }; 75 };
83   76  
84 factory: partition@40000 { 77 factory: partition@40000 {
85 label = "factory"; 78 label = "factory";
86 reg = <0x40000 0x10000>; 79 reg = <0x40000 0x10000>;
87 read-only; 80 read-only;
88 }; -  
89   81 };
90 partition@50000 { 82  
91 compatible = "denx,uimage"; -  
92 label = "firmware"; 83 partition@50000 {
93 reg = <0x50000 0xfb0000>; 84 label = "firmware";
94 }; 85 reg = <0x50000 0xfb0000>;
Line 95... Line 86...
95 }; 86 };
96 }; 87 };
97 }; -  
Line 98... Line 88...
98   88 };
99 &pcie { 89  
100 status = "okay"; 90 &pcie {
-   91 status = "okay";
101 }; 92  
102   93 pcie0 {
-   94 mt76@0,0 {
103 &pcie0 { 95 reg = <0x0000 0 0 0 0>;
104 mt76@0,0 { -  
Line 105... Line 96...
105 reg = <0x0000 0 0 0 0>; 96 device_type = "pci";
106 mediatek,mtd-eeprom = <&factory 0x8000>; 97 mediatek,mtd-eeprom = <&factory 0x8000>;
107 ieee80211-freq-limit = <5000000 6000000>; 98 ieee80211-freq-limit = <5000000 6000000>;
-   99 };
108 }; 100 };
109 }; 101  
-   102 pcie1 {
110   103 mt76@1,0 {
111 &pcie1 { 104 reg = <0x0000 0 0 0 0>;
Line 112... Line 105...
112 mt76@0,0 { 105 device_type = "pci";
113 reg = <0x0000 0 0 0 0>; 106 mediatek,mtd-eeprom = <&factory 0x0000>;