OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
Line 22... Line 22...
22 reg = <0x51>; 22 reg = <0x51>;
23 }; 23 };
24 }; 24 };
25 }; 25 };
Line 26... Line 26...
26   26  
27 keys { 27 gpio-keys-polled {
-   28 compatible = "gpio-keys-polled";
-   29 #address-cells = <1>;
28 compatible = "gpio-keys-polled"; 30 #size-cells = <0>;
Line 29... Line 31...
29 poll-interval = <20>; 31 poll-interval = <20>;
30   32  
31 reset { 33 reset {
Line 42... Line 44...
42   44  
43 &spi0 { 45 &spi0 {
Line 44... Line 46...
44 status = "okay"; 46 status = "okay";
-   47  
-   48 m25p80@0 {
45   49 #address-cells = <1>;
46 m25p80@0 { 50 #size-cells = <1>;
47 compatible = "jedec,spi-nor"; 51 compatible = "jedec,spi-nor";
-   52 reg = <0>;
Line 48... Line -...
48 reg = <0>; -  
49 spi-max-frequency = <10000000>; -  
50   -  
51 partitions { -  
52 compatible = "fixed-partitions"; -  
53 #address-cells = <1>; 53 spi-max-frequency = <10000000>;
54 #size-cells = <1>; 54 m25p,chunked-io = <32>;
55   55  
56 partition@0 { 56 partition@0 {
57 label = "u-boot"; 57 label = "u-boot";
Line 58... Line 58...
58 reg = <0x0 0x30000>; 58 reg = <0x0 0x30000>;
59 read-only; 59 read-only;
60 }; 60 };
61   61  
62 partition@30000 { 62 partition@30000 {
Line 63... Line 63...
63 label = "u-boot-env"; 63 label = "u-boot-env";
64 reg = <0x30000 0x10000>; 64 reg = <0x30000 0x10000>;
65 read-only; 65 read-only;
66 }; 66 };
Line 67... Line 67...
67   67  
68 factory: partition@40000 { -  
69 label = "factory"; 68 factory: partition@40000 {
70 reg = <0x40000 0x10000>; 69 label = "factory";
71 }; -  
72   70 reg = <0x40000 0x10000>;
73 partition@50000 { 71 };
74 compatible = "denx,uimage"; 72  
Line 75... Line 73...
75 label = "firmware"; 73 partition@50000 {
76 reg = <0x50000 0xfb0000>; 74 label = "firmware";
77 }; -  
Line 78... Line 75...
78 }; 75 reg = <0x50000 0xfb0000>;
79 }; 76 };
80 }; 77 };
-   78 };
81   79  
82 &pcie { 80 &pcie {
83 status = "okay"; 81 status = "okay";
-   82  
84 }; 83 pcie0 {
85   -  
Line 86... Line 84...
86 &pcie0 { 84 mt76@0,0 {
87 mt76@0,0 { 85 reg = <0x0000 0 0 0 0>;
88 reg = <0x0000 0 0 0 0>; 86 device_type = "pci";
-   87 mediatek,mtd-eeprom = <&factory 0x8000>;
89 mediatek,mtd-eeprom = <&factory 0x8000>; 88 ieee80211-freq-limit = <5000000 6000000>;
90 ieee80211-freq-limit = <5000000 6000000>; 89 mtd-mac-address = <&factory 0xe000>;
91 mtd-mac-address = <&factory 0xe000>; 90 };
-   91 };
92 }; 92  
93 }; 93 pcie1 {
Line 94... Line 94...
94   94 mt76@1,0 {
95 &pcie1 { 95 reg = <0x0000 0 0 0 0>;