OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
Line 7... Line 7...
7   7  
8 / { 8 / {
9 compatible = "d-team,pbr-m1", "mediatek,mt7621-soc"; 9 compatible = "d-team,pbr-m1", "mediatek,mt7621-soc";
Line 10... Line -...
10 model = "PBR-M1"; -  
11   -  
12 aliases { -  
13 led-boot = &led_sys; -  
14 led-failsafe = &led_sys; -  
15 led-running = &led_sys; -  
16 led-upgrade = &led_sys; -  
17 }; 10 model = "PBR-M1";
18   11  
19 memory@0 { 12 memory@0 {
20 device_type = "memory"; 13 device_type = "memory";
Line 35... Line 28...
35 reg = <0x51>; 28 reg = <0x51>;
36 }; 29 };
37 }; 30 };
38 }; 31 };
Line 39... Line 32...
39   32  
40 leds { 33 gpio-leds {
Line 41... Line 34...
41 compatible = "gpio-leds"; 34 compatible = "gpio-leds";
42   35  
43 power { 36 power {
44 label = "pbr-m1:blue:power"; -  
45 gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; 37 label = "pbr-m1:blue:power";
Line 46... Line 38...
46 default-state = "on"; 38 gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
47 }; 39 };
48   40  
49 led_sys: sys { 41 sys {
Line 50... Line 42...
50 label = "pbr-m1:blue:sys"; 42 label = "pbr-m1:blue:sys";
Line 65... Line 57...
65 label = "pbr-m1:blue:wlan5g"; 57 label = "pbr-m1:blue:wlan5g";
66 gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; 58 gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
67 }; 59 };
68 }; 60 };
Line 69... Line 61...
69   61  
70 keys { 62 gpio-keys-polled {
-   63 compatible = "gpio-keys-polled";
-   64 #address-cells = <1>;
71 compatible = "gpio-keys-polled"; 65 #size-cells = <0>;
Line 72... Line 66...
72 poll-interval = <20>; 66 poll-interval = <20>;
73   67  
74 reset { 68 reset {
Line 107... Line 101...
107 }; 101 };
108 }; 102 };
Line 109... Line 103...
109   103  
110 &sdhci { 104 &sdhci {
-   105 status = "okay";
-   106 pinctrl-names = "default";
111 status = "okay"; 107 pinctrl-0 = <&sdhci_pins>;
Line 112... Line 108...
112 }; 108 };
113   109  
Line 114... Line 110...
114 &spi0 { 110 &spi0 {
-   111 status = "okay";
-   112  
115 status = "okay"; 113 m25p80@0 {
116   114 #address-cells = <1>;
117 m25p80@0 { 115 #size-cells = <1>;
-   116 compatible = "jedec,spi-nor";
Line 118... Line -...
118 compatible = "jedec,spi-nor"; -  
119 reg = <0>; -  
120 spi-max-frequency = <10000000>; -  
121   -  
122 partitions { -  
123 compatible = "fixed-partitions"; 117 reg = <0>;
124 #address-cells = <1>; 118 spi-max-frequency = <10000000>;
125 #size-cells = <1>; 119 m25p,chunked-io = <32>;
126   120  
127 partition@0 { 121 partition@0 {
Line 128... Line 122...
128 label = "u-boot"; 122 label = "u-boot";
129 reg = <0x0 0x30000>; 123 reg = <0x0 0x30000>;
130 read-only; 124 read-only;
131 }; 125 };
132   126  
Line 133... Line 127...
133 partition@30000 { 127 partition@30000 {
134 label = "u-boot-env"; 128 label = "u-boot-env";
135 reg = <0x30000 0x10000>; 129 reg = <0x30000 0x10000>;
136 read-only; 130 read-only;
137 }; 131 };
Line 138... Line 132...
138   132  
139 factory: partition@40000 { -  
140 label = "factory"; 133 factory: partition@40000 {
141 reg = <0x40000 0x10000>; 134 label = "factory";
142 read-only; -  
143 }; 135 reg = <0x40000 0x10000>;
144   136 read-only;
145 partition@50000 { 137 };
Line 146... Line 138...
146 compatible = "denx,uimage"; 138  
147 label = "firmware"; 139 partition@50000 {
148 reg = <0x50000 0xfb0000>; -  
Line 149... Line 140...
149 }; 140 label = "firmware";
150 }; 141 reg = <0x50000 0xfb0000>;
151 }; 142 };
-   143 };
152 }; 144 };
153   145  
-   146 &pcie {
154 &pcie { 147 status = "okay";
155 status = "okay"; -  
Line 156... Line 148...
156 }; 148  
157   149 pcie0 {
158 &pcie0 { 150 mt76@0,0 {
-   151 reg = <0x0000 0 0 0 0>;
159 mt76@0,0 { 152 device_type = "pci";
-   153 mediatek,mtd-eeprom = <&factory 0x8000>;
160 reg = <0x0000 0 0 0 0>; 154 ieee80211-freq-limit = <5000000 6000000>;
161 mediatek,mtd-eeprom = <&factory 0x8000>; 155 };
Line 162... Line 156...
162 ieee80211-freq-limit = <5000000 6000000>; 156 };
163 }; 157