OpenWrt – Diff between revs 2 and 3

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Line 1... Line 1...
1 --- a/arch/mips/include/asm/r4kcache.h 1 --- a/arch/mips/include/asm/r4kcache.h
2 +++ b/arch/mips/include/asm/r4kcache.h 2 +++ b/arch/mips/include/asm/r4kcache.h
3 @@ -26,6 +26,38 @@ 3 @@ -25,6 +25,38 @@
4 extern void (*r4k_blast_dcache)(void); 4 extern void (*r4k_blast_dcache)(void);
5 extern void (*r4k_blast_icache)(void); 5 extern void (*r4k_blast_icache)(void);
Line 6... Line 6...
6 6
7 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2) 7 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
Line 37... Line 37...
37 +#endif 37 +#endif
38 + 38 +
39 /* 39 /*
40 * This macro return a properly sign-extended address suitable as base address 40 * This macro return a properly sign-extended address suitable as base address
41 * for indexed cache operations. Two issues here: 41 * for indexed cache operations. Two issues here:
42 @@ -99,6 +131,7 @@ static inline void flush_icache_line_ind 42 @@ -98,6 +130,7 @@ static inline void flush_icache_line_ind
43 static inline void flush_dcache_line_indexed(unsigned long addr) 43 static inline void flush_dcache_line_indexed(unsigned long addr)
44 { 44 {
45 __dflush_prologue 45 __dflush_prologue
46 + BCM4710_DUMMY_RREG(); 46 + BCM4710_DUMMY_RREG();
47 cache_op(Index_Writeback_Inv_D, addr); 47 cache_op(Index_Writeback_Inv_D, addr);
48 __dflush_epilogue 48 __dflush_epilogue
49 } 49 }
50 @@ -126,6 +159,7 @@ static inline void flush_icache_line(uns 50 @@ -125,6 +158,7 @@ static inline void flush_icache_line(uns
51 static inline void flush_dcache_line(unsigned long addr) 51 static inline void flush_dcache_line(unsigned long addr)
52 { 52 {
53 __dflush_prologue 53 __dflush_prologue
54 + BCM4710_DUMMY_RREG(); 54 + BCM4710_DUMMY_RREG();
55 cache_op(Hit_Writeback_Inv_D, addr); 55 cache_op(Hit_Writeback_Inv_D, addr);
56 __dflush_epilogue 56 __dflush_epilogue
57 } 57 }
58 @@ -133,6 +167,7 @@ static inline void flush_dcache_line(uns 58 @@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns
59 static inline void invalidate_dcache_line(unsigned long addr) 59 static inline void invalidate_dcache_line(unsigned long addr)
60 { 60 {
61 __dflush_prologue 61 __dflush_prologue
62 + BCM4710_DUMMY_RREG(); 62 + BCM4710_DUMMY_RREG();
63 cache_op(Hit_Invalidate_D, addr); 63 cache_op(Hit_Invalidate_D, addr);
64 __dflush_epilogue 64 __dflush_epilogue
65 } 65 }
66 @@ -206,6 +241,7 @@ static inline int protected_flush_icache 66 @@ -205,6 +240,7 @@ static inline int protected_flush_icache
67 #ifdef CONFIG_EVA 67 #ifdef CONFIG_EVA
68 return protected_cachee_op(Hit_Invalidate_I, addr); 68 return protected_cachee_op(Hit_Invalidate_I, addr);
69 #else 69 #else
70 + BCM4710_DUMMY_RREG(); 70 + BCM4710_DUMMY_RREG();
71 return protected_cache_op(Hit_Invalidate_I, addr); 71 return protected_cache_op(Hit_Invalidate_I, addr);
72 #endif 72 #endif
73 } 73 }
74 @@ -219,6 +255,7 @@ static inline int protected_flush_icache 74 @@ -218,6 +254,7 @@ static inline int protected_flush_icache
75 */ 75 */
76 static inline int protected_writeback_dcache_line(unsigned long addr) 76 static inline int protected_writeback_dcache_line(unsigned long addr)
77 { 77 {
78 + BCM4710_DUMMY_RREG(); 78 + BCM4710_DUMMY_RREG();
79 #ifdef CONFIG_EVA 79 #ifdef CONFIG_EVA
80 return protected_cachee_op(Hit_Writeback_Inv_D, addr); 80 return protected_cachee_op(Hit_Writeback_Inv_D, addr);
81 #else 81 #else
82 @@ -576,8 +613,51 @@ static inline void invalidate_tcache_pag 82 @@ -575,8 +612,51 @@ static inline void invalidate_tcache_pag
83 : "r" (base), \ 83 : "r" (base), \
84 "i" (op)); 84 "i" (op));
Line 85... Line 85...
85 85
86 +static inline void blast_dcache(void) 86 +static inline void blast_dcache(void)
Line 130... Line 130...
130 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ 130 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
131 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \ 131 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
132 static inline void extra##blast_##pfx##cache##lsize(void) \ 132 static inline void extra##blast_##pfx##cache##lsize(void) \
133 { \ 133 { \
134 unsigned long start = INDEX_BASE; \ 134 unsigned long start = INDEX_BASE; \
135 @@ -589,6 +669,7 @@ static inline void extra##blast_##pfx##c 135 @@ -588,6 +668,7 @@ static inline void extra##blast_##pfx##c
136 \ 136 \
137 __##pfx##flush_prologue \ 137 __##pfx##flush_prologue \
138 \ 138 \
139 + war \ 139 + war \
140 for (ws = 0; ws < ws_end; ws += ws_inc) \ 140 for (ws = 0; ws < ws_end; ws += ws_inc) \
141 for (addr = start; addr < end; addr += lsize * 32) \ 141 for (addr = start; addr < end; addr += lsize * 32) \
142 cache##lsize##_unroll32(addr|ws, indexop); \ 142 cache##lsize##_unroll32(addr|ws, indexop); \
143 @@ -603,6 +684,7 @@ static inline void extra##blast_##pfx##c 143 @@ -602,6 +683,7 @@ static inline void extra##blast_##pfx##c
144 \ 144 \
145 __##pfx##flush_prologue \ 145 __##pfx##flush_prologue \
146 \ 146 \
147 + war \ 147 + war \
148 do { \ 148 do { \
149 cache##lsize##_unroll32(start, hitop); \ 149 cache##lsize##_unroll32(start, hitop); \
150 start += lsize * 32; \ 150 start += lsize * 32; \
151 @@ -621,6 +703,8 @@ static inline void extra##blast_##pfx##c 151 @@ -620,6 +702,8 @@ static inline void extra##blast_##pfx##c
152 current_cpu_data.desc.waybit; \ 152 current_cpu_data.desc.waybit; \
153 unsigned long ws, addr; \ 153 unsigned long ws, addr; \
154 \ 154 \
155 + war \ 155 + war \
156 + \ 156 + \
157 __##pfx##flush_prologue \ 157 __##pfx##flush_prologue \
158 \ 158 \
159 for (ws = 0; ws < ws_end; ws += ws_inc) \ 159 for (ws = 0; ws < ws_end; ws += ws_inc) \
160 @@ -630,26 +714,26 @@ static inline void extra##blast_##pfx##c 160 @@ -629,26 +713,26 @@ static inline void extra##blast_##pfx##c
161 __##pfx##flush_epilogue \ 161 __##pfx##flush_epilogue \
162 } 162 }
Line 163... Line 163...
163 163
164 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) 164 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
Line 202... Line 202...
202 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , ) 202 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
203 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , ) 203 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
Line 204... Line 204...
204 204
205 #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ 205 #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
206 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ 206 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
207 @@ -678,53 +762,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde 207 @@ -677,53 +761,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
Line 208... Line 208...
208 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) 208 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
209 209
210 /* build blast_xxx_range, protected_blast_xxx_range */ 210 /* build blast_xxx_range, protected_blast_xxx_range */
Line 264... Line 264...
264 + break; \ 264 + break; \
265 + addr += lsize; \ 265 + addr += lsize; \
266 } \ 266 } \
267 \ 267 \
268 __##pfx##flush_epilogue \ 268 __##pfx##flush_epilogue \
269 @@ -732,8 +786,8 @@ static inline void prot##extra##blast_## 269 @@ -731,8 +785,8 @@ static inline void prot##extra##blast_##
Line 270... Line 270...
270 270
Line 271... Line 271...
271 #ifndef CONFIG_EVA 271 #ifndef CONFIG_EVA
272 272
273 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, ) 273 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
274 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) 274 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
Line 275... Line 275...
275 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();) 275 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
Line 276... Line 276...
276 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , ) 276 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
277 277
Line 278... Line 278...
278 #else 278 #else
279 279
280 @@ -770,15 +824,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache 280 @@ -769,14 +823,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
Line 296... Line 296...
296 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) 296 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
297 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , ) 297 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
298 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();) 298 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
299 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , ) 299 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
Line 300... Line 300...
300 300
301 /* Currently, this is very specific to Loongson-3 */ -  
302 #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \ 301 #endif /* _ASM_R4KCACHE_H */
303 --- a/arch/mips/include/asm/stackframe.h 302 --- a/arch/mips/include/asm/stackframe.h
304 +++ b/arch/mips/include/asm/stackframe.h 303 +++ b/arch/mips/include/asm/stackframe.h
305 @@ -428,6 +428,10 @@ 304 @@ -428,6 +428,10 @@
306 eretnc 305 eretnc
Line 395... Line 394...
395 + r4k_blast_dcache = blast_dcache; 394 + r4k_blast_dcache = blast_dcache;
396 + else 395 + else
397 if (dc_lsize == 0) 396 if (dc_lsize == 0)
398 r4k_blast_dcache = (void *)cache_noop; 397 r4k_blast_dcache = (void *)cache_noop;
399 else if (dc_lsize == 16) 398 else if (dc_lsize == 16)
400 @@ -986,6 +998,8 @@ static void local_r4k_flush_cache_sigtra 399 @@ -955,6 +967,8 @@ static void local_r4k_flush_cache_sigtra
401 } 400 }
Line 402... Line 401...
402 401
403 R4600_HIT_CACHEOP_WAR_IMPL; 402 R4600_HIT_CACHEOP_WAR_IMPL;
404 + BCM4710_PROTECTED_FILL_TLB(addr); 403 + BCM4710_PROTECTED_FILL_TLB(addr);
405 + BCM4710_PROTECTED_FILL_TLB(addr + 4); 404 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
406 if (!cpu_has_ic_fills_f_dc) { 405 if (!cpu_has_ic_fills_f_dc) {
407 if (dc_lsize) 406 if (dc_lsize)
408 vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1)) 407 vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
409 @@ -1880,6 +1894,17 @@ static void coherency_setup(void) 408 @@ -1849,6 +1863,17 @@ static void coherency_setup(void)
410 * silly idea of putting something else there ... 409 * silly idea of putting something else there ...
411 */ 410 */
412 switch (current_cpu_type()) { 411 switch (current_cpu_type()) {
413 + case CPU_BMIPS3300: 412 + case CPU_BMIPS3300:
Line 422... Line 421...
422 + } 421 + }
423 + break; 422 + break;
424 case CPU_R4000PC: 423 case CPU_R4000PC:
425 case CPU_R4000SC: 424 case CPU_R4000SC:
426 case CPU_R4000MC: 425 case CPU_R4000MC:
427 @@ -1926,6 +1951,15 @@ void r4k_cache_init(void) 426 @@ -1895,6 +1920,15 @@ void r4k_cache_init(void)
428 extern void build_copy_page(void); 427 extern void build_copy_page(void);
429 struct cpuinfo_mips *c = &current_cpu_data; 428 struct cpuinfo_mips *c = &current_cpu_data;
Line 430... Line 429...
430 429
431 + /* Check if special workarounds are required */ 430 + /* Check if special workarounds are required */
Line 438... Line 437...
438 + bcm4710 = 0; 437 + bcm4710 = 0;
439 + 438 +
440 probe_pcache(); 439 probe_pcache();
441 probe_vcache(); 440 probe_vcache();
442 setup_scache(); 441 setup_scache();
443 @@ -2004,7 +2038,15 @@ void r4k_cache_init(void) 442 @@ -1972,7 +2006,15 @@ void r4k_cache_init(void)
444 */ 443 */
445 local_r4k___flush_cache_all(NULL); 444 local_r4k___flush_cache_all(NULL);
Line 446... Line 445...
446 445
447 +#ifdef CONFIG_BCM47XX 446 +#ifdef CONFIG_BCM47XX