OpenWrt – Diff between revs 2 and 3

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Line 120... Line 120...
120 }; 120 };
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121   121  
122 static struct at803x_platform_data fritz450E_at803x_data = { 122 static struct at803x_platform_data fritz450E_at803x_data = {
123 .disable_smarteee = 1, 123 .disable_smarteee = 1,
124 .has_reset_gpio = 1, -  
125 .override_sgmii_aneg = 1, 124 .has_reset_gpio = 1,
126 .reset_gpio = FRITZ450E_GPIO_PHY_RESET, 125 .reset_gpio = FRITZ450E_GPIO_PHY_RESET,
Line 127... Line 126...
127 }; 126 };
128   127  
129 static struct mdio_board_info fritz450E_mdio_info[] = { 128 static struct mdio_board_info fritz450E_mdio_info[] = {
130 { 129 {
131 .bus_id = "ag71xx-mdio.1", 130 .bus_id = "ag71xx-mdio.1",
132 .mdio_addr = FRITZ450E_PHY_ADDRESS, 131 .phy_addr = FRITZ450E_PHY_ADDRESS,
133 .platform_data = &fritz450E_at803x_data, 132 .platform_data = &fritz450E_at803x_data,
Line 134... Line 133...
134 }, 133 },
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154   153  
155 ath79_register_mdio(1, ~BIT(FRITZ450E_PHY_ADDRESS)); 154 ath79_register_mdio(1, ~BIT(FRITZ450E_PHY_ADDRESS));
156 ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; 155 ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
157 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; 156 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
158 ath79_eth0_data.phy_mask = BIT(FRITZ450E_PHY_ADDRESS); -  
159 ath79_eth0_data.enable_sgmii_fixup = 1; 157 ath79_eth0_data.phy_mask = BIT(FRITZ450E_PHY_ADDRESS);
160 ath79_eth0_pll_data.pll_1000 = 0x03000000; 158 ath79_eth0_pll_data.pll_1000 = 0x03000000;
161 ath79_eth0_pll_data.pll_100 = 0x00000101; 159 ath79_eth0_pll_data.pll_100 = 0x00000101;
162 ath79_eth0_pll_data.pll_10 = 0x00001313; 160 ath79_eth0_pll_data.pll_10 = 0x00001313;