OpenWrt – Diff between revs 2 and 3
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| Rev 2 | Rev 3 | |||
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| Line 19... | Line 19... | |||
| 19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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| 20 | * |
20 | * |
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| 21 | */ |
21 | */ |
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| Line 22... | Line 22... | |||
| 22 | |
22 | |
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| - | 23 | #include <linux/gpio.h> |
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| 23 | #include <linux/gpio.h> |
24 | #include <linux/pci.h> |
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| 24 | #include <linux/phy.h> |
25 | #include <linux/phy.h> |
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| 25 | #include <linux/platform_device.h> |
26 | #include <linux/platform_device.h> |
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| 26 | #include <linux/ath9k_platform.h> |
27 | #include <linux/ath9k_platform.h> |
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| Line 27... | Line 28... | |||
| 27 | #include <linux/ar8216_platform.h> |
28 | #include <linux/ar8216_platform.h> |
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| 28 | |
29 | |
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| Line 29... | Line 30... | |||
| 29 | #include <asm/mach-ath79/ar71xx_regs.h> |
30 | #include <asm/mach-ath79/ar71xx_regs.h> |
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| - | 31 | #include <asm/mach-ath79/ath79.h> |
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| 30 | #include <asm/mach-ath79/ath79.h> |
32 | |
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| 31 | |
33 | #include "common.h" |
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| 32 | #include "common.h" |
34 | #include "dev-ap9x-pci.h" |
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| 33 | #include "dev-eth.h" |
35 | #include "dev-eth.h" |
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| 34 | #include "dev-gpio-buttons.h" |
36 | #include "dev-gpio-buttons.h" |
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| Line 54... | Line 56... | |||
| 54 | |
56 | |
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| 55 | #define CR3000_MAC0_OFFSET 0 |
57 | #define CR3000_MAC0_OFFSET 0 |
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| 56 | #define CR3000_MAC1_OFFSET 6 |
58 | #define CR3000_MAC1_OFFSET 6 |
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| 57 | #define CR3000_WMAC_CALDATA_OFFSET 0x1000 |
59 | #define CR3000_WMAC_CALDATA_OFFSET 0x1000 |
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| - | 60 | #define CR3000_WMAC_MAC_OFFSET 0x1002 |
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| Line 58... | Line 61... | |||
| 58 | #define CR3000_WMAC_MAC_OFFSET 0x1002 |
61 | #define CR3000_PCIE_CALDATA_OFFSET 0x5000 |
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| 59 | |
62 | |
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| 60 | static struct gpio_led cr3000_leds_gpio[] __initdata = { |
63 | static struct gpio_led cr3000_leds_gpio[] __initdata = { |
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| 61 | { |
64 | { |
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| Line 127... | Line 130... | |||
| 127 | ARRAY_SIZE(cr3000_gpio_keys), |
130 | ARRAY_SIZE(cr3000_gpio_keys), |
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| 128 | cr3000_gpio_keys); |
131 | cr3000_gpio_keys); |
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| Line 129... | Line 132... | |||
| 129 | |
132 | |
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| 130 | /* WLAN 2GHz onboard */ |
133 | /* WLAN 2GHz onboard */ |
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| 131 | ath79_register_wmac(art + CR3000_WMAC_CALDATA_OFFSET, art + CR3000_WMAC_MAC_OFFSET); |
134 | ath79_register_wmac(art + CR3000_WMAC_CALDATA_OFFSET, art + CR3000_WMAC_MAC_OFFSET); |
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| 132 | |
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| 133 | /* FE Lan on first 4-ports of internal switch and attached to GMAC1 |
- | ||
| 134 | * WAN Fast Ethernet interface attached to GMAC0 |
- | ||
| 135 | * Could be configured as a 5-port switch, but we use |
- | ||
| 136 | * the SoC capabilities to attach port 5 to a separate PHY/MAC |
- | ||
| 137 | * theoretically this leaves future possibility of using SoC |
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| 138 | * acceleration/offloading. |
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| 139 | */ |
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| 140 | ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); |
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| 141 | |
- | ||
| 142 | /* GMAC0 attached to PHY4 (port 5 of the internal switch) */ |
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| 143 | ath79_switch_data.phy4_mii_en = 1; |
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| 144 | /* For switch carrier ignore port 5 (wan) */ |
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| 145 | ath79_switch_data.phy_poll_mask = 0x1; |
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| 146 | |
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| 147 | /* Register MII bus */ |
135 | |
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| - | 136 | ath79_register_mdio(1, 0x0); |
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| Line 148... | Line -... | |||
| 148 | ath79_register_mdio(1, 0x0); |
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| 149 | |
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| 150 | /* GMAC0 attached to PHY4 (port 5 of the internal switch) */ |
137 | ath79_register_mdio(0, 0x0); |
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| Line 151... | Line 138... | |||
| 151 | ath79_switch_data.phy4_mii_en = 1; |
138 | |
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| 152 | ath79_switch_data.phy_poll_mask = 0x1; |
139 | ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP); |
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| - | 140 | |
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| 153 | |
141 | /* Lan 4-port switch attached to GMAC1 internal switch */ |
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| - | 142 | ath79_init_mac(ath79_eth1_data.mac_addr, art + CR3000_MAC0_OFFSET, 0); |
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| - | 143 | |
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| 154 | /* LAN */ |
144 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
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| Line 155... | Line -... | |||
| 155 | ath79_init_mac(ath79_eth1_data.mac_addr, art + CR3000_MAC0_OFFSET, 0); |
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| 156 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
145 | ath79_eth1_data.speed = SPEED_1000; |
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| - | 146 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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| - | 147 | ath79_register_eth(1); |
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| - | 148 | |
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| 157 | ath79_register_eth(1); |
149 | ath79_init_mac(ath79_eth0_data.mac_addr, art + CR3000_MAC1_OFFSET, 0); |
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| 158 | |
150 | |
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| - | 151 | /* WAN Fast Ethernet interface attached to GMAC0 */ |
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| 159 | /* Wan */ |
152 | ath79_switch_data.phy4_mii_en = 1; |
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| 160 | ath79_init_mac(ath79_eth0_data.mac_addr, art + CR3000_MAC0_OFFSET, 1); |
153 | ath79_switch_data.phy_poll_mask = BIT(0); |
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| 161 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
154 | ath79_eth0_data.phy_mask = BIT(0); |
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| Line 162... | Line 155... | |||
| 162 | ath79_eth0_data.phy_mask = BIT(0); |
155 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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| 163 | ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; |
156 | ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; |
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