OpenWrt – Diff between revs 2 and 3
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| Rev 2 | Rev 3 | |||
|---|---|---|---|---|
| Line 7... | Line 7... | |||
| 7 | |
7 | |
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| 8 | / { |
8 | / { |
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| 9 | compatible = "phicomm,psg1208", "ralink,mt7620a-soc"; |
9 | compatible = "phicomm,psg1208", "ralink,mt7620a-soc"; |
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| Line 10... | Line -... | |||
| 10 | model = "Phicomm PSG1208"; |
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| 11 | |
- | ||
| 12 | aliases { |
- | ||
| 13 | led-boot = &led_wps; |
- | ||
| 14 | led-failsafe = &led_wps; |
- | ||
| 15 | led-running = &led_wps; |
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| 16 | led-upgrade = &led_wps; |
- | ||
| 17 | }; |
10 | model = "Phicomm PSG1208"; |
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| 18 | |
11 | |
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| Line 19... | Line 12... | |||
| 19 | leds { |
12 | gpio-leds { |
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| 20 | compatible = "gpio-leds"; |
13 | compatible = "gpio-leds"; |
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| 21 | |
14 | |
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| 22 | led_wps: wps { |
15 | wan { |
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| Line 23... | Line 16... | |||
| 23 | label = "psg1208:white:wps"; |
16 | label = "psg1208:white:wps"; |
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| 24 | gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; |
17 | gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; |
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| 25 | }; |
18 | }; |
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| 26 | |
19 | |
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| 27 | wlan { |
20 | wlan { |
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| Line 28... | Line 21... | |||
| 28 | label = "psg1208:white:wlan2g"; |
21 | label = "psg1208:white:wlan2g"; |
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| 29 | gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; |
22 | gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; |
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| - | 23 | }; |
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| - | 24 | }; |
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| 30 | }; |
25 | |
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| Line 31... | Line 26... | |||
| 31 | }; |
26 | gpio-keys-polled { |
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| 32 | |
27 | compatible = "gpio-keys-polled"; |
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| 33 | keys { |
28 | #address-cells = <1>; |
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| Line 52... | Line 47... | |||
| 52 | |
47 | |
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| 53 | &spi0 { |
48 | &spi0 { |
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| Line 54... | Line 49... | |||
| 54 | status = "okay"; |
49 | status = "okay"; |
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| - | 50 | |
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| - | 51 | m25p80@0 { |
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| 55 | |
52 | #address-cells = <1>; |
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| 56 | m25p80@0 { |
53 | #size-cells = <1>; |
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| 57 | compatible = "jedec,spi-nor"; |
54 | compatible = "jedec,spi-nor"; |
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| Line 58... | Line -... | |||
| 58 | reg = <0>; |
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| 59 | spi-max-frequency = <10000000>; |
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| 60 | |
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| 61 | partitions { |
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| 62 | compatible = "fixed-partitions"; |
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| 63 | #address-cells = <1>; |
55 | reg = <0>; |
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| 64 | #size-cells = <1>; |
56 | spi-max-frequency = <10000000>; |
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| 65 | |
57 | |
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| 66 | partition@0 { |
58 | partition@0 { |
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| 67 | label = "u-boot"; |
59 | label = "u-boot"; |
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| 68 | reg = <0x0 0x30000>; |
60 | reg = <0x0 0x30000>; |
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| 69 | read-only; |
61 | read-only; |
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| 70 | }; |
62 | }; |
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| 71 | |
63 | |
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| 72 | partition@20000 { |
64 | partition@20000 { |
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| 73 | label = "u-boot-env"; |
65 | label = "u-boot-env"; |
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| 74 | reg = <0x30000 0x10000>; |
66 | reg = <0x30000 0x10000>; |
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| 75 | read-only; |
67 | read-only; |
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| 76 | }; |
68 | }; |
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| 77 | |
69 | |
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| 78 | factory: partition@30000 { |
70 | factory: partition@30000 { |
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| 79 | label = "factory"; |
71 | label = "factory"; |
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| 80 | reg = <0x40000 0x10000>; |
72 | reg = <0x40000 0x10000>; |
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| 81 | read-only; |
73 | read-only; |
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| 82 | }; |
- | ||
| 83 | |
74 | }; |
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| 84 | partition@40000 { |
75 | |
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| 85 | compatible = "denx,uimage"; |
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| 86 | label = "firmware"; |
76 | partition@40000 { |
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| 87 | reg = <0x50000 0x7b0000>; |
77 | label = "firmware"; |
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| 88 | }; |
78 | reg = <0x50000 0x7b0000>; |
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| Line 89... | Line 79... | |||
| 89 | }; |
79 | }; |
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| Line 106... | Line 96... | |||
| 106 | mediatek,portmap = "llllw"; |
96 | mediatek,portmap = "llllw"; |
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| 107 | }; |
97 | }; |
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| Line 108... | Line 98... | |||
| 108 | |
98 | |
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| 109 | &pcie { |
99 | &pcie { |
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| 110 | status = "okay"; |
- | ||
| Line 111... | Line 100... | |||
| 111 | }; |
100 | status = "okay"; |
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| 112 | |
101 | |
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| 113 | &pcie0 { |
102 | pcie-bridge { |
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| - | 103 | mt76@0,0 { |
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| 114 | mt76@0,0 { |
104 | reg = <0x0000 0 0 0 0>; |
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| 115 | reg = <0x0000 0 0 0 0>; |
105 | device_type = "pci"; |
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| - | 106 | mediatek,mtd-eeprom = <&factory 0x8000>; |
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| 116 | mediatek,mtd-eeprom = <&factory 0x8000>; |
107 | ieee80211-freq-limit = <5000000 6000000>; |
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| 117 | ieee80211-freq-limit = <5000000 6000000>; |
108 | }; |
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| Line 118... | Line 109... | |||
| 118 | }; |
109 | }; |
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| 119 | }; |
110 | }; |
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