OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
Line 7... Line 7...
7   7  
8 / { 8 / {
9 compatible = "planex,mzk-ex750np", "ralink,mt7620a-soc"; 9 compatible = "planex,mzk-ex750np", "ralink,mt7620a-soc";
Line 10... Line -...
10 model = "Planex MZK-EX750NP"; -  
11   -  
12 aliases { -  
13 led-boot = &led_power; -  
14 led-failsafe = &led_power; -  
15 led-running = &led_power; -  
16 led-upgrade = &led_power; -  
17 }; 10 model = "Planex MZK-EX750NP";
18   11  
Line 19... Line 12...
19 leds { 12 gpio-leds {
20 compatible = "gpio-leds"; 13 compatible = "gpio-leds";
21   14  
22 led_power: power { 15 power {
Line 23... Line 16...
23 label = "mzk-ex750np:red:power"; 16 label = "mzk-ex750np:red:power";
Line 53... Line 46...
53 label = "mzk-ex750np:blue:wifi3"; 46 label = "mzk-ex750np:blue:wifi3";
54 gpios = <&gpio2 17 GPIO_ACTIVE_LOW>; 47 gpios = <&gpio2 17 GPIO_ACTIVE_LOW>;
55 }; 48 };
56 }; 49 };
Line 57... Line 50...
57   50  
58 keys { 51 gpio-keys-polled {
-   52 compatible = "gpio-keys-polled";
-   53 #address-cells = <1>;
59 compatible = "gpio-keys-polled"; 54 #size-cells = <0>;
Line 60... Line 55...
60 poll-interval = <20>; 55 poll-interval = <20>;
61   56  
62 reset { 57 reset {
Line 83... Line 78...
83   78  
84 &spi0 { 79 &spi0 {
Line 85... Line 80...
85 status = "okay"; 80 status = "okay";
-   81  
-   82 m25p80@0 {
86   83 #address-cells = <1>;
87 m25p80@0 { 84 #size-cells = <1>;
88 compatible = "jedec,spi-nor"; 85 compatible = "jedec,spi-nor";
Line 89... Line -...
89 reg = <0>; -  
90 spi-max-frequency = <10000000>; -  
91   -  
92 partitions { -  
93 compatible = "fixed-partitions"; -  
94 #address-cells = <1>; 86 reg = <0>;
95 #size-cells = <1>; 87 spi-max-frequency = <10000000>;
96   88  
97 partition@0 { 89 partition@0 {
98 label = "u-boot"; 90 label = "u-boot";
99 reg = <0x0 0x30000>; 91 reg = <0x0 0x30000>;
100 read-only; 92 read-only;
101 }; 93 };
102   94  
103 partition@30000 { 95 partition@30000 {
104 label = "u-boot-env"; 96 label = "u-boot-env";
105 reg = <0x30000 0x10000>; 97 reg = <0x30000 0x10000>;
106 read-only; 98 read-only;
107 }; 99 };
108   100  
109 factory: partition@40000 { 101 factory: partition@40000 {
110 label = "factory"; 102 label = "factory";
111 reg = <0x40000 0x10000>; 103 reg = <0x40000 0x10000>;
112 read-only; 104 read-only;
113 }; -  
114   105 };
115 partition@50000 { 106  
116 compatible = "denx,uimage"; 107 partition@50000 {
117 label = "firmware"; 108 label = "firmware";
118 reg = <0x50000 0x730000>; 109 reg = <0x50000 0x730000>;
119 }; 110 };
120   111  
121 partition@780000 { -  
122 label = "Udata"; 112 partition@780000 {
123 reg = <0x780000 0x80000>; 113 label = "Udata";
124 }; 114 reg = <0x780000 0x80000>;
Line 125... Line 115...
125 }; 115 };
Line 146... Line 136...
146 ralink,mtd-eeprom = <&factory 0>; 136 ralink,mtd-eeprom = <&factory 0>;
147 }; 137 };
Line 148... Line 138...
148   138  
149 &pcie { 139 &pcie {
150 status = "okay"; -  
Line 151... Line 140...
151 }; 140 status = "okay";
152   141  
153 &pcie0 { 142 pcie-bridge {
-   143 mt76@0,0 {
154 mt76@0,0 { 144 reg = <0x0000 0 0 0 0>;
-   145 device_type = "pci";
155 reg = <0x0000 0 0 0 0>; 146 mediatek,mtd-eeprom = <&factory 0x8000>;
156 mediatek,mtd-eeprom = <&factory 0x8000>; 147 };