OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
Line 7... Line 7...
7   7  
8 / { 8 / {
9 compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; 9 compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
Line 10... Line 10...
10 model = "Ralink MT7620A evaluation board"; 10 model = "Ralink MT7620A evaluation board";
11   11  
-   12 gpio-keys-polled {
-   13 compatible = "gpio-keys";
12 keys { 14 #address-cells = <1>;
Line 13... Line 15...
13 compatible = "gpio-keys"; 15 #size-cells = <0>;
14 poll-interval = <20>; 16 poll-interval = <20>;
15   17  
Line 33... Line 35...
33   35  
34 &spi0 { 36 &spi0 {
Line 35... Line 37...
35 status = "okay"; 37 status = "okay";
-   38  
-   39 m25p80@0 {
36   40 #address-cells = <1>;
37 m25p80@0 { 41 #size-cells = <1>;
38 compatible = "jedec,spi-nor"; 42 compatible = "jedec,spi-nor";
Line 39... Line -...
39 reg = <0>; -  
40 spi-max-frequency = <1000000>; -  
41   -  
42 partitions { -  
43 compatible = "fixed-partitions"; -  
44 #address-cells = <1>; 43 reg = <0>;
45 #size-cells = <1>; 44 spi-max-frequency = <1000000>;
46   45  
47 partition@0 { 46 partition@0 {
48 label = "u-boot"; 47 label = "u-boot";
49 reg = <0x0 0x30000>; 48 reg = <0x0 0x30000>;
50 read-only; 49 read-only;
51 }; 50 };
52   51  
53 partition@30000 { 52 partition@30000 {
54 label = "u-boot-env"; 53 label = "u-boot-env";
55 reg = <0x30000 0x10000>; 54 reg = <0x30000 0x10000>;
56 read-only; 55 read-only;
57 }; 56 };
58   57  
59 factory: partition@40000 { 58 factory: partition@40000 {
60 label = "factory"; 59 label = "factory";
61 reg = <0x40000 0x10000>; 60 reg = <0x40000 0x10000>;
62 read-only; 61 read-only;
63 }; -  
64   62 };
65 partition@50000 { 63  
66 compatible = "denx,uimage"; -  
67 label = "firmware"; 64 partition@50000 {
68 reg = <0x50000 0x7b0000>; 65 label = "firmware";
69 }; 66 reg = <0x50000 0x7b0000>;
Line 70... Line 67...
70 }; 67 };
Line 87... Line 84...
87 }; 84 };
Line 88... Line 85...
88   85  
89 &pcie { 86 &pcie {
90 status = "okay"; 87 status = "okay";
91 }; -  
92   -  
93 &pcie0 { -  
94 wifi@0,0 { -  
95 reg = <0x0000 0 0 0 0>; -  
96 mediatek,mtd-eeprom = <&factory 0x8000>; -  
97 ieee80211-freq-limit = <5000000 6000000>; -  
98 }; -