OpenWrt – Diff between revs 2 and 3

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Rev 2 – Details – Blame – Last modification – View Log

 	MV_GLOBAL_VTU_OP		= 0x05,
 	MV_GLOBAL_VTU_VID		= 0x06,
 	MV_GLOBAL_VTU_DATA1		= 0x07,
 	MV_GLOBAL_VTU_DATA2		= 0x08,
 	MV_GLOBAL_VTU_DATA3		= 0x09,
-	MV_GLOBAL_MONITOR_CTRL		= 0x1a,
 	MV_GLOBAL_CONTROL2		= 0x1c,
 };
 #define MV_GLOBALREG(_type) MV_SWITCH_GLOBAL, MV_GLOBAL_##_type
 #define MV_FDB_HI_MASK			0x00ff
 #define MV_FDB_LO_MASK			0xf000
 #define MV_FDB_HI_SHIFT			4
 #define MV_FDB_LO_SHIFT			12
-#define MV_MIRROR_RX_DEST_MASK		0xf000
-#define MV_MIRROR_TX_DEST_MASK		0x0f00
-#define MV_MIRROR_RX_DEST_SHIFT		12
-#define MV_MIRROR_TX_DEST_SHIFT		8
-#define MV_MIRROR_RX_SRC_SHIFT		4
-#define MV_MIRROR_RX_SRC_MASK		(1 << MV_MIRROR_RX_SRC_SHIFT)
-#define MV_MIRROR_TX_SRC_SHIFT		5
-#define MV_MIRROR_TX_SRC_MASK		(1 << MV_MIRROR_TX_SRC_SHIFT)
 /* Marvell Specific PHY register */
 #define MII_MV_SPEC_CTRL		16
 enum {
 	MV_SPEC_MDI_CROSS_AUTO		= (0x6 << 4),
 		u16 vid;
 		u32 port_mode;
 		u32 port_sstate;
 	} vlans[MV_VLANS];
-	/* mirroring */
-	bool mirror_rx;
-	bool mirror_tx;
-	int source_port;
-	int monitor_port;
 	char buf[128];
 };