OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
Line 29... Line 29...
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
Line 30... Line 30...
30   30  
Line 31... Line 31...
31 #define ETH_SWITCH_HEADER_LEN 2 31 #define ETH_SWITCH_HEADER_LEN 2
32   -  
Line 33... Line 32...
33 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush); 32  
34 static void ag71xx_qca955x_sgmii_init(void); 33 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
35   34  
36 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu) 35 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
Line 609... Line 608...
609 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3); 608 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
Line 610... Line 609...
610   609  
611 if (update && pdata->set_speed) 610 if (update && pdata->set_speed)
Line 612... Line -...
612 pdata->set_speed(ag->speed); -  
613   -  
614 if (update && pdata->enable_sgmii_fixup) -  
615 ag71xx_qca955x_sgmii_init(); 611 pdata->set_speed(ag->speed);
616   612  
617 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); 613 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
Line 618... Line 614...
618 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); 614 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
Line 640... Line 636...
640 pr_info("%s: link up (%sMbps/%s duplex)\n", 636 pr_info("%s: link up (%sMbps/%s duplex)\n",
641 ag->dev->name, 637 ag->dev->name,
642 ag71xx_speed_str(ag), 638 ag71xx_speed_str(ag),
643 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); 639 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
Line -... Line 640...
-   640  
644   641 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
-   642 ag->dev->name,
-   643 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
-   644 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
-   645 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
-   646  
-   647 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
-   648 ag->dev->name,
-   649 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
-   650 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
-   651 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
-   652  
-   653 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
-   654 ag->dev->name,
-   655 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
645 ag71xx_dump_regs(ag); 656 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
Line 646... Line 657...
646 } 657 }
647   658  
648 void ag71xx_link_adjust(struct ag71xx *ag) 659 void ag71xx_link_adjust(struct ag71xx *ag)
Line 900... Line 911...
900 pr_info("%s: tx timeout\n", ag->dev->name); 911 pr_info("%s: tx timeout\n", ag->dev->name);
Line 901... Line 912...
901   912  
902 schedule_delayed_work(&ag->restart_work, 1); 913 schedule_delayed_work(&ag->restart_work, 1);
Line 903... Line -...
903 } -  
904   -  
905 static void ag71xx_bit_set(void __iomem *reg, u32 bit) -  
906 { -  
907 u32 val = __raw_readl(reg) | bit; -  
908 __raw_writel(val, reg); -  
909 __raw_readl(reg); -  
910 } -  
911   -  
912 static void ag71xx_bit_clear(void __iomem *reg, u32 bit) -  
913 { -  
914 u32 val = __raw_readl(reg) & ~bit; -  
915 __raw_writel(val, reg); -  
916 __raw_readl(reg); -  
917 } -  
918   -  
919 static void ag71xx_qca955x_sgmii_init() -  
920 { -  
921 void __iomem *gmac_base; -  
922 u32 mr_an_status, sgmii_status; -  
923 u8 tries = 0; -  
924   -  
925 gmac_base = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); -  
926   -  
927 if (!gmac_base) -  
928 goto sgmii_out; -  
929   -  
930 mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS); -  
931 if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY)) -  
932 goto sgmii_out; -  
933   -  
934 __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET , -  
935 gmac_base + QCA955X_GMAC_REG_SGMII_RESET); -  
936 __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET); -  
937 udelay(10); -  
938   -  
939 /* Init sequence */ -  
940 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, -  
941 QCA955X_SGMII_RESET_HW_RX_125M_N); -  
942 udelay(10); -  
943   -  
944 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, -  
945 QCA955X_SGMII_RESET_RX_125M_N); -  
946 udelay(10); -  
947   -  
948 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, -  
949 QCA955X_SGMII_RESET_TX_125M_N); -  
950 udelay(10); -  
951   -  
952 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, -  
953 QCA955X_SGMII_RESET_RX_CLK_N); -  
954 udelay(10); -  
955   -  
956 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET, -  
957 QCA955X_SGMII_RESET_TX_CLK_N); -  
958 udelay(10); -  
959   -  
960 do { -  
961 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL, -  
962 QCA955X_MR_AN_CONTROL_PHY_RESET | -  
963 QCA955X_MR_AN_CONTROL_AN_ENABLE); -  
964 udelay(100); -  
965 ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL, -  
966 QCA955X_MR_AN_CONTROL_PHY_RESET); -  
967 mdelay(10); -  
968 sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) & 0xF; -  
969   -  
970 if (tries++ >= QCA955X_SGMII_LINK_WAR_MAX_TRY) { -  
971 pr_warn("ag71xx: max retries for SGMII fixup exceeded!\n"); -  
972 break; -  
973 } -  
974 } while (!(sgmii_status == 0xf || sgmii_status == 0x10)); -  
975   -  
976 sgmii_out: -  
977 iounmap(gmac_base); -  
978 } 914 }
979   915  
980 static void ag71xx_restart_work_func(struct work_struct *work) 916 static void ag71xx_restart_work_func(struct work_struct *work)
Line 981... Line 917...
981 { 917 {