OpenWrt – Diff between revs 2 and 3

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1 /* 1 /*
2 * PowerCloud Systems CR5000 support 2 * PowerCloud CR5000 support
3 * 3 *
4 * Copyright (c) 2011 Qualcomm Atheros 4 * Copyright (c) 2011 Qualcomm Atheros
5 * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (c) 2012-2013 PowerCloud Systems 6 * Copyright (c) 2012-2013 PowerCloud Systems
7 * Copyright (c) 2015 Daniel Dickinson <openwrt@daniel.thecshore.com> 7 * Copyright (c) 2015 Daniel Dickinson <openwrt@daniel.thecshore.com>
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56   56  
57 #define CR5000_MAC0_OFFSET 0 57 #define CR5000_MAC0_OFFSET 0
58 #define CR5000_WMAC_CALDATA_OFFSET 0x1000 58 #define CR5000_WMAC_CALDATA_OFFSET 0x1000
59 #define CR5000_WMAC_MAC_OFFSET 0x1002 59 #define CR5000_WMAC_MAC_OFFSET 0x1002
60 #define CR5000_PCIE_CALDATA_OFFSET 0x5000 60 #define CR5000_PCIE_CALDATA_OFFSET 0x5000
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61 #define CR5000_PCIE_WMAC_OFFSET 0x5002 61 #define CR5000_PCIE_MAC_OFFSET 0x5002
62   62  
63 static struct gpio_led cr5000_leds_gpio[] __initdata = { 63 static struct gpio_led cr5000_leds_gpio[] __initdata = {
64 { 64 {
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88 .active_low = 1, 88 .active_low = 1,
89 }, 89 },
90 { 90 {
91 .desc = "Reset button", 91 .desc = "Reset button",
92 .type = EV_KEY, 92 .type = EV_KEY,
93 .code = KEY_RESTART, 93 .code = KEY_WPS_BUTTON,
94 .debounce_interval = CR5000_KEYS_DEBOUNCE_INTERVAL, 94 .debounce_interval = CR5000_KEYS_DEBOUNCE_INTERVAL,
95 .gpio = CR5000_GPIO_BTN_RESET, 95 .gpio = CR5000_GPIO_BTN_RESET,
96 .active_low = 1, 96 .active_low = 1,
97 }, 97 },
98 }; 98 };
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104 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, 104 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
105 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, 105 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
106 }; 106 };
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107   107  
108 static struct ar8327_led_cfg cr5000_ar8327_led_cfg = { 108 static struct ar8327_led_cfg cr5000_ar8327_led_cfg = {
109 .led_ctrl0 = 0xcc35cc35, 109 .led_ctrl0 = 0x00000000,
110 .led_ctrl1 = 0xca35ca35, 110 .led_ctrl1 = 0xc737c737,
111 .led_ctrl2 = 0xc935c935, 111 .led_ctrl2 = 0x00000000,
112 .led_ctrl3 = 0x03ffff00, 112 .led_ctrl3 = 0x00c30c00,
113 .open_drain = true, 113 .open_drain = true,
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114 }; 114 };
115   115  
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126 }; 126 };
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127   127  
128 static struct mdio_board_info cr5000_mdio0_info[] = { 128 static struct mdio_board_info cr5000_mdio0_info[] = {
129 { 129 {
130 .bus_id = "ag71xx-mdio.0", 130 .bus_id = "ag71xx-mdio.0",
131 .mdio_addr = 0, 131 .phy_addr = 0,
132 .platform_data = &cr5000_ar8327_data, 132 .platform_data = &cr5000_ar8327_data,
133 }, 133 },
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134 }; 134 };
135   135  
136 static void __init cr5000_setup(void) 136 static void __init cr5000_setup(void)
137 { -  
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138 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); 137 {
139 struct ath9k_platform_data *pdata; 138 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
140   139  
141 ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); 140 ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
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152 ath79_register_gpio_keys_polled(-1, CR5000_KEYS_POLL_INTERVAL, 151 ath79_register_gpio_keys_polled(-1, CR5000_KEYS_POLL_INTERVAL,
153 ARRAY_SIZE(cr5000_gpio_keys), 152 ARRAY_SIZE(cr5000_gpio_keys),
154 cr5000_gpio_keys); 153 cr5000_gpio_keys);
155 ath79_register_usb(); 154 ath79_register_usb();
156 ath79_register_wmac(art + CR5000_WMAC_CALDATA_OFFSET, art + CR5000_WMAC_MAC_OFFSET); 155 ath79_register_wmac(art + CR5000_WMAC_CALDATA_OFFSET, art + CR5000_WMAC_MAC_OFFSET);
157 ap91_pci_init(NULL, art + CR5000_PCIE_WMAC_OFFSET); 156 ap94_pci_init(NULL, NULL, NULL, art + CR5000_PCIE_MAC_OFFSET);
-   157  
158 pdata = ap9x_pci_get_wmac_data(0); 158 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
159 if (pdata) -  
160 pdata->use_eeprom = true; -  
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161   -  
162 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0); 159  
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163 ath79_register_mdio(0, 0x0); 160 ath79_register_mdio(0, 0x0);
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164   161  
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173 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; 170 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
174 ath79_eth0_pll_data.pll_1000 = 0x06000000; 171 ath79_eth0_pll_data.pll_1000 = 0x06000000;
175 ath79_register_eth(0); 172 ath79_register_eth(0);
176 } 173 }
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177   174  
178 MIPS_MACHINE(ATH79_MACH_CR5000, "CR5000", "PowerCloud Systems CR5000", 175 MIPS_MACHINE(ATH79_MACH_CR5000, "CR5000", "PowerCloud CR5000",