OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
Line 7... Line 7...
7   7  
8 / { 8 / {
9 compatible = "firefly,firewrt", "mediatek,mt7621-soc"; 9 compatible = "firefly,firewrt", "mediatek,mt7621-soc";
Line 10... Line -...
10 model = "Firefly FireWRT"; -  
11   -  
12 aliases { -  
13 led-boot = &led_power; -  
14 led-failsafe = &led_power; -  
15 led-running = &led_power; -  
16 led-upgrade = &led_power; -  
17 }; 10 model = "Firefly FireWRT";
18   11  
19 memory@0 { 12 memory@0 {
20 device_type = "memory"; 13 device_type = "memory";
Line 21... Line 14...
21 reg = <0x0 0x1c000000>, <0x20000000 0x4000000>; 14 reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
22 }; 15 };
23   16  
Line 24... Line 17...
24 chosen { 17 chosen {
25 bootargs = "console=ttyS0,57600"; 18 bootargs = "console=ttyS0,57600";
Line 26... Line 19...
26 }; 19 };
27   20  
28 leds { 21 gpio-leds {
29 compatible = "gpio-leds"; 22 compatible = "gpio-leds";
30   23  
Line 31... Line 24...
31 led_power: power { 24 power {
32 label = "firewrt:green:power"; 25 label = "firewrt:green:power";
-   26 gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
-   27 };
33 gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; 28 };
Line 34... Line 29...
34 }; 29  
35 }; 30 gpio-keys-polled {
36   31 compatible = "gpio-keys-polled";
Line 58... Line 53...
58   53  
59 &spi0 { 54 &spi0 {
Line 60... Line 55...
60 status = "okay"; 55 status = "okay";
-   56  
-   57 m25p80@0 {
61   58 #address-cells = <1>;
62 m25p80@0 { 59 #size-cells = <1>;
63 compatible = "jedec,spi-nor"; 60 compatible = "jedec,spi-nor";
64 reg = <0>; -  
65 spi-max-frequency = <10000000>; -  
66   -  
67 partitions { -  
68 compatible = "fixed-partitions"; 61 reg = <0>;
Line 69... Line 62...
69 #address-cells = <1>; 62 spi-max-frequency = <10000000>;
70 #size-cells = <1>; 63 m25p,chunked-io = <32>;
71   64  
72 partition@0 { 65 partition@0 {
Line 86... Line 79...
86 reg = <0x40000 0x10000>; 79 reg = <0x40000 0x10000>;
87 read-only; 80 read-only;
88 }; 81 };
Line 89... Line 82...
89   82  
90 partition@50000 { -  
91 compatible = "denx,uimage"; 83 partition@50000 {
92 label = "firmware"; 84 label = "firmware";
93 reg = <0x50000 0xfb0000>; 85 reg = <0x50000 0xfb0000>;
94 }; 86 };
95 }; 87 };
96 }; -  
Line 97... Line 88...
97 }; 88 };
98   89  
99 &pcie { -  
Line 100... Line 90...
100 status = "okay"; 90 &pcie {
101 }; 91 status = "okay";
102   92  
-   93 pcie0 {
103 &pcie0 { 94 mt76@0,0 {
104 mt76@0,0 { 95 reg = <0x0000 0 0 0 0>;
105 reg = <0x0000 0 0 0 0>; 96 device_type = "pci";
106 mediatek,mtd-eeprom = <&factory 0x8000>; 97 mediatek,mtd-eeprom = <&factory 0x8000>;
Line 107... Line 98...
107 ieee80211-freq-limit = <5000000 6000000>; 98 ieee80211-freq-limit = <5000000 6000000>;
108 }; 99 };
109 }; 100 };
-   101  
110   102 pcie1 {
111 &pcie1 { 103 mt76@1,0 {
112 mt76@0,0 { 104 reg = <0x0000 0 0 0 0>;
113 reg = <0x0000 0 0 0 0>; 105 device_type = "pci";
-   106 mediatek,mtd-eeprom = <&factory 0x0000>;
Line 114... Line 107...
114 mediatek,mtd-eeprom = <&factory 0x0000>; 107 ieee80211-freq-limit = <2400000 2500000>;
115 ieee80211-freq-limit = <2400000 2500000>; 108 };
116 }; 109 };