OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
1 / { 1 / {
2 #address-cells = <1>; 2 #address-cells = <1>;
3 #size-cells = <1>; 3 #size-cells = <1>;
4 compatible = "mediatek,mt7628an-soc"; 4 compatible = "ralink,mtk7628an-soc";
5   5  
6 cpus { -  
7 #address-cells = <1>; -  
8 #size-cells = <0>; -  
9   6 cpus {
10 cpu@0 { 7 cpu@0 {
11 compatible = "mips,mips24KEc"; -  
12 reg = <0>; 8 compatible = "mips,mips24KEc";
13 }; 9 };
14 }; 10 };
15   11  
16 chosen { 12 chosen {
17 bootargs = "console=ttyS0,57600"; 13 bootargs = "console=ttyS0,57600";
18 }; 14 };
19   15  
20 aliases { 16 aliases {
21 serial0 = &uartlite; 17 serial0 = &uartlite;
22 }; 18 };
23   19  
24 cpuintc: cpuintc { 20 cpuintc: cpuintc@0 {
25 #address-cells = <0>; 21 #address-cells = <0>;
26 #interrupt-cells = <1>; 22 #interrupt-cells = <1>;
27 interrupt-controller; 23 interrupt-controller;
28 compatible = "mti,cpu-interrupt-controller"; 24 compatible = "mti,cpu-interrupt-controller";
29 }; 25 };
30   26  
31 palmbus: palmbus@10000000 { 27 palmbus: palmbus@10000000 {
32 compatible = "palmbus"; 28 compatible = "palmbus";
33 reg = <0x10000000 0x200000>; 29 reg = <0x10000000 0x200000>;
34 ranges = <0x0 0x10000000 0x1FFFFF>; 30 ranges = <0x0 0x10000000 0x1FFFFF>;
35   31  
36 #address-cells = <1>; 32 #address-cells = <1>;
37 #size-cells = <1>; 33 #size-cells = <1>;
38   34  
39 sysc: sysc@0 { 35 sysc: sysc@0 {
40 compatible = "ralink,mt7620a-sysc", "syscon"; 36 compatible = "ralink,mt7620a-sysc", "syscon";
41 reg = <0x0 0x100>; 37 reg = <0x0 0x100>;
42 }; 38 };
43   39  
44 watchdog: watchdog@100 { 40 watchdog: watchdog@100 {
45 compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt"; 41 compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt";
46 reg = <0x100 0x30>; 42 reg = <0x100 0x30>;
47   43  
48 resets = <&rstctrl 8>; 44 resets = <&rstctrl 8>;
49 reset-names = "wdt"; 45 reset-names = "wdt";
50   46  
51 interrupt-parent = <&intc>; 47 interrupt-parent = <&intc>;
52 interrupts = <24>; 48 interrupts = <24>;
53 }; 49 };
54   50  
55 intc: intc@200 { 51 intc: intc@200 {
56 compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc"; 52 compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
57 reg = <0x200 0x100>; 53 reg = <0x200 0x100>;
58   54  
59 resets = <&rstctrl 9>; 55 resets = <&rstctrl 9>;
60 reset-names = "intc"; 56 reset-names = "intc";
61   57  
62 interrupt-controller; 58 interrupt-controller;
63 #interrupt-cells = <1>; 59 #interrupt-cells = <1>;
64   60  
65 interrupt-parent = <&cpuintc>; 61 interrupt-parent = <&cpuintc>;
66 interrupts = <2>; 62 interrupts = <2>;
67   63  
68 ralink,intc-registers = <0x9c 0xa0 64 ralink,intc-registers = <0x9c 0xa0
69 0x6c 0xa4 65 0x6c 0xa4
70 0x80 0x78>; 66 0x80 0x78>;
71 }; 67 };
72   68  
73 memc: memc@300 { 69 memc: memc@300 {
74 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; 70 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
75 reg = <0x300 0x100>; 71 reg = <0x300 0x100>;
76   72  
77 resets = <&rstctrl 20>; 73 resets = <&rstctrl 20>;
78 reset-names = "mc"; 74 reset-names = "mc";
79   75  
80 interrupt-parent = <&intc>; 76 interrupt-parent = <&intc>;
81 interrupts = <3>; 77 interrupts = <3>;
82 }; 78 };
83   79  
84 gpio@600 { 80 gpio@600 {
85 #address-cells = <1>; 81 #address-cells = <1>;
86 #size-cells = <0>; 82 #size-cells = <0>;
87   83  
88 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; 84 compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
89 reg = <0x600 0x100>; 85 reg = <0x600 0x100>;
90   86  
91 interrupt-parent = <&intc>; 87 interrupt-parent = <&intc>;
92 interrupts = <6>; 88 interrupts = <6>;
93   89  
94 gpio0: bank@0 { 90 gpio0: bank@0 {
95 reg = <0>; 91 reg = <0>;
96 compatible = "mtk,mt7621-gpio-bank"; 92 compatible = "mtk,mt7621-gpio-bank";
97 gpio-controller; 93 gpio-controller;
98 #gpio-cells = <2>; 94 #gpio-cells = <2>;
99 }; 95 };
100   96  
101 gpio1: bank@1 { 97 gpio1: bank@1 {
102 reg = <1>; 98 reg = <1>;
103 compatible = "mtk,mt7621-gpio-bank"; 99 compatible = "mtk,mt7621-gpio-bank";
104 gpio-controller; 100 gpio-controller;
105 #gpio-cells = <2>; 101 #gpio-cells = <2>;
106 }; 102 };
107   103  
108 gpio2: bank@2 { 104 gpio2: bank@2 {
109 reg = <2>; 105 reg = <2>;
110 compatible = "mtk,mt7621-gpio-bank"; 106 compatible = "mtk,mt7621-gpio-bank";
111 gpio-controller; 107 gpio-controller;
112 #gpio-cells = <2>; 108 #gpio-cells = <2>;
113 }; 109 };
114 }; 110 };
115   111  
116 i2c: i2c@900 { 112 i2c: i2c@900 {
117 compatible = "mediatek,mt7621-i2c"; 113 compatible = "mediatek,mt7621-i2c";
118 reg = <0x900 0x100>; 114 reg = <0x900 0x100>;
119   115  
120 resets = <&rstctrl 16>; 116 resets = <&rstctrl 16>;
121 reset-names = "i2c"; 117 reset-names = "i2c";
122   118  
123 #address-cells = <1>; 119 #address-cells = <1>;
124 #size-cells = <0>; 120 #size-cells = <0>;
125   121  
126 status = "disabled"; 122 status = "disabled";
127   123  
128 pinctrl-names = "default"; 124 pinctrl-names = "default";
129 pinctrl-0 = <&i2c_pins>; 125 pinctrl-0 = <&i2c_pins>;
130 }; 126 };
131   127  
132 i2s: i2s@a00 { 128 i2s: i2s@a00 {
133 compatible = "mediatek,mt7628-i2s"; 129 compatible = "mediatek,mt7628-i2s";
134 reg = <0xa00 0x100>; 130 reg = <0xa00 0x100>;
135   131  
136 resets = <&rstctrl 17>; 132 resets = <&rstctrl 17>;
137 reset-names = "i2s"; 133 reset-names = "i2s";
138   134  
139 interrupt-parent = <&intc>; 135 interrupt-parent = <&intc>;
140 interrupts = <10>; 136 interrupts = <10>;
141   137  
142 txdma-req = <2>; 138 txdma-req = <2>;
143 rxdma-req = <3>; 139 rxdma-req = <3>;
144   140  
145 dmas = <&gdma 4>, 141 dmas = <&gdma 4>,
146 <&gdma 6>; 142 <&gdma 6>;
147 dma-names = "tx", "rx"; 143 dma-names = "tx", "rx";
148   144  
149 status = "disabled"; 145 status = "disabled";
150 }; 146 };
151   147  
152 spi0: spi@b00 { 148 spi0: spi@b00 {
153 compatible = "ralink,mt7621-spi"; 149 compatible = "ralink,mt7621-spi";
154 reg = <0xb00 0x100>; 150 reg = <0xb00 0x100>;
155   151  
156 resets = <&rstctrl 18>; 152 resets = <&rstctrl 18>;
157 reset-names = "spi"; 153 reset-names = "spi";
158   154  
159 #address-cells = <1>; 155 #address-cells = <1>;
160 #size-cells = <0>; 156 #size-cells = <0>;
161   157  
162 pinctrl-names = "default"; 158 pinctrl-names = "default";
163 pinctrl-0 = <&spi_pins>; 159 pinctrl-0 = <&spi_pins>;
164   160  
165 status = "disabled"; 161 status = "disabled";
166 }; 162 };
167   163  
168 uartlite: uartlite@c00 { 164 uartlite: uartlite@c00 {
169 compatible = "ns16550a"; 165 compatible = "ns16550a";
170 reg = <0xc00 0x100>; 166 reg = <0xc00 0x100>;
171   167  
172 reg-shift = <2>; 168 reg-shift = <2>;
173 reg-io-width = <4>; 169 reg-io-width = <4>;
174 no-loopback-test; 170 no-loopback-test;
175   171  
176 clock-frequency = <40000000>; 172 clock-frequency = <40000000>;
177   173  
178 resets = <&rstctrl 12>; 174 resets = <&rstctrl 12>;
179 reset-names = "uartl"; 175 reset-names = "uartl";
180   176  
181 interrupt-parent = <&intc>; 177 interrupt-parent = <&intc>;
182 interrupts = <20>; 178 interrupts = <20>;
183   179  
184 pinctrl-names = "default"; 180 pinctrl-names = "default";
185 pinctrl-0 = <&uart0_pins>; 181 pinctrl-0 = <&uart0_pins>;
186 }; 182 };
187   183  
188 uart1: uart1@d00 { 184 uart1: uart1@d00 {
189 compatible = "ns16550a"; 185 compatible = "ns16550a";
190 reg = <0xd00 0x100>; 186 reg = <0xd00 0x100>;
191   187  
192 reg-shift = <2>; 188 reg-shift = <2>;
193 reg-io-width = <4>; 189 reg-io-width = <4>;
194 no-loopback-test; 190 no-loopback-test;
195   191  
196 clock-frequency = <40000000>; 192 clock-frequency = <40000000>;
197   193  
198 resets = <&rstctrl 19>; 194 resets = <&rstctrl 19>;
199 reset-names = "uart1"; 195 reset-names = "uart1";
200   196  
201 interrupt-parent = <&intc>; 197 interrupt-parent = <&intc>;
202 interrupts = <21>; 198 interrupts = <21>;
203   199  
204 pinctrl-names = "default"; 200 pinctrl-names = "default";
205 pinctrl-0 = <&uart1_pins>; 201 pinctrl-0 = <&uart1_pins>;
206   202  
207 status = "disabled"; 203 status = "disabled";
208 }; 204 };
209   205  
210 uart2: uart2@e00 { 206 uart2: uart2@e00 {
211 compatible = "ns16550a"; 207 compatible = "ns16550a";
212 reg = <0xe00 0x100>; 208 reg = <0xe00 0x100>;
213   209  
214 reg-shift = <2>; 210 reg-shift = <2>;
215 reg-io-width = <4>; 211 reg-io-width = <4>;
216 no-loopback-test; 212 no-loopback-test;
217   213  
218 clock-frequency = <40000000>; 214 clock-frequency = <40000000>;
219   215  
220 resets = <&rstctrl 20>; 216 resets = <&rstctrl 20>;
221 reset-names = "uart2"; 217 reset-names = "uart2";
222   218  
223 interrupt-parent = <&intc>; 219 interrupt-parent = <&intc>;
224 interrupts = <22>; 220 interrupts = <22>;
225   221  
226 pinctrl-names = "default"; 222 pinctrl-names = "default";
227 pinctrl-0 = <&uart2_pins>; 223 pinctrl-0 = <&uart2_pins>;
228   224  
229 status = "disabled"; 225 status = "disabled";
230 }; 226 };
231   227  
232 pwm: pwm@5000 { 228 pwm: pwm@5000 {
233 compatible = "mediatek,mt7628-pwm"; 229 compatible = "mediatek,mt7628-pwm";
234 reg = <0x5000 0x1000>; 230 reg = <0x5000 0x1000>;
235   231  
236 resets = <&rstctrl 31>; 232 resets = <&rstctrl 31>;
237 reset-names = "pwm"; 233 reset-names = "pwm";
238   234  
239 pinctrl-names = "default"; 235 pinctrl-names = "default";
240 pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; 236 pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
241   237  
242 status = "disabled"; 238 status = "disabled";
243 }; 239 };
244   240  
245 pcm: pcm@2000 { 241 pcm: pcm@2000 {
246 compatible = "ralink,mt7620a-pcm"; 242 compatible = "ralink,mt7620a-pcm";
247 reg = <0x2000 0x800>; 243 reg = <0x2000 0x800>;
248   244  
249 resets = <&rstctrl 11>; 245 resets = <&rstctrl 11>;
250 reset-names = "pcm"; 246 reset-names = "pcm";
251   247  
252 interrupt-parent = <&intc>; 248 interrupt-parent = <&intc>;
253 interrupts = <4>; 249 interrupts = <4>;
254   250  
255 status = "disabled"; 251 status = "disabled";
256 }; 252 };
257   253  
258 gdma: gdma@2800 { 254 gdma: gdma@2800 {
259 compatible = "ralink,rt3883-gdma"; 255 compatible = "ralink,rt3883-gdma";
260 reg = <0x2800 0x800>; 256 reg = <0x2800 0x800>;
261   257  
262 resets = <&rstctrl 14>; 258 resets = <&rstctrl 14>;
263 reset-names = "dma"; 259 reset-names = "dma";
264   260  
265 interrupt-parent = <&intc>; 261 interrupt-parent = <&intc>;
266 interrupts = <7>; 262 interrupts = <7>;
267   263  
268 #dma-cells = <1>; 264 #dma-cells = <1>;
269 #dma-channels = <16>; 265 #dma-channels = <16>;
270 #dma-requests = <16>; 266 #dma-requests = <16>;
271   267  
272 status = "disabled"; 268 status = "disabled";
273 }; 269 };
274 }; 270 };
275   271  
276 pinctrl: pinctrl { 272 pinctrl: pinctrl {
277 compatible = "ralink,rt2880-pinmux"; 273 compatible = "ralink,rt2880-pinmux";
278 pinctrl-names = "default"; 274 pinctrl-names = "default";
279 pinctrl-0 = <&state_default>; 275 pinctrl-0 = <&state_default>;
280   276  
281 state_default: pinctrl0 { 277 state_default: pinctrl0 {
282 }; 278 };
283   279  
284 spi_pins: spi_pins { 280 spi_pins: spi {
285 spi_pins { 281 spi {
286 ralink,group = "spi"; 282 ralink,group = "spi";
287 ralink,function = "spi"; 283 ralink,function = "spi";
288 }; 284 };
289 }; 285 };
290   286  
291 spi_cs1_pins: spi_cs1 { 287 spi_cs1_pins: spi_cs1 {
292 spi_cs1 { 288 spi_cs1 {
293 ralink,group = "spi cs1"; 289 ralink,group = "spi cs1";
294 ralink,function = "spi cs1"; 290 ralink,function = "spi cs1";
295 }; 291 };
296 }; 292 };
297   293  
298 i2c_pins: i2c_pins { 294 i2c_pins: i2c {
299 i2c_pins { 295 i2c {
300 ralink,group = "i2c"; 296 ralink,group = "i2c";
301 ralink,function = "i2c"; 297 ralink,function = "i2c";
302 }; 298 };
303 }; 299 };
304   300  
305 i2s_pins: i2s { 301 i2s_pins: i2s {
306 i2s { 302 i2s {
307 ralink,group = "i2s"; 303 ralink,group = "i2s";
308 ralink,function = "i2s"; 304 ralink,function = "i2s";
309 }; 305 };
310 }; 306 };
311   307  
312 uart0_pins: uartlite { 308 uart0_pins: uartlite {
313 uartlite { 309 uartlite {
314 ralink,group = "uart0"; 310 ralink,group = "uart0";
315 ralink,function = "uart0"; 311 ralink,function = "uart0";
316 }; 312 };
317 }; 313 };
318   314  
319 uart1_pins: uart1 { 315 uart1_pins: uart1 {
320 uart1 { 316 uart1 {
321 ralink,group = "uart1"; 317 ralink,group = "uart1";
322 ralink,function = "uart1"; 318 ralink,function = "uart1";
323 }; 319 };
324 }; 320 };
325   321  
326 uart2_pins: uart2 { 322 uart2_pins: uart2 {
327 uart2 { 323 uart2 {
328 ralink,group = "uart2"; 324 ralink,group = "uart2";
329 ralink,function = "uart2"; 325 ralink,function = "uart2";
330 }; 326 };
331 }; 327 };
332   328  
333 sdxc_pins: sdxc { 329 sdxc_pins: sdxc {
334 sdxc { 330 sdxc {
335 ralink,group = "sdmode"; 331 ralink,group = "sdmode";
336 ralink,function = "sdxc"; 332 ralink,function = "sdxc";
337 }; 333 };
338 }; 334 };
339   335  
340 pwm0_pins: pwm0 { 336 pwm0_pins: pwm0 {
341 pwm0 { 337 pwm0 {
342 ralink,group = "pwm0"; 338 ralink,group = "pwm0";
343 ralink,function = "pwm0"; 339 ralink,function = "pwm0";
344 }; 340 };
345 }; 341 };
346   342  
347 pwm1_pins: pwm1 { 343 pwm1_pins: pwm1 {
348 pwm1 { 344 pwm1 {
349 ralink,group = "pwm1"; 345 ralink,group = "pwm1";
350 ralink,function = "pwm1"; 346 ralink,function = "pwm1";
351 }; 347 };
352 }; 348 };
353   349  
354 pcm_i2s_pins: pcm_i2s { 350 pcm_i2s_pins: pcm_i2s {
355 pcm_i2s { 351 pcm_i2s {
356 ralink,group = "i2s"; 352 ralink,group = "i2s";
357 ralink,function = "pcm"; 353 ralink,function = "pcm";
358 }; 354 };
359 }; 355 };
360   356  
361 refclk_pins: refclk { 357 refclk_pins: refclk {
362 refclk { 358 refclk {
363 ralink,group = "refclk"; 359 ralink,group = "refclk";
364 ralink,function = "refclk"; 360 ralink,function = "refclk";
365 }; 361 };
366 }; 362 };
367 }; 363 };
368   364  
369 rstctrl: rstctrl { 365 rstctrl: rstctrl {
370 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset"; 366 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
371 #reset-cells = <1>; 367 #reset-cells = <1>;
372 }; 368 };
373   369  
374 clkctrl: clkctrl { 370 clkctrl: clkctrl {
375 compatible = "ralink,rt2880-clock"; 371 compatible = "ralink,rt2880-clock";
376 #clock-cells = <1>; 372 #clock-cells = <1>;
377 }; 373 };
378   374  
379 usbphy: usbphy@10120000 { 375 usbphy: usbphy@10120000 {
380 compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy"; 376 compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
381 reg = <0x10120000 0x1000>; 377 reg = <0x10120000 0x1000>;
382 #phy-cells = <0>; 378 #phy-cells = <0>;
383   379  
384 ralink,sysctl = <&sysc>; 380 ralink,sysctl = <&sysc>;
385 resets = <&rstctrl 22 &rstctrl 25>; 381 resets = <&rstctrl 22 &rstctrl 25>;
386 reset-names = "host", "device"; 382 reset-names = "host", "device";
387 clocks = <&clkctrl 22 &clkctrl 25>; 383 clocks = <&clkctrl 22 &clkctrl 25>;
388 clock-names = "host", "device"; 384 clock-names = "host", "device";
389 }; 385 };
390   386  
391 sdhci: sdhci@10130000 { 387 sdhci: sdhci@10130000 {
392 compatible = "ralink,mt7620-sdhci"; 388 compatible = "ralink,mt7620-sdhci";
393 reg = <0x10130000 0x4000>; 389 reg = <0x10130000 0x4000>;
394   390  
395 interrupt-parent = <&intc>; 391 interrupt-parent = <&intc>;
396 interrupts = <14>; 392 interrupts = <14>;
397   393  
398 pinctrl-names = "default"; 394 pinctrl-names = "default";
399 pinctrl-0 = <&sdxc_pins>; 395 pinctrl-0 = <&sdxc_pins>;
400   396  
401 status = "disabled"; 397 status = "disabled";
402 }; 398 };
403   399  
404 ehci: ehci@101c0000 { 400 ehci: ehci@101c0000 {
405 #address-cells = <1>; -  
406 #size-cells = <0>; -  
407 compatible = "generic-ehci"; 401 compatible = "generic-ehci";
408 reg = <0x101c0000 0x1000>; 402 reg = <0x101c0000 0x1000>;
409   403  
410 phys = <&usbphy>; 404 phys = <&usbphy>;
411 phy-names = "usb"; 405 phy-names = "usb";
412   406  
413 interrupt-parent = <&intc>; 407 interrupt-parent = <&intc>;
414 interrupts = <18>; 408 interrupts = <18>;
415   -  
416 ehci_port1: port@1 { -  
417 reg = <1>; -  
418 #trigger-source-cells = <0>; -  
419 }; -  
420 }; 409 };
421   410  
422 ohci: ohci@101c1000 { 411 ohci: ohci@101c1000 {
423 #address-cells = <1>; -  
424 #size-cells = <0>; -  
425 compatible = "generic-ohci"; 412 compatible = "generic-ohci";
426 reg = <0x101c1000 0x1000>; 413 reg = <0x101c1000 0x1000>;
427   414  
428 phys = <&usbphy>; 415 phys = <&usbphy>;
429 phy-names = "usb"; 416 phy-names = "usb";
430   417  
431 interrupt-parent = <&intc>; 418 interrupt-parent = <&intc>;
432 interrupts = <18>; 419 interrupts = <18>;
433   -  
434 ohci_port1: port@1 { -  
435 reg = <1>; -  
436 #trigger-source-cells = <0>; -  
437 }; -  
438 }; 420 };
439   421  
440 ethernet: ethernet@10100000 { 422 ethernet: ethernet@10100000 {
441 compatible = "ralink,rt5350-eth"; 423 compatible = "ralink,rt5350-eth";
442 reg = <0x10100000 0x10000>; 424 reg = <0x10100000 0x10000>;
443   425  
444 interrupt-parent = <&cpuintc>; 426 interrupt-parent = <&cpuintc>;
445 interrupts = <5>; 427 interrupts = <5>;
446   428  
447 resets = <&rstctrl 21 &rstctrl 23>; 429 resets = <&rstctrl 21 &rstctrl 23>;
448 reset-names = "fe", "esw"; 430 reset-names = "fe", "esw";
449   431  
450 mediatek,switch = <&esw>; 432 mediatek,switch = <&esw>;
451 }; 433 };
452   434  
453 esw: esw@10110000 { 435 esw: esw@10110000 {
454 compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw"; 436 compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
455 reg = <0x10110000 0x8000>; 437 reg = <0x10110000 0x8000>;
456   438  
457 resets = <&rstctrl 23>; 439 resets = <&rstctrl 23>;
458 reset-names = "esw"; 440 reset-names = "esw";
459   441  
460 interrupt-parent = <&intc>; 442 interrupt-parent = <&intc>;
461 interrupts = <17>; 443 interrupts = <17>;
462 }; 444 };
463   445  
464 pcie: pcie@10140000 { 446 pcie: pcie@10140000 {
465 compatible = "mediatek,mt7620-pci"; 447 compatible = "mediatek,mt7620-pci";
466 reg = <0x10140000 0x100 448 reg = <0x10140000 0x100
467 0x10142000 0x100>; 449 0x10142000 0x100>;
468   450  
469 #address-cells = <3>; 451 #address-cells = <3>;
470 #size-cells = <2>; 452 #size-cells = <2>;
471   453  
472 interrupt-parent = <&cpuintc>; 454 interrupt-parent = <&cpuintc>;
473 interrupts = <4>; 455 interrupts = <4>;
474   456  
475 resets = <&rstctrl 26 &rstctrl 27>; 457 resets = <&rstctrl 26 &rstctrl 27>;
476 reset-names = "pcie0", "pcie1"; 458 reset-names = "pcie0", "pcie1";
477 clocks = <&clkctrl 26 &clkctrl 27>; 459 clocks = <&clkctrl 26 &clkctrl 27>;
478 clock-names = "pcie0", "pcie1"; 460 clock-names = "pcie0", "pcie1";
479   461  
480 status = "disabled"; 462 status = "disabled";
481   463  
482 device_type = "pci"; 464 device_type = "pci";
483   465  
484 bus-range = <0 255>; 466 bus-range = <0 255>;
485 ranges = < 467 ranges = <
486 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ 468 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
487 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ 469 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
488 >; 470 >;
489   471  
490 pcie0: pcie@0,0 { 472 pcie-bridge {
491 reg = <0x0000 0 0 0 0>; 473 reg = <0x0000 0 0 0 0>;
492   474  
493 #address-cells = <3>; 475 #address-cells = <3>;
494 #size-cells = <2>; 476 #size-cells = <2>;
495   477  
496 device_type = "pci"; 478 device_type = "pci";
497   -  
498 ranges; -  
499 }; 479 };
500 }; 480 };
501   481  
502 wmac: wmac@10300000 { 482 wmac: wmac@10300000 {
503 compatible = "mediatek,mt7628-wmac"; 483 compatible = "mediatek,mt7628-wmac";
504 reg = <0x10300000 0x100000>; 484 reg = <0x10300000 0x100000>;
505   485  
506 interrupt-parent = <&cpuintc>; 486 interrupt-parent = <&cpuintc>;
507 interrupts = <6>; 487 interrupts = <6>;
508   488  
509 status = "disabled"; 489 status = "disabled";
510   490  
511 mediatek,mtd-eeprom = <&factory 0x0000>; 491 mediatek,mtd-eeprom = <&factory 0x0000>;
512 }; 492 };
513 }; 493 };
514   494