OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
1 / { 1 / {
2 #address-cells = <1>; 2 #address-cells = <1>;
3 #size-cells = <1>; 3 #size-cells = <1>;
4 compatible = "ralink,mt7620a-soc"; 4 compatible = "ralink,mtk7620a-soc";
5   5  
6 cpus { -  
7 #address-cells = <1>; -  
8 #size-cells = <0>; -  
9   6 cpus {
10 cpu@0 { 7 cpu@0 {
11 compatible = "mips,mips24KEc"; -  
12 reg = <0>; 8 compatible = "mips,mips24KEc";
13 }; 9 };
14 }; 10 };
15   11  
16 chosen { 12 chosen {
17 bootargs = "console=ttyS0,57600"; 13 bootargs = "console=ttyS0,57600";
18 }; 14 };
19   15  
20 cpuintc: cpuintc { 16 cpuintc: cpuintc@0 {
21 #address-cells = <0>; 17 #address-cells = <0>;
22 #interrupt-cells = <1>; 18 #interrupt-cells = <1>;
23 interrupt-controller; 19 interrupt-controller;
24 compatible = "mti,cpu-interrupt-controller"; 20 compatible = "mti,cpu-interrupt-controller";
25 }; 21 };
26   22  
27 aliases { 23 aliases {
28 spi0 = &spi0; 24 spi0 = &spi0;
29 spi1 = &spi1; 25 spi1 = &spi1;
30 serial0 = &uartlite; 26 serial0 = &uartlite;
31 }; 27 };
32   28  
33 palmbus: palmbus@10000000 { 29 palmbus: palmbus@10000000 {
34 compatible = "palmbus"; 30 compatible = "palmbus";
35 reg = <0x10000000 0x200000>; 31 reg = <0x10000000 0x200000>;
36 ranges = <0x0 0x10000000 0x1FFFFF>; 32 ranges = <0x0 0x10000000 0x1FFFFF>;
37   33  
38 #address-cells = <1>; 34 #address-cells = <1>;
39 #size-cells = <1>; 35 #size-cells = <1>;
40   36  
41 sysc: sysc@0 { 37 sysc: sysc@0 {
42 compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon"; 38 compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
43 reg = <0x0 0x100>; 39 reg = <0x0 0x100>;
44 }; 40 };
45   41  
46 timer: timer@100 { 42 timer: timer@100 {
47 compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer"; 43 compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
48 reg = <0x100 0x20>; 44 reg = <0x100 0x20>;
49   45  
50 interrupt-parent = <&intc>; 46 interrupt-parent = <&intc>;
51 interrupts = <1>; 47 interrupts = <1>;
52 }; 48 };
53   49  
54 watchdog: watchdog@120 { 50 watchdog: watchdog@120 {
55 compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt"; 51 compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
56 reg = <0x120 0x10>; 52 reg = <0x120 0x10>;
57   53  
58 resets = <&rstctrl 8>; 54 resets = <&rstctrl 8>;
59 reset-names = "wdt"; 55 reset-names = "wdt";
60   56  
61 interrupt-parent = <&intc>; 57 interrupt-parent = <&intc>;
62 interrupts = <1>; 58 interrupts = <1>;
63 }; 59 };
64   60  
65 intc: intc@200 { 61 intc: intc@200 {
66 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; 62 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
67 reg = <0x200 0x100>; 63 reg = <0x200 0x100>;
68   64  
69 resets = <&rstctrl 19>; 65 resets = <&rstctrl 19>;
70 reset-names = "intc"; 66 reset-names = "intc";
71   67  
72 interrupt-controller; 68 interrupt-controller;
73 #interrupt-cells = <1>; 69 #interrupt-cells = <1>;
74   70  
75 interrupt-parent = <&cpuintc>; 71 interrupt-parent = <&cpuintc>;
76 interrupts = <2>; 72 interrupts = <2>;
77 }; 73 };
78   74  
79 memc: memc@300 { 75 memc: memc@300 {
80 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; 76 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
81 reg = <0x300 0x100>; 77 reg = <0x300 0x100>;
82   78  
83 resets = <&rstctrl 20>; 79 resets = <&rstctrl 20>;
84 reset-names = "mc"; 80 reset-names = "mc";
85   81  
86 interrupt-parent = <&intc>; 82 interrupt-parent = <&intc>;
87 interrupts = <3>; 83 interrupts = <3>;
88 }; 84 };
89   85  
90 uart: uart@500 { 86 uart: uart@500 {
91 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; 87 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
92 reg = <0x500 0x100>; 88 reg = <0x500 0x100>;
93   89  
94 resets = <&rstctrl 12>; 90 resets = <&rstctrl 12>;
95 reset-names = "uart"; 91 reset-names = "uart";
96   92  
97 interrupt-parent = <&intc>; 93 interrupt-parent = <&intc>;
98 interrupts = <5>; 94 interrupts = <5>;
99   95  
100 reg-shift = <2>; 96 reg-shift = <2>;
101   97  
102 status = "disabled"; 98 status = "disabled";
103 }; 99 };
104   100  
105 gpio0: gpio@600 { 101 gpio0: gpio@600 {
106 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; 102 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
107 reg = <0x600 0x34>; 103 reg = <0x600 0x34>;
108   104  
109 resets = <&rstctrl 13>; 105 resets = <&rstctrl 13>;
110 reset-names = "pio"; 106 reset-names = "pio";
111   107  
112 interrupt-parent = <&intc>; 108 interrupt-parent = <&intc>;
113 interrupts = <6>; 109 interrupts = <6>;
114   110  
115 gpio-controller; 111 gpio-controller;
116 #gpio-cells = <2>; 112 #gpio-cells = <2>;
117   113  
118 ralink,gpio-base = <0>; 114 ralink,gpio-base = <0>;
119 ralink,nr-gpio = <24>; 115 ralink,num-gpios = <24>;
120 ralink,register-map = [ 00 04 08 0c 116 ralink,register-map = [ 00 04 08 0c
121 20 24 28 2c 117 20 24 28 2c
122 30 34 ]; 118 30 34 ];
123 }; 119 };
124   120  
125 gpio1: gpio@638 { 121 gpio1: gpio@638 {
126 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; 122 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
127 reg = <0x638 0x24>; 123 reg = <0x638 0x24>;
128   124  
129 interrupt-parent = <&intc>; 125 interrupt-parent = <&intc>;
130 interrupts = <6>; 126 interrupts = <6>;
131   127  
132 gpio-controller; 128 gpio-controller;
133 #gpio-cells = <2>; 129 #gpio-cells = <2>;
134   130  
135 ralink,gpio-base = <24>; 131 ralink,gpio-base = <24>;
136 ralink,nr-gpio = <16>; 132 ralink,num-gpios = <16>;
137 ralink,register-map = [ 00 04 08 0c 133 ralink,register-map = [ 00 04 08 0c
138 10 14 18 1c 134 10 14 18 1c
139 20 24 ]; 135 20 24 ];
140   136  
141 status = "disabled"; 137 status = "disabled";
142 }; 138 };
143   139  
144 gpio2: gpio@660 { 140 gpio2: gpio@660 {
145 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; 141 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
146 reg = <0x660 0x24>; 142 reg = <0x660 0x24>;
147   143  
148 interrupt-parent = <&intc>; 144 interrupt-parent = <&intc>;
149 interrupts = <6>; 145 interrupts = <6>;
150   146  
151 gpio-controller; 147 gpio-controller;
152 #gpio-cells = <2>; 148 #gpio-cells = <2>;
153   149  
154 ralink,gpio-base = <40>; 150 ralink,gpio-base = <40>;
155 ralink,nr-gpio = <32>; 151 ralink,num-gpios = <32>;
156 ralink,register-map = [ 00 04 08 0c 152 ralink,register-map = [ 00 04 08 0c
157 10 14 18 1c 153 10 14 18 1c
158 20 24 ]; 154 20 24 ];
159   155  
160 status = "disabled"; 156 status = "disabled";
161 }; 157 };
162   158  
163 gpio3: gpio@688 { 159 gpio3: gpio@688 {
164 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio"; 160 compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
165 reg = <0x688 0x24>; 161 reg = <0x688 0x24>;
166   162  
167 interrupt-parent = <&intc>; 163 interrupt-parent = <&intc>;
168 interrupts = <6>; 164 interrupts = <6>;
169   165  
170 gpio-controller; 166 gpio-controller;
171 #gpio-cells = <2>; 167 #gpio-cells = <2>;
172   168  
173 ralink,gpio-base = <72>; 169 ralink,gpio-base = <72>;
174 ralink,nr-gpio = <1>; 170 ralink,num-gpios = <1>;
175 ralink,register-map = [ 00 04 08 0c 171 ralink,register-map = [ 00 04 08 0c
176 10 14 18 1c 172 10 14 18 1c
177 20 24 ]; 173 20 24 ];
178   174  
179 status = "disabled"; 175 status = "disabled";
180 }; 176 };
181   177  
182 i2c: i2c@900 { 178 i2c: i2c@900 {
183 compatible = "ralink,rt2880-i2c"; 179 compatible = "ralink,rt2880-i2c";
184 reg = <0x900 0x100>; 180 reg = <0x900 0x100>;
185   181  
186 resets = <&rstctrl 16>; 182 resets = <&rstctrl 16>;
187 reset-names = "i2c"; 183 reset-names = "i2c";
188   184  
189 #address-cells = <1>; 185 #address-cells = <1>;
190 #size-cells = <0>; 186 #size-cells = <0>;
191   187  
192 status = "disabled"; 188 status = "disabled";
193   189  
194 pinctrl-names = "default"; 190 pinctrl-names = "default";
195 pinctrl-0 = <&i2c_pins>; 191 pinctrl-0 = <&i2c_pins>;
196 }; 192 };
197   193  
198 i2s: i2s@a00 { 194 i2s: i2s@a00 {
199 compatible = "mediatek,mt7620-i2s"; 195 compatible = "mediatek,mt7620-i2s";
200 reg = <0xa00 0x100>; 196 reg = <0xa00 0x100>;
201   197  
202 resets = <&rstctrl 17>; 198 resets = <&rstctrl 17>;
203 reset-names = "i2s"; 199 reset-names = "i2s";
204   200  
205 interrupt-parent = <&intc>; 201 interrupt-parent = <&intc>;
206 interrupts = <10>; 202 interrupts = <10>;
207   203  
208 txdma-req = <2>; 204 txdma-req = <2>;
209 rxdma-req = <3>; 205 rxdma-req = <3>;
210   206  
211 dmas = <&gdma 4>, 207 dmas = <&gdma 4>,
212 <&gdma 6>; 208 <&gdma 6>;
213 dma-names = "tx", "rx"; 209 dma-names = "tx", "rx";
214   210  
215 status = "disabled"; 211 status = "disabled";
216 }; 212 };
217   213  
218 spi0: spi@b00 { 214 spi0: spi@b00 {
219 compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi"; 215 compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
220 reg = <0xb00 0x40>; 216 reg = <0xb00 0x40>;
221   217  
222 resets = <&rstctrl 18>; 218 resets = <&rstctrl 18>;
223 reset-names = "spi"; 219 reset-names = "spi";
224   220  
225 #address-cells = <1>; 221 #address-cells = <1>;
226 #size-cells = <0>; 222 #size-cells = <0>;
227   223  
228 status = "disabled"; 224 status = "disabled";
229   225  
230 pinctrl-names = "default"; 226 pinctrl-names = "default";
231 pinctrl-0 = <&spi_pins>; 227 pinctrl-0 = <&spi_pins>;
232 }; 228 };
233   229  
234 spi1: spi@b40 { 230 spi1: spi@b40 {
235 compatible = "ralink,rt2880-spi"; 231 compatible = "ralink,rt2880-spi";
236 reg = <0xb40 0x60>; 232 reg = <0xb40 0x60>;
237   233  
238 resets = <&rstctrl 18>; 234 resets = <&rstctrl 18>;
239 reset-names = "spi"; 235 reset-names = "spi";
240   236  
241 #address-cells = <1>; 237 #address-cells = <1>;
242 #size-cells = <0>; 238 #size-cells = <0>;
243   239  
244 status = "disabled"; 240 status = "disabled";
245   241  
246 pinctrl-names = "default"; 242 pinctrl-names = "default";
247 pinctrl-0 = <&spi_cs1>; 243 pinctrl-0 = <&spi_cs1>;
248 }; 244 };
249   245  
250 uartlite: uartlite@c00 { 246 uartlite: uartlite@c00 {
251 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; 247 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
252 reg = <0xc00 0x100>; 248 reg = <0xc00 0x100>;
253   249  
254 resets = <&rstctrl 19>; 250 resets = <&rstctrl 19>;
255 reset-names = "uartl"; 251 reset-names = "uartl";
256   252  
257 interrupt-parent = <&intc>; 253 interrupt-parent = <&intc>;
258 interrupts = <12>; 254 interrupts = <12>;
259   255  
260 reg-shift = <2>; 256 reg-shift = <2>;
261   257  
262 pinctrl-names = "default"; 258 pinctrl-names = "default";
263 pinctrl-0 = <&uartlite_pins>; 259 pinctrl-0 = <&uartlite_pins>;
264 }; 260 };
265   261  
266 systick: systick@d00 { 262 systick: systick@d00 {
267 compatible = "ralink,mt7620a-systick", "ralink,cevt-systick"; 263 compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
268 reg = <0xd00 0x10>; 264 reg = <0xd00 0x10>;
269   265  
270 resets = <&rstctrl 28>; 266 resets = <&rstctrl 28>;
271 reset-names = "intc"; 267 reset-names = "intc";
272   268  
273 interrupt-parent = <&cpuintc>; 269 interrupt-parent = <&cpuintc>;
274 interrupts = <7>; 270 interrupts = <7>;
275 }; 271 };
276   272  
277 pcm: pcm@2000 { 273 pcm: pcm@2000 {
278 compatible = "ralink,mt7620a-pcm"; 274 compatible = "ralink,mt7620a-pcm";
279 reg = <0x2000 0x800>; 275 reg = <0x2000 0x800>;
280   276  
281 resets = <&rstctrl 11>; 277 resets = <&rstctrl 11>;
282 reset-names = "pcm"; 278 reset-names = "pcm";
283   279  
284 interrupt-parent = <&intc>; 280 interrupt-parent = <&intc>;
285 interrupts = <4>; 281 interrupts = <4>;
286   282  
287 status = "disabled"; 283 status = "disabled";
288 }; 284 };
289   285  
290 gdma: gdma@2800 { 286 gdma: gdma@2800 {
291 compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma"; 287 compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
292 reg = <0x2800 0x800>; 288 reg = <0x2800 0x800>;
293   289  
294 resets = <&rstctrl 14>; 290 resets = <&rstctrl 14>;
295 reset-names = "dma"; 291 reset-names = "dma";
296   292  
297 interrupt-parent = <&intc>; 293 interrupt-parent = <&intc>;
298 interrupts = <7>; 294 interrupts = <7>;
299   295  
300 #dma-cells = <1>; 296 #dma-cells = <1>;
301 #dma-channels = <16>; 297 #dma-channels = <16>;
302 #dma-requests = <16>; 298 #dma-requests = <16>;
303   299  
304 status = "disabled"; 300 status = "disabled";
305 }; 301 };
306 }; 302 };
307   303  
308 pinctrl: pinctrl { 304 pinctrl: pinctrl {
309 compatible = "ralink,rt2880-pinmux"; 305 compatible = "ralink,rt2880-pinmux";
310 pinctrl-names = "default"; 306 pinctrl-names = "default";
311 pinctrl-0 = <&state_default>; 307 pinctrl-0 = <&state_default>;
312   308  
313 state_default: pinctrl0 { 309 state_default: pinctrl0 {
314 }; 310 };
315   311  
316 pcm_i2s_pins: pcm_i2s { 312 pcm_i2s_pins: pcm_i2s {
317 pcm_i2s { 313 pcm_i2s {
318 ralink,group = "uartf"; 314 ralink,group = "uartf";
319 ralink,function = "pcm i2s"; 315 ralink,function = "pcm i2s";
320 }; 316 };
321 }; 317 };
322   318  
323 uartf_gpio_pins: uartf_gpio { 319 uartf_gpio_pins: uartf_gpio {
324 uartf_gpio { 320 uartf_gpio {
325 ralink,group = "uartf"; 321 ralink,group = "uartf";
326 ralink,function = "gpio uartf"; 322 ralink,function = "gpio uartf";
327 }; 323 };
328 }; 324 };
329   325  
330 gpio_i2s_pins: gpio_i2s { 326 gpio_i2s_pins: gpio_i2s {
331 gpio_i2s { 327 gpio_i2s {
332 ralink,group = "uartf"; 328 ralink,group = "uartf";
333 ralink,function = "gpio i2s"; 329 ralink,function = "gpio i2s";
334 }; 330 };
335 }; 331 };
336   332  
337 spi_pins: spi_pins { 333 spi_pins: spi {
338 spi_pins { 334 spi {
339 ralink,group = "spi"; 335 ralink,group = "spi";
340 ralink,function = "spi"; 336 ralink,function = "spi";
341 }; 337 };
342 }; 338 };
343   339  
344 spi_cs1: spi1 { 340 spi_cs1: spi1 {
345 spi1 { 341 spi1 {
346 ralink,group = "spi refclk"; 342 ralink,group = "spi_cs1";
347 ralink,function = "spi refclk"; 343 ralink,function = "spi_cs1";
348 }; 344 };
349 }; 345 };
350   346  
351 i2c_pins: i2c_pins { 347 i2c_pins: i2c {
352 i2c_pins { 348 i2c {
353 ralink,group = "i2c"; 349 ralink,group = "i2c";
354 ralink,function = "i2c"; 350 ralink,function = "i2c";
355 }; 351 };
356 }; 352 };
357   353  
358 uartlite_pins: uartlite { 354 uartlite_pins: uartlite {
359 uart { 355 uart {
360 ralink,group = "uartlite"; 356 ralink,group = "uartlite";
361 ralink,function = "uartlite"; 357 ralink,function = "uartlite";
362 }; 358 };
363 }; 359 };
364   360  
365 mdio_pins: mdio { 361 mdio_pins: mdio {
366 mdio { 362 mdio {
367 ralink,group = "mdio"; 363 ralink,group = "mdio";
368 ralink,function = "mdio"; 364 ralink,function = "mdio";
369 }; 365 };
370 }; 366 };
371   367  
372 mdio_refclk_pins: mdio_refclk { 368 mdio_refclk_pins: mdio_refclk {
373 mdio_refclk { 369 mdio_refclk {
374 ralink,group = "mdio"; 370 ralink,group = "mdio";
375 ralink,function = "refclk"; 371 ralink,function = "refclk";
376 }; 372 };
377 }; 373 };
378   374  
379 ephy_pins: ephy { 375 ephy_pins: ephy {
380 ephy { 376 ephy {
381 ralink,group = "ephy"; 377 ralink,group = "ephy";
382 ralink,function = "ephy"; 378 ralink,function = "ephy";
383 }; 379 };
384 }; 380 };
385   381  
386 wled_pins: wled { 382 wled_pins: wled {
387 wled { 383 wled {
388 ralink,group = "wled"; 384 ralink,group = "wled";
389 ralink,function = "wled"; 385 ralink,function = "wled";
390 }; 386 };
391 }; 387 };
392   388  
393 rgmii1_pins: rgmii1 { 389 rgmii1_pins: rgmii1 {
394 rgmii1 { 390 rgmii1 {
395 ralink,group = "rgmii1"; 391 ralink,group = "rgmii1";
396 ralink,function = "rgmii1"; 392 ralink,function = "rgmii1";
397 }; 393 };
398 }; 394 };
399   395  
400 rgmii2_pins: rgmii2 { 396 rgmii2_pins: rgmii2 {
401 rgmii2 { 397 rgmii2 {
402 ralink,group = "rgmii2"; 398 ralink,group = "rgmii2";
403 ralink,function = "rgmii2"; 399 ralink,function = "rgmii2";
404 }; 400 };
405 }; 401 };
406   402  
407 pcie_pins: pcie { 403 pcie_pins: pcie {
408 pcie { 404 pcie {
409 ralink,group = "pcie"; 405 ralink,group = "pcie";
410 ralink,function = "pcie rst"; 406 ralink,function = "pcie rst";
411 }; 407 };
412 }; 408 };
413   409  
414 pa_pins: pa { 410 pa_pins: pa {
415 pa { 411 pa {
416 ralink,group = "pa"; 412 ralink,group = "pa";
417 ralink,function = "pa"; 413 ralink,function = "pa";
418 }; 414 };
419 }; 415 };
420   -  
421 sdhci_pins: sdhci { -  
422 sdhci { -  
423 ralink,group = "nd_sd"; -  
424 ralink,function = "sd"; -  
425 }; -  
426 }; -  
427 }; 416 };
428   417  
429 rstctrl: rstctrl { 418 rstctrl: rstctrl {
430 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset"; 419 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
431 #reset-cells = <1>; 420 #reset-cells = <1>;
432 }; 421 };
433   422  
434 clkctrl: clkctrl { 423 clkctrl: clkctrl {
435 compatible = "ralink,rt2880-clock"; 424 compatible = "ralink,rt2880-clock";
436 #clock-cells = <1>; 425 #clock-cells = <1>;
437 }; 426 };
438   427  
439 usbphy: usbphy { 428 usbphy: usbphy {
440 compatible = "mediatek,mt7620-usbphy"; 429 compatible = "mediatek,mt7620-usbphy";
441 #phy-cells = <0>; 430 #phy-cells = <0>;
442   431  
443 ralink,sysctl = <&sysc>; 432 ralink,sysctl = <&sysc>;
444 resets = <&rstctrl 22 &rstctrl 25>; 433 resets = <&rstctrl 22 &rstctrl 25>;
445 reset-names = "host", "device"; 434 reset-names = "host", "device";
446   435  
447 clocks = <&clkctrl 22 &clkctrl 25>; 436 clocks = <&clkctrl 22 &clkctrl 25>;
448 clock-names = "host", "device"; 437 clock-names = "host", "device";
449 }; 438 };
450   439  
451 ethernet: ethernet@10100000 { 440 ethernet: ethernet@10100000 {
452 compatible = "mediatek,mt7620-eth"; 441 compatible = "mediatek,mt7620-eth";
453 reg = <0x10100000 0x10000>; 442 reg = <0x10100000 0x10000>;
454   443  
455 #address-cells = <1>; 444 #address-cells = <1>;
456 #size-cells = <0>; 445 #size-cells = <0>;
457   446  
458 interrupt-parent = <&cpuintc>; 447 interrupt-parent = <&cpuintc>;
459 interrupts = <5>; 448 interrupts = <5>;
460   449  
461 resets = <&rstctrl 21 &rstctrl 23>; 450 resets = <&rstctrl 21 &rstctrl 23>;
462 reset-names = "fe", "esw"; 451 reset-names = "fe", "esw";
463   452  
464 mediatek,switch = <&gsw>; 453 mediatek,switch = <&gsw>;
465   454  
466 port@4 { 455 port@4 {
467 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port"; 456 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
468 reg = <4>; 457 reg = <4>;
469   458  
470 status = "disabled"; 459 status = "disabled";
471 }; 460 };
472   461  
473 port@5 { 462 port@5 {
474 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port"; 463 compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
475 reg = <5>; 464 reg = <5>;
476   465  
477 status = "disabled"; 466 status = "disabled";
478 }; 467 };
479   468  
480 mdio-bus { 469 mdio-bus {
481 #address-cells = <1>; 470 #address-cells = <1>;
482 #size-cells = <0>; 471 #size-cells = <0>;
483   472  
484 status = "disabled"; 473 status = "disabled";
485 }; 474 };
486 }; 475 };
487   476  
488 gsw: gsw@10110000 { 477 gsw: gsw@10110000 {
489 compatible = "mediatek,mt7620-gsw"; 478 compatible = "mediatek,mt7620-gsw";
490 reg = <0x10110000 0x8000>; 479 reg = <0x10110000 0x8000>;
491   480  
492 resets = <&rstctrl 23>; 481 resets = <&rstctrl 23>;
493 reset-names = "esw"; 482 reset-names = "esw";
494   483  
495 interrupt-parent = <&intc>; 484 interrupt-parent = <&intc>;
496 interrupts = <17>; 485 interrupts = <17>;
497 }; 486 };
498   487  
499 sdhci: sdhci@10130000 { 488 sdhci: sdhci@10130000 {
500 compatible = "ralink,mt7620-sdhci"; 489 compatible = "ralink,mt7620-sdhci";
501 reg = <0x10130000 0x4000>; 490 reg = <0x10130000 0x4000>;
502   491  
503 interrupt-parent = <&intc>; 492 interrupt-parent = <&intc>;
504 interrupts = <14>; 493 interrupts = <14>;
505   -  
506 pinctrl-names = "default"; -  
507 pinctrl-0 = <&sdhci_pins>; -  
508   494  
509 status = "disabled"; 495 status = "disabled";
510 }; 496 };
511   497  
512 ehci: ehci@101c0000 { 498 ehci: ehci@101c0000 {
513 #address-cells = <1>; -  
514 #size-cells = <0>; -  
515 compatible = "generic-ehci"; 499 compatible = "generic-ehci";
516 reg = <0x101c0000 0x1000>; 500 reg = <0x101c0000 0x1000>;
517   501  
518 interrupt-parent = <&intc>; 502 interrupt-parent = <&intc>;
519 interrupts = <18>; 503 interrupts = <18>;
520   504  
521 phys = <&usbphy>; 505 phys = <&usbphy>;
522 phy-names = "usb"; 506 phy-names = "usb";
523   507  
524 status = "disabled"; 508 status = "disabled";
525   -  
526 ehci_port1: port@1 { -  
527 reg = <1>; -  
528 #trigger-source-cells = <0>; -  
529 }; -  
530 }; 509 };
531   510  
532 ohci: ohci@101c1000 { 511 ohci: ohci@101c1000 {
533 #address-cells = <1>; -  
534 #size-cells = <0>; -  
535 compatible = "generic-ohci"; 512 compatible = "generic-ohci";
536 reg = <0x101c1000 0x1000>; 513 reg = <0x101c1000 0x1000>;
537   514  
538 interrupt-parent = <&intc>; 515 interrupt-parent = <&intc>;
539 interrupts = <18>; 516 interrupts = <18>;
540   517  
541 phys = <&usbphy>; 518 phys = <&usbphy>;
542 phy-names = "usb"; 519 phy-names = "usb";
543   520  
544 status = "disabled"; 521 status = "disabled";
545   -  
546 ohci_port1: port@1 { -  
547 reg = <1>; -  
548 #trigger-source-cells = <0>; -  
549 }; -  
550 }; 522 };
551   523  
552 pcie: pcie@10140000 { 524 pcie: pcie@10140000 {
553 compatible = "mediatek,mt7620-pci"; 525 compatible = "mediatek,mt7620-pci";
554 reg = <0x10140000 0x100 526 reg = <0x10140000 0x100
555 0x10142000 0x100>; 527 0x10142000 0x100>;
556   528  
557 #address-cells = <3>; 529 #address-cells = <3>;
558 #size-cells = <2>; 530 #size-cells = <2>;
559   531  
560 resets = <&rstctrl 26>; 532 resets = <&rstctrl 26>;
561 reset-names = "pcie0"; 533 reset-names = "pcie0";
562   534  
563 clocks = <&clkctrl 26>; 535 clocks = <&clkctrl 26>;
564 clock-names = "pcie0"; 536 clock-names = "pcie0";
565   537  
566 interrupt-parent = <&cpuintc>; 538 interrupt-parent = <&cpuintc>;
567 interrupts = <4>; 539 interrupts = <4>;
568   540  
569 pinctrl-names = "default"; 541 pinctrl-names = "default";
570 pinctrl-0 = <&pcie_pins>; 542 pinctrl-0 = <&pcie_pins>;
571   543  
572 device_type = "pci"; 544 device_type = "pci";
573   545  
574 bus-range = <0 255>; 546 bus-range = <0 255>;
575 ranges = < 547 ranges = <
576 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ 548 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
577 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ 549 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
578 >; 550 >;
579   551  
580 status = "disabled"; 552 status = "disabled";
581   553  
582 pcie0: pcie@0,0 { 554 pcie-bridge {
583 reg = <0x0000 0 0 0 0>; 555 reg = <0x0000 0 0 0 0>;
584   556  
585 #address-cells = <3>; 557 #address-cells = <3>;
586 #size-cells = <2>; 558 #size-cells = <2>;
587   559  
588 device_type = "pci"; 560 device_type = "pci";
589   -  
590 ranges; -  
591 }; 561 };
592 }; 562 };
593   563  
594 wmac: wmac@10180000 { 564 wmac: wmac@10180000 {
595 compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac"; 565 compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
596 reg = <0x10180000 0x40000>; 566 reg = <0x10180000 0x40000>;
597   567  
598 interrupt-parent = <&cpuintc>; 568 interrupt-parent = <&cpuintc>;
599 interrupts = <6>; 569 interrupts = <6>;
600   570  
601 ralink,eeprom = "soc_wmac.eeprom"; 571 ralink,eeprom = "soc_wmac.eeprom";
602 }; 572 };
603 }; 573 };
604   574