OpenWrt – Diff between revs 2 and 3

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Rev 2 Rev 3
1 /dts-v1/; 1 /dts-v1/;
2   2  
3 #include "mt7620a.dtsi" 3 #include "mt7620a.dtsi"
4   4  
5 #include <dt-bindings/gpio/gpio.h> 5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h> 6 #include <dt-bindings/input/input.h>
7   7  
8 / { 8 / {
9 compatible = "planex,cs-qr10", "ralink,mt7620a-soc"; 9 compatible = "planex,cs-qr10", "ralink,mt7620a-soc";
10 model = "Planex CS-QR10"; 10 model = "Planex CS-QR10";
11   -  
12 aliases { -  
13 led-boot = &led_power; -  
14 led-failsafe = &led_power; -  
15 led-running = &led_power; -  
16 led-upgrade = &led_power; -  
17 }; -  
18   11  
19 leds { 12 gpio-leds {
20 compatible = "gpio-leds"; 13 compatible = "gpio-leds";
21   14  
22 led_power: power { 15 power {
23 label = "cs-qr10:red:power"; 16 label = "cs-qr10:red:power";
24 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 17 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
25 }; 18 };
26 }; 19 };
27   20  
28 keys { 21 gpio-keys-polled {
-   22 compatible = "gpio-keys-polled";
-   23 #address-cells = <1>;
29 compatible = "gpio-keys-polled"; 24 #size-cells = <0>;
30 poll-interval = <20>; 25 poll-interval = <20>;
31   26  
32 s1 { 27 s1 {
33 label = "reset"; 28 label = "reset";
34 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 29 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_RESTART>; 30 linux,code = <KEY_RESTART>;
36 }; 31 };
37   32  
38 s2 { 33 s2 {
39 label = "wps"; 34 label = "wps";
40 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 35 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
41 linux,code = <KEY_WPS_BUTTON>; 36 linux,code = <KEY_WPS_BUTTON>;
42 }; 37 };
43 }; 38 };
44 }; 39 };
45   40  
46 &gpio0 { 41 &gpio0 {
47 status = "okay"; 42 status = "okay";
48 }; 43 };
49   44  
50 &gpio1 { 45 &gpio1 {
51 status = "okay"; 46 status = "okay";
52 }; 47 };
53   48  
54 &gpio2 { 49 &gpio2 {
55 status = "okay"; 50 status = "okay";
56 }; 51 };
57   52  
58 &gpio3 { 53 &gpio3 {
59 status = "okay"; 54 status = "okay";
60 }; 55 };
61   56  
62 &i2c { 57 &i2c {
63 status = "okay"; 58 status = "okay";
64 }; 59 };
65   60  
66 &i2s { 61 &i2s {
67 status = "okay"; 62 status = "okay";
68 pinctrl-names = "default"; 63 pinctrl-names = "default";
69 pinctrl-0 = <&pcm_i2s_pins>; 64 pinctrl-0 = <&pcm_i2s_pins>;
70 }; 65 };
71   66  
72 &spi0 { 67 &spi0 {
73 status = "okay"; 68 status = "okay";
74   69  
75 m25p80@0 { 70 m25p80@0 {
-   71 #address-cells = <1>;
-   72 #size-cells = <1>;
76 compatible = "jedec,spi-nor"; 73 compatible = "jedec,spi-nor";
77 reg = <0>; 74 reg = <0>;
78 spi-max-frequency = <10000000>; 75 spi-max-frequency = <10000000>;
79   -  
80 partitions { -  
81 compatible = "fixed-partitions"; -  
82 #address-cells = <1>; -  
83 #size-cells = <1>; -  
84   76  
85 partition@0 { 77 partition@0 {
86 label = "u-boot"; 78 label = "u-boot";
87 reg = <0x0 0x30000>; 79 reg = <0x0 0x30000>;
88 read-only; 80 read-only;
89 }; 81 };
90   82  
91 partition@30000 { 83 partition@30000 {
92 label = "u-boot-env"; 84 label = "u-boot-env";
93 reg = <0x30000 0x10000>; 85 reg = <0x30000 0x10000>;
94 read-only; 86 read-only;
95 }; 87 };
96   88  
97 factory: partition@40000 { 89 factory: partition@40000 {
98 label = "factory"; 90 label = "factory";
99 reg = <0x40000 0x10000>; 91 reg = <0x40000 0x10000>;
100 read-only; 92 read-only;
101 }; 93 };
102   94  
103 partition@50000 { -  
104 compatible = "denx,uimage"; 95 partition@50000 {
105 label = "firmware"; 96 label = "firmware";
106 reg = <0x50000 0x7b0000>; -  
107 }; 97 reg = <0x50000 0x7b0000>;
108 }; 98 };
109 }; 99 };
110 }; 100 };
111   101  
112 &pcm { 102 &pcm {
113 status = "okay"; 103 status = "okay";
114 }; 104 };
115   105  
116 &gdma { 106 &gdma {
117 status = "okay"; 107 status = "okay";
118 }; 108 };
119   109  
120 &pinctrl { 110 &pinctrl {
121 state_default: pinctrl0 { 111 state_default: pinctrl0 {
122 gpio { 112 gpio {
123 ralink,group = "spi refclk", "rgmii1"; 113 ralink,group = "spi refclk", "rgmii1";
124 ralink,function = "gpio"; 114 ralink,function = "gpio";
125 }; 115 };
126 wdt { 116 wdt {
127 ralink,group = "wdt"; 117 ralink,group = "wdt";
128 ralink,function = "wdt refclk"; 118 ralink,function = "wdt refclk";
129 }; 119 };
130 }; 120 };
131 }; 121 };
132   122  
133 &ethernet { 123 &ethernet {
134 pinctrl-names = "default"; 124 pinctrl-names = "default";
135 pinctrl-0 = <&ephy_pins>; 125 pinctrl-0 = <&ephy_pins>;
136 mtd-mac-address = <&factory 0x4>; 126 mtd-mac-address = <&factory 0x4>;
137 mediatek,portmap = "llllw"; 127 mediatek,portmap = "llllw";
138 }; 128 };
139   129  
140 &gsw { 130 &gsw {
141 ralink,port4 = "ephy"; 131 ralink,port4 = "ephy";
142 }; 132 };
143   133  
144 &sdhci { 134 &sdhci {
145 status = "okay"; 135 status = "okay";
146 }; 136 };
147   137  
148 &ehci { 138 &ehci {
149 status = "okay"; 139 status = "okay";
150 }; 140 };
151   141  
152 &ohci { 142 &ohci {
153 status = "okay"; 143 status = "okay";
154 }; 144 };
155   145  
156 &wmac { 146 &wmac {
157 ralink,mtd-eeprom = <&factory 0>; 147 ralink,mtd-eeprom = <&factory 0>;
158 }; 148 };
-   149  
-   150 &pcie {
-   151 status = "okay";
-   152 };
159   153