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1 /* 1 /*
2 * Platform driver for the Realtek RTL8367R/M ethernet switches 2 * Platform driver for the Realtek RTL8367R/M ethernet switches
3 * 3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published 7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation. 8 * by the Free Software Foundation.
9 */ 9 */
10   10  
11 #include <linux/kernel.h> 11 #include <linux/kernel.h>
12 #include <linux/module.h> 12 #include <linux/module.h>
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/device.h> 14 #include <linux/device.h>
15 #include <linux/of.h> 15 #include <linux/of.h>
16 #include <linux/of_platform.h> 16 #include <linux/of_platform.h>
17 #include <linux/delay.h> 17 #include <linux/delay.h>
18 #include <linux/skbuff.h> 18 #include <linux/skbuff.h>
19 #include <linux/rtl8367.h> 19 #include <linux/rtl8367.h>
20   20  
21 #include "rtl8366_smi.h" 21 #include "rtl8366_smi.h"
22   22  
23 #define RTL8367_RESET_DELAY 1000 /* msecs*/ 23 #define RTL8367_RESET_DELAY 1000 /* msecs*/
24   24  
25 #define RTL8367_PHY_ADDR_MAX 8 25 #define RTL8367_PHY_ADDR_MAX 8
26 #define RTL8367_PHY_REG_MAX 31 26 #define RTL8367_PHY_REG_MAX 31
27   27  
28 #define RTL8367_VID_MASK 0xffff 28 #define RTL8367_VID_MASK 0xffff
29 #define RTL8367_FID_MASK 0xfff 29 #define RTL8367_FID_MASK 0xfff
30 #define RTL8367_UNTAG_MASK 0xffff 30 #define RTL8367_UNTAG_MASK 0xffff
31 #define RTL8367_MEMBER_MASK 0xffff 31 #define RTL8367_MEMBER_MASK 0xffff
32   32  
33 #define RTL8367_PORT_CFG_REG(_p) (0x000e + 0x20 * (_p)) 33 #define RTL8367_PORT_CFG_REG(_p) (0x000e + 0x20 * (_p))
34 #define RTL8367_PORT_CFG_EGRESS_MODE_SHIFT 4 34 #define RTL8367_PORT_CFG_EGRESS_MODE_SHIFT 4
35 #define RTL8367_PORT_CFG_EGRESS_MODE_MASK 0x3 35 #define RTL8367_PORT_CFG_EGRESS_MODE_MASK 0x3
36 #define RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL 0 36 #define RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL 0
37 #define RTL8367_PORT_CFG_EGRESS_MODE_KEEP 1 37 #define RTL8367_PORT_CFG_EGRESS_MODE_KEEP 1
38 #define RTL8367_PORT_CFG_EGRESS_MODE_PRI 2 38 #define RTL8367_PORT_CFG_EGRESS_MODE_PRI 2
39 #define RTL8367_PORT_CFG_EGRESS_MODE_REAL 3 39 #define RTL8367_PORT_CFG_EGRESS_MODE_REAL 3
40   40  
41 #define RTL8367_BYPASS_LINE_RATE_REG 0x03f7 41 #define RTL8367_BYPASS_LINE_RATE_REG 0x03f7
42   42  
43 #define RTL8367_TA_CTRL_REG 0x0500 43 #define RTL8367_TA_CTRL_REG 0x0500
44 #define RTL8367_TA_CTRL_STATUS BIT(12) 44 #define RTL8367_TA_CTRL_STATUS BIT(12)
45 #define RTL8367_TA_CTRL_METHOD BIT(5) 45 #define RTL8367_TA_CTRL_METHOD BIT(5)
46 #define RTL8367_TA_CTRL_CMD_SHIFT 4 46 #define RTL8367_TA_CTRL_CMD_SHIFT 4
47 #define RTL8367_TA_CTRL_CMD_READ 0 47 #define RTL8367_TA_CTRL_CMD_READ 0
48 #define RTL8367_TA_CTRL_CMD_WRITE 1 48 #define RTL8367_TA_CTRL_CMD_WRITE 1
49 #define RTL8367_TA_CTRL_TABLE_SHIFT 0 49 #define RTL8367_TA_CTRL_TABLE_SHIFT 0
50 #define RTL8367_TA_CTRL_TABLE_ACLRULE 1 50 #define RTL8367_TA_CTRL_TABLE_ACLRULE 1
51 #define RTL8367_TA_CTRL_TABLE_ACLACT 2 51 #define RTL8367_TA_CTRL_TABLE_ACLACT 2
52 #define RTL8367_TA_CTRL_TABLE_CVLAN 3 52 #define RTL8367_TA_CTRL_TABLE_CVLAN 3
53 #define RTL8367_TA_CTRL_TABLE_L2 4 53 #define RTL8367_TA_CTRL_TABLE_L2 4
54 #define RTL8367_TA_CTRL_CVLAN_READ \ 54 #define RTL8367_TA_CTRL_CVLAN_READ \
55 ((RTL8367_TA_CTRL_CMD_READ << RTL8367_TA_CTRL_CMD_SHIFT) | \ 55 ((RTL8367_TA_CTRL_CMD_READ << RTL8367_TA_CTRL_CMD_SHIFT) | \
56 RTL8367_TA_CTRL_TABLE_CVLAN) 56 RTL8367_TA_CTRL_TABLE_CVLAN)
57 #define RTL8367_TA_CTRL_CVLAN_WRITE \ 57 #define RTL8367_TA_CTRL_CVLAN_WRITE \
58 ((RTL8367_TA_CTRL_CMD_WRITE << RTL8367_TA_CTRL_CMD_SHIFT) | \ 58 ((RTL8367_TA_CTRL_CMD_WRITE << RTL8367_TA_CTRL_CMD_SHIFT) | \
59 RTL8367_TA_CTRL_TABLE_CVLAN) 59 RTL8367_TA_CTRL_TABLE_CVLAN)
60   60  
61 #define RTL8367_TA_ADDR_REG 0x0501 61 #define RTL8367_TA_ADDR_REG 0x0501
62 #define RTL8367_TA_ADDR_MASK 0x3fff 62 #define RTL8367_TA_ADDR_MASK 0x3fff
63   63  
64 #define RTL8367_TA_DATA_REG(_x) (0x0503 + (_x)) 64 #define RTL8367_TA_DATA_REG(_x) (0x0503 + (_x))
65 #define RTL8367_TA_VLAN_DATA_SIZE 4 65 #define RTL8367_TA_VLAN_DATA_SIZE 4
66 #define RTL8367_TA_VLAN_VID_MASK RTL8367_VID_MASK 66 #define RTL8367_TA_VLAN_VID_MASK RTL8367_VID_MASK
67 #define RTL8367_TA_VLAN_MEMBER_SHIFT 0 67 #define RTL8367_TA_VLAN_MEMBER_SHIFT 0
68 #define RTL8367_TA_VLAN_MEMBER_MASK RTL8367_MEMBER_MASK 68 #define RTL8367_TA_VLAN_MEMBER_MASK RTL8367_MEMBER_MASK
69 #define RTL8367_TA_VLAN_FID_SHIFT 0 69 #define RTL8367_TA_VLAN_FID_SHIFT 0
70 #define RTL8367_TA_VLAN_FID_MASK RTL8367_FID_MASK 70 #define RTL8367_TA_VLAN_FID_MASK RTL8367_FID_MASK
71 #define RTL8367_TA_VLAN_UNTAG1_SHIFT 14 71 #define RTL8367_TA_VLAN_UNTAG1_SHIFT 14
72 #define RTL8367_TA_VLAN_UNTAG1_MASK 0x3 72 #define RTL8367_TA_VLAN_UNTAG1_MASK 0x3
73 #define RTL8367_TA_VLAN_UNTAG2_SHIFT 0 73 #define RTL8367_TA_VLAN_UNTAG2_SHIFT 0
74 #define RTL8367_TA_VLAN_UNTAG2_MASK 0x3fff 74 #define RTL8367_TA_VLAN_UNTAG2_MASK 0x3fff
75   75  
76 #define RTL8367_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2) 76 #define RTL8367_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2)
77 #define RTL8367_VLAN_PVID_CTRL_MASK 0x1f 77 #define RTL8367_VLAN_PVID_CTRL_MASK 0x1f
78 #define RTL8367_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2)) 78 #define RTL8367_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2))
79   79  
80 #define RTL8367_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4) 80 #define RTL8367_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4)
81 #define RTL8367_VLAN_MC_DATA_SIZE 4 81 #define RTL8367_VLAN_MC_DATA_SIZE 4
82 #define RTL8367_VLAN_MC_MEMBER_SHIFT 0 82 #define RTL8367_VLAN_MC_MEMBER_SHIFT 0
83 #define RTL8367_VLAN_MC_MEMBER_MASK RTL8367_MEMBER_MASK 83 #define RTL8367_VLAN_MC_MEMBER_MASK RTL8367_MEMBER_MASK
84 #define RTL8367_VLAN_MC_FID_SHIFT 0 84 #define RTL8367_VLAN_MC_FID_SHIFT 0
85 #define RTL8367_VLAN_MC_FID_MASK RTL8367_FID_MASK 85 #define RTL8367_VLAN_MC_FID_MASK RTL8367_FID_MASK
86 #define RTL8367_VLAN_MC_EVID_SHIFT 0 86 #define RTL8367_VLAN_MC_EVID_SHIFT 0
87 #define RTL8367_VLAN_MC_EVID_MASK RTL8367_VID_MASK 87 #define RTL8367_VLAN_MC_EVID_MASK RTL8367_VID_MASK
88   88  
89 #define RTL8367_VLAN_CTRL_REG 0x07a8 89 #define RTL8367_VLAN_CTRL_REG 0x07a8
90 #define RTL8367_VLAN_CTRL_ENABLE BIT(0) 90 #define RTL8367_VLAN_CTRL_ENABLE BIT(0)
91   91  
92 #define RTL8367_VLAN_INGRESS_REG 0x07a9 92 #define RTL8367_VLAN_INGRESS_REG 0x07a9
93   93  
94 #define RTL8367_PORT_ISOLATION_REG(_p) (0x08a2 + (_p)) 94 #define RTL8367_PORT_ISOLATION_REG(_p) (0x08a2 + (_p))
95   95  
96 #define RTL8367_MIB_COUNTER_REG(_x) (0x1000 + (_x)) 96 #define RTL8367_MIB_COUNTER_REG(_x) (0x1000 + (_x))
97   97  
98 #define RTL8367_MIB_ADDRESS_REG 0x1004 98 #define RTL8367_MIB_ADDRESS_REG 0x1004
99   99  
100 #define RTL8367_MIB_CTRL_REG(_x) (0x1005 + (_x)) 100 #define RTL8367_MIB_CTRL_REG(_x) (0x1005 + (_x))
101 #define RTL8367_MIB_CTRL_GLOBAL_RESET_MASK BIT(11) 101 #define RTL8367_MIB_CTRL_GLOBAL_RESET_MASK BIT(11)
102 #define RTL8367_MIB_CTRL_QM_RESET_MASK BIT(10) 102 #define RTL8367_MIB_CTRL_QM_RESET_MASK BIT(10)
103 #define RTL8367_MIB_CTRL_PORT_RESET_MASK(_p) BIT(2 + (_p)) 103 #define RTL8367_MIB_CTRL_PORT_RESET_MASK(_p) BIT(2 + (_p))
104 #define RTL8367_MIB_CTRL_RESET_MASK BIT(1) 104 #define RTL8367_MIB_CTRL_RESET_MASK BIT(1)
105 #define RTL8367_MIB_CTRL_BUSY_MASK BIT(0) 105 #define RTL8367_MIB_CTRL_BUSY_MASK BIT(0)
106   106  
107 #define RTL8367_MIB_COUNT 36 107 #define RTL8367_MIB_COUNT 36
108 #define RTL8367_MIB_COUNTER_PORT_OFFSET 0x0050 108 #define RTL8367_MIB_COUNTER_PORT_OFFSET 0x0050
109   109  
110 #define RTL8367_SWC0_REG 0x1200 110 #define RTL8367_SWC0_REG 0x1200
111 #define RTL8367_SWC0_MAX_LENGTH_SHIFT 13 111 #define RTL8367_SWC0_MAX_LENGTH_SHIFT 13
112 #define RTL8367_SWC0_MAX_LENGTH(_x) ((_x) << 13) 112 #define RTL8367_SWC0_MAX_LENGTH(_x) ((_x) << 13)
113 #define RTL8367_SWC0_MAX_LENGTH_MASK RTL8367_SWC0_MAX_LENGTH(0x3) 113 #define RTL8367_SWC0_MAX_LENGTH_MASK RTL8367_SWC0_MAX_LENGTH(0x3)
114 #define RTL8367_SWC0_MAX_LENGTH_1522 RTL8367_SWC0_MAX_LENGTH(0) 114 #define RTL8367_SWC0_MAX_LENGTH_1522 RTL8367_SWC0_MAX_LENGTH(0)
115 #define RTL8367_SWC0_MAX_LENGTH_1536 RTL8367_SWC0_MAX_LENGTH(1) 115 #define RTL8367_SWC0_MAX_LENGTH_1536 RTL8367_SWC0_MAX_LENGTH(1)
116 #define RTL8367_SWC0_MAX_LENGTH_1552 RTL8367_SWC0_MAX_LENGTH(2) 116 #define RTL8367_SWC0_MAX_LENGTH_1552 RTL8367_SWC0_MAX_LENGTH(2)
117 #define RTL8367_SWC0_MAX_LENGTH_16000 RTL8367_SWC0_MAX_LENGTH(3) 117 #define RTL8367_SWC0_MAX_LENGTH_16000 RTL8367_SWC0_MAX_LENGTH(3)
118   118  
119 #define RTL8367_CHIP_NUMBER_REG 0x1300 119 #define RTL8367_CHIP_NUMBER_REG 0x1300
120   120  
121 #define RTL8367_CHIP_VER_REG 0x1301 121 #define RTL8367_CHIP_VER_REG 0x1301
122 #define RTL8367_CHIP_VER_RLVID_SHIFT 12 122 #define RTL8367_CHIP_VER_RLVID_SHIFT 12
123 #define RTL8367_CHIP_VER_RLVID_MASK 0xf 123 #define RTL8367_CHIP_VER_RLVID_MASK 0xf
124 #define RTL8367_CHIP_VER_MCID_SHIFT 8 124 #define RTL8367_CHIP_VER_MCID_SHIFT 8
125 #define RTL8367_CHIP_VER_MCID_MASK 0xf 125 #define RTL8367_CHIP_VER_MCID_MASK 0xf
126 #define RTL8367_CHIP_VER_BOID_SHIFT 4 126 #define RTL8367_CHIP_VER_BOID_SHIFT 4
127 #define RTL8367_CHIP_VER_BOID_MASK 0xf 127 #define RTL8367_CHIP_VER_BOID_MASK 0xf
128   128  
129 #define RTL8367_CHIP_MODE_REG 0x1302 129 #define RTL8367_CHIP_MODE_REG 0x1302
130 #define RTL8367_CHIP_MODE_MASK 0x7 130 #define RTL8367_CHIP_MODE_MASK 0x7
131   131  
132 #define RTL8367_CHIP_DEBUG0_REG 0x1303 132 #define RTL8367_CHIP_DEBUG0_REG 0x1303
133 #define RTL8367_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x)) 133 #define RTL8367_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x))
134   134  
135 #define RTL8367_CHIP_DEBUG1_REG 0x1304 135 #define RTL8367_CHIP_DEBUG1_REG 0x1304
136   136  
137 #define RTL8367_DIS_REG 0x1305 137 #define RTL8367_DIS_REG 0x1305
138 #define RTL8367_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x)) 138 #define RTL8367_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
139 #define RTL8367_DIS_RGMII_SHIFT(_x) (4 * (_x)) 139 #define RTL8367_DIS_RGMII_SHIFT(_x) (4 * (_x))
140 #define RTL8367_DIS_RGMII_MASK 0x7 140 #define RTL8367_DIS_RGMII_MASK 0x7
141   141  
142 #define RTL8367_EXT_RGMXF_REG(_x) (0x1306 + (_x)) 142 #define RTL8367_EXT_RGMXF_REG(_x) (0x1306 + (_x))
143 #define RTL8367_EXT_RGMXF_DUMMY0_SHIFT 5 143 #define RTL8367_EXT_RGMXF_DUMMY0_SHIFT 5
144 #define RTL8367_EXT_RGMXF_DUMMY0_MASK 0x7ff 144 #define RTL8367_EXT_RGMXF_DUMMY0_MASK 0x7ff
145 #define RTL8367_EXT_RGMXF_TXDELAY_SHIFT 3 145 #define RTL8367_EXT_RGMXF_TXDELAY_SHIFT 3
146 #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1 146 #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1
147 #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7 147 #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7
148   148  
149 #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x)) 149 #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x))
150 #define RTL8367_DI_FORCE_MODE BIT(12) 150 #define RTL8367_DI_FORCE_MODE BIT(12)
151 #define RTL8367_DI_FORCE_NWAY BIT(7) 151 #define RTL8367_DI_FORCE_NWAY BIT(7)
152 #define RTL8367_DI_FORCE_TXPAUSE BIT(6) 152 #define RTL8367_DI_FORCE_TXPAUSE BIT(6)
153 #define RTL8367_DI_FORCE_RXPAUSE BIT(5) 153 #define RTL8367_DI_FORCE_RXPAUSE BIT(5)
154 #define RTL8367_DI_FORCE_LINK BIT(4) 154 #define RTL8367_DI_FORCE_LINK BIT(4)
155 #define RTL8367_DI_FORCE_DUPLEX BIT(2) 155 #define RTL8367_DI_FORCE_DUPLEX BIT(2)
156 #define RTL8367_DI_FORCE_SPEED_MASK 3 156 #define RTL8367_DI_FORCE_SPEED_MASK 3
157 #define RTL8367_DI_FORCE_SPEED_10 0 157 #define RTL8367_DI_FORCE_SPEED_10 0
158 #define RTL8367_DI_FORCE_SPEED_100 1 158 #define RTL8367_DI_FORCE_SPEED_100 1
159 #define RTL8367_DI_FORCE_SPEED_1000 2 159 #define RTL8367_DI_FORCE_SPEED_1000 2
160   160  
161 #define RTL8367_MAC_FORCE_REG(_x) (0x1312 + (_x)) 161 #define RTL8367_MAC_FORCE_REG(_x) (0x1312 + (_x))
162   162  
163 #define RTL8367_CHIP_RESET_REG 0x1322 163 #define RTL8367_CHIP_RESET_REG 0x1322
164 #define RTL8367_CHIP_RESET_SW BIT(1) 164 #define RTL8367_CHIP_RESET_SW BIT(1)
165 #define RTL8367_CHIP_RESET_HW BIT(0) 165 #define RTL8367_CHIP_RESET_HW BIT(0)
166   166  
167 #define RTL8367_PORT_STATUS_REG(_p) (0x1352 + (_p)) 167 #define RTL8367_PORT_STATUS_REG(_p) (0x1352 + (_p))
168 #define RTL8367_PORT_STATUS_NWAY BIT(7) 168 #define RTL8367_PORT_STATUS_NWAY BIT(7)
169 #define RTL8367_PORT_STATUS_TXPAUSE BIT(6) 169 #define RTL8367_PORT_STATUS_TXPAUSE BIT(6)
170 #define RTL8367_PORT_STATUS_RXPAUSE BIT(5) 170 #define RTL8367_PORT_STATUS_RXPAUSE BIT(5)
171 #define RTL8367_PORT_STATUS_LINK BIT(4) 171 #define RTL8367_PORT_STATUS_LINK BIT(4)
172 #define RTL8367_PORT_STATUS_DUPLEX BIT(2) 172 #define RTL8367_PORT_STATUS_DUPLEX BIT(2)
173 #define RTL8367_PORT_STATUS_SPEED_MASK 0x0003 173 #define RTL8367_PORT_STATUS_SPEED_MASK 0x0003
174 #define RTL8367_PORT_STATUS_SPEED_10 0 174 #define RTL8367_PORT_STATUS_SPEED_10 0
175 #define RTL8367_PORT_STATUS_SPEED_100 1 175 #define RTL8367_PORT_STATUS_SPEED_100 1
176 #define RTL8367_PORT_STATUS_SPEED_1000 2 176 #define RTL8367_PORT_STATUS_SPEED_1000 2
177   177  
178 #define RTL8367_RTL_NO_REG 0x13c0 178 #define RTL8367_RTL_NO_REG 0x13c0
179 #define RTL8367_RTL_NO_8367R 0x3670 179 #define RTL8367_RTL_NO_8367R 0x3670
180 #define RTL8367_RTL_NO_8367M 0x3671 180 #define RTL8367_RTL_NO_8367M 0x3671
181   181  
182 #define RTL8367_RTL_VER_REG 0x13c1 182 #define RTL8367_RTL_VER_REG 0x13c1
183 #define RTL8367_RTL_VER_MASK 0xf 183 #define RTL8367_RTL_VER_MASK 0xf
184   184  
185 #define RTL8367_RTL_MAGIC_ID_REG 0x13c2 185 #define RTL8367_RTL_MAGIC_ID_REG 0x13c2
186 #define RTL8367_RTL_MAGIC_ID_VAL 0x0249 186 #define RTL8367_RTL_MAGIC_ID_VAL 0x0249
187   187  
188 #define RTL8367_LED_SYS_CONFIG_REG 0x1b00 188 #define RTL8367_LED_SYS_CONFIG_REG 0x1b00
189 #define RTL8367_LED_MODE_REG 0x1b02 189 #define RTL8367_LED_MODE_REG 0x1b02
190 #define RTL8367_LED_MODE_RATE_M 0x7 190 #define RTL8367_LED_MODE_RATE_M 0x7
191 #define RTL8367_LED_MODE_RATE_S 1 191 #define RTL8367_LED_MODE_RATE_S 1
192   192  
193 #define RTL8367_LED_CONFIG_REG 0x1b03 193 #define RTL8367_LED_CONFIG_REG 0x1b03
194 #define RTL8367_LED_CONFIG_DATA_S 12 194 #define RTL8367_LED_CONFIG_DATA_S 12
195 #define RTL8367_LED_CONFIG_DATA_M 0x3 195 #define RTL8367_LED_CONFIG_DATA_M 0x3
196 #define RTL8367_LED_CONFIG_SEL BIT(14) 196 #define RTL8367_LED_CONFIG_SEL BIT(14)
197 #define RTL8367_LED_CONFIG_LED_CFG_M 0xf 197 #define RTL8367_LED_CONFIG_LED_CFG_M 0xf
198   198  
199 #define RTL8367_PARA_LED_IO_EN1_REG 0x1b24 199 #define RTL8367_PARA_LED_IO_EN1_REG 0x1b24
200 #define RTL8367_PARA_LED_IO_EN2_REG 0x1b25 200 #define RTL8367_PARA_LED_IO_EN2_REG 0x1b25
201 #define RTL8367_PARA_LED_IO_EN_PMASK 0xff 201 #define RTL8367_PARA_LED_IO_EN_PMASK 0xff
202   202  
203 #define RTL8367_IA_CTRL_REG 0x1f00 203 #define RTL8367_IA_CTRL_REG 0x1f00
204 #define RTL8367_IA_CTRL_RW(_x) ((_x) << 1) 204 #define RTL8367_IA_CTRL_RW(_x) ((_x) << 1)
205 #define RTL8367_IA_CTRL_RW_READ RTL8367_IA_CTRL_RW(0) 205 #define RTL8367_IA_CTRL_RW_READ RTL8367_IA_CTRL_RW(0)
206 #define RTL8367_IA_CTRL_RW_WRITE RTL8367_IA_CTRL_RW(1) 206 #define RTL8367_IA_CTRL_RW_WRITE RTL8367_IA_CTRL_RW(1)
207 #define RTL8367_IA_CTRL_CMD_MASK BIT(0) 207 #define RTL8367_IA_CTRL_CMD_MASK BIT(0)
208   208  
209 #define RTL8367_IA_STATUS_REG 0x1f01 209 #define RTL8367_IA_STATUS_REG 0x1f01
210 #define RTL8367_IA_STATUS_PHY_BUSY BIT(2) 210 #define RTL8367_IA_STATUS_PHY_BUSY BIT(2)
211 #define RTL8367_IA_STATUS_SDS_BUSY BIT(1) 211 #define RTL8367_IA_STATUS_SDS_BUSY BIT(1)
212 #define RTL8367_IA_STATUS_MDX_BUSY BIT(0) 212 #define RTL8367_IA_STATUS_MDX_BUSY BIT(0)
213   213  
214 #define RTL8367_IA_ADDRESS_REG 0x1f02 214 #define RTL8367_IA_ADDRESS_REG 0x1f02
215   215  
216 #define RTL8367_IA_WRITE_DATA_REG 0x1f03 216 #define RTL8367_IA_WRITE_DATA_REG 0x1f03
217 #define RTL8367_IA_READ_DATA_REG 0x1f04 217 #define RTL8367_IA_READ_DATA_REG 0x1f04
218   218  
219 #define RTL8367_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r)) 219 #define RTL8367_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
220   220  
221 #define RTL8367_CPU_PORT_NUM 9 221 #define RTL8367_CPU_PORT_NUM 9
222 #define RTL8367_NUM_PORTS 10 222 #define RTL8367_NUM_PORTS 10
223 #define RTL8367_NUM_VLANS 32 223 #define RTL8367_NUM_VLANS 32
224 #define RTL8367_NUM_LEDGROUPS 4 224 #define RTL8367_NUM_LEDGROUPS 4
225 #define RTL8367_NUM_VIDS 4096 225 #define RTL8367_NUM_VIDS 4096
226 #define RTL8367_PRIORITYMAX 7 226 #define RTL8367_PRIORITYMAX 7
227 #define RTL8367_FIDMAX 7 227 #define RTL8367_FIDMAX 7
228   228  
229 #define RTL8367_PORT_0 BIT(0) 229 #define RTL8367_PORT_0 BIT(0)
230 #define RTL8367_PORT_1 BIT(1) 230 #define RTL8367_PORT_1 BIT(1)
231 #define RTL8367_PORT_2 BIT(2) 231 #define RTL8367_PORT_2 BIT(2)
232 #define RTL8367_PORT_3 BIT(3) 232 #define RTL8367_PORT_3 BIT(3)
233 #define RTL8367_PORT_4 BIT(4) 233 #define RTL8367_PORT_4 BIT(4)
234 #define RTL8367_PORT_5 BIT(5) 234 #define RTL8367_PORT_5 BIT(5)
235 #define RTL8367_PORT_6 BIT(6) 235 #define RTL8367_PORT_6 BIT(6)
236 #define RTL8367_PORT_7 BIT(7) 236 #define RTL8367_PORT_7 BIT(7)
237 #define RTL8367_PORT_E1 BIT(8) /* external port 1 */ 237 #define RTL8367_PORT_E1 BIT(8) /* external port 1 */
238 #define RTL8367_PORT_E0 BIT(9) /* external port 0 */ 238 #define RTL8367_PORT_E0 BIT(9) /* external port 0 */
239   239  
240 #define RTL8367_PORTS_ALL \ 240 #define RTL8367_PORTS_ALL \
241 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \ 241 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
242 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \ 242 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
243 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1 | \ 243 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1 | \
244 RTL8367_PORT_E0) 244 RTL8367_PORT_E0)
245   245  
246 #define RTL8367_PORTS_ALL_BUT_CPU \ 246 #define RTL8367_PORTS_ALL_BUT_CPU \
247 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \ 247 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
248 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \ 248 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
249 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1) 249 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1)
250   250  
251 struct rtl8367_initval { 251 struct rtl8367_initval {
252 u16 reg; 252 u16 reg;
253 u16 val; 253 u16 val;
254 }; 254 };
255   255  
256 #define RTL8367_MIB_RXB_ID 0 /* IfInOctets */ 256 #define RTL8367_MIB_RXB_ID 0 /* IfInOctets */
257 #define RTL8367_MIB_TXB_ID 20 /* IfOutOctets */ 257 #define RTL8367_MIB_TXB_ID 20 /* IfOutOctets */
258   258  
259 static struct rtl8366_mib_counter rtl8367_mib_counters[] = { 259 static struct rtl8366_mib_counter rtl8367_mib_counters[] = {
260 { 0, 0, 4, "IfInOctets" }, 260 { 0, 0, 4, "IfInOctets" },
261 { 0, 4, 2, "Dot3StatsFCSErrors" }, 261 { 0, 4, 2, "Dot3StatsFCSErrors" },
262 { 0, 6, 2, "Dot3StatsSymbolErrors" }, 262 { 0, 6, 2, "Dot3StatsSymbolErrors" },
263 { 0, 8, 2, "Dot3InPauseFrames" }, 263 { 0, 8, 2, "Dot3InPauseFrames" },
264 { 0, 10, 2, "Dot3ControlInUnknownOpcodes" }, 264 { 0, 10, 2, "Dot3ControlInUnknownOpcodes" },
265 { 0, 12, 2, "EtherStatsFragments" }, 265 { 0, 12, 2, "EtherStatsFragments" },
266 { 0, 14, 2, "EtherStatsJabbers" }, 266 { 0, 14, 2, "EtherStatsJabbers" },
267 { 0, 16, 2, "IfInUcastPkts" }, 267 { 0, 16, 2, "IfInUcastPkts" },
268 { 0, 18, 2, "EtherStatsDropEvents" }, 268 { 0, 18, 2, "EtherStatsDropEvents" },
269 { 0, 20, 4, "EtherStatsOctets" }, 269 { 0, 20, 4, "EtherStatsOctets" },
270   270  
271 { 0, 24, 2, "EtherStatsUnderSizePkts" }, 271 { 0, 24, 2, "EtherStatsUnderSizePkts" },
272 { 0, 26, 2, "EtherOversizeStats" }, 272 { 0, 26, 2, "EtherOversizeStats" },
273 { 0, 28, 2, "EtherStatsPkts64Octets" }, 273 { 0, 28, 2, "EtherStatsPkts64Octets" },
274 { 0, 30, 2, "EtherStatsPkts65to127Octets" }, 274 { 0, 30, 2, "EtherStatsPkts65to127Octets" },
275 { 0, 32, 2, "EtherStatsPkts128to255Octets" }, 275 { 0, 32, 2, "EtherStatsPkts128to255Octets" },
276 { 0, 34, 2, "EtherStatsPkts256to511Octets" }, 276 { 0, 34, 2, "EtherStatsPkts256to511Octets" },
277 { 0, 36, 2, "EtherStatsPkts512to1023Octets" }, 277 { 0, 36, 2, "EtherStatsPkts512to1023Octets" },
278 { 0, 38, 2, "EtherStatsPkts1024to1518Octets" }, 278 { 0, 38, 2, "EtherStatsPkts1024to1518Octets" },
279 { 0, 40, 2, "EtherStatsMulticastPkts" }, 279 { 0, 40, 2, "EtherStatsMulticastPkts" },
280 { 0, 42, 2, "EtherStatsBroadcastPkts" }, 280 { 0, 42, 2, "EtherStatsBroadcastPkts" },
281   281  
282 { 0, 44, 4, "IfOutOctets" }, 282 { 0, 44, 4, "IfOutOctets" },
283   283  
284 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, 284 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
285 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, 285 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
286 { 0, 52, 2, "Dot3sDeferredTransmissions" }, 286 { 0, 52, 2, "Dot3sDeferredTransmissions" },
287 { 0, 54, 2, "Dot3StatsLateCollisions" }, 287 { 0, 54, 2, "Dot3StatsLateCollisions" },
288 { 0, 56, 2, "EtherStatsCollisions" }, 288 { 0, 56, 2, "EtherStatsCollisions" },
289 { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, 289 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
290 { 0, 60, 2, "Dot3OutPauseFrames" }, 290 { 0, 60, 2, "Dot3OutPauseFrames" },
291 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, 291 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
292 { 0, 64, 2, "Dot1dTpPortInDiscards" }, 292 { 0, 64, 2, "Dot1dTpPortInDiscards" },
293 { 0, 66, 2, "IfOutUcastPkts" }, 293 { 0, 66, 2, "IfOutUcastPkts" },
294 { 0, 68, 2, "IfOutMulticastPkts" }, 294 { 0, 68, 2, "IfOutMulticastPkts" },
295 { 0, 70, 2, "IfOutBroadcastPkts" }, 295 { 0, 70, 2, "IfOutBroadcastPkts" },
296 { 0, 72, 2, "OutOampduPkts" }, 296 { 0, 72, 2, "OutOampduPkts" },
297 { 0, 74, 2, "InOampduPkts" }, 297 { 0, 74, 2, "InOampduPkts" },
298 { 0, 76, 2, "PktgenPkts" }, 298 { 0, 76, 2, "PktgenPkts" },
299 }; 299 };
300   300  
301 #define REG_RD(_smi, _reg, _val) \ 301 #define REG_RD(_smi, _reg, _val) \
302 do { \ 302 do { \
303 err = rtl8366_smi_read_reg(_smi, _reg, _val); \ 303 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
304 if (err) \ 304 if (err) \
305 return err; \ 305 return err; \
306 } while (0) 306 } while (0)
307   307  
308 #define REG_WR(_smi, _reg, _val) \ 308 #define REG_WR(_smi, _reg, _val) \
309 do { \ 309 do { \
310 err = rtl8366_smi_write_reg(_smi, _reg, _val); \ 310 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
311 if (err) \ 311 if (err) \
312 return err; \ 312 return err; \
313 } while (0) 313 } while (0)
314   314  
315 #define REG_RMW(_smi, _reg, _mask, _val) \ 315 #define REG_RMW(_smi, _reg, _mask, _val) \
316 do { \ 316 do { \
317 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ 317 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
318 if (err) \ 318 if (err) \
319 return err; \ 319 return err; \
320 } while (0) 320 } while (0)
321   321  
322 static const struct rtl8367_initval rtl8367_initvals_0_0[] = { 322 static const struct rtl8367_initval rtl8367_initvals_0_0[] = {
323 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006}, 323 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
324 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048}, 324 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
325 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412}, 325 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
326 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0}, 326 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
327 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4}, 327 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
328 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7}, 328 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
329 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003}, 329 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
330 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2}, 330 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
331 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207}, 331 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
332 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620}, 332 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
333 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede}, 333 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
334 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1}, 334 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
335 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00}, 335 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
336 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002}, 336 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
337 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000}, 337 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
338 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f}, 338 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
339 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A}, 339 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
340 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005}, 340 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
341 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA}, 341 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
342 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055}, 342 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
343 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354}, 343 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
344 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB}, 344 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
345 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1006}, {0x121e, 0x03e8}, 345 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1006}, {0x121e, 0x03e8},
346 {0x121f, 0x02b3}, {0x1220, 0x028f}, {0x1221, 0x029b}, {0x1222, 0x0277}, 346 {0x121f, 0x02b3}, {0x1220, 0x028f}, {0x1221, 0x029b}, {0x1222, 0x0277},
347 {0x1223, 0x02b3}, {0x1224, 0x028f}, {0x1225, 0x029b}, {0x1226, 0x0277}, 347 {0x1223, 0x02b3}, {0x1224, 0x028f}, {0x1225, 0x029b}, {0x1226, 0x0277},
348 {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, {0x1230, 0x00b4}, 348 {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, {0x1230, 0x00b4},
349 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024}, 349 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
350 {0x0219, 0x0032}, {0x0200, 0x03e8}, {0x0201, 0x03e8}, {0x0202, 0x03e8}, 350 {0x0219, 0x0032}, {0x0200, 0x03e8}, {0x0201, 0x03e8}, {0x0202, 0x03e8},
351 {0x0203, 0x03e8}, {0x0204, 0x03e8}, {0x0205, 0x03e8}, {0x0206, 0x03e8}, 351 {0x0203, 0x03e8}, {0x0204, 0x03e8}, {0x0205, 0x03e8}, {0x0206, 0x03e8},
352 {0x0207, 0x03e8}, {0x0218, 0x0032}, {0x0208, 0x029b}, {0x0209, 0x029b}, 352 {0x0207, 0x03e8}, {0x0218, 0x0032}, {0x0208, 0x029b}, {0x0209, 0x029b},
353 {0x020a, 0x029b}, {0x020b, 0x029b}, {0x020c, 0x029b}, {0x020d, 0x029b}, 353 {0x020a, 0x029b}, {0x020b, 0x029b}, {0x020c, 0x029b}, {0x020d, 0x029b},
354 {0x020e, 0x029b}, {0x020f, 0x029b}, {0x0210, 0x029b}, {0x0211, 0x029b}, 354 {0x020e, 0x029b}, {0x020f, 0x029b}, {0x0210, 0x029b}, {0x0211, 0x029b},
355 {0x0212, 0x029b}, {0x0213, 0x029b}, {0x0214, 0x029b}, {0x0215, 0x029b}, 355 {0x0212, 0x029b}, {0x0213, 0x029b}, {0x0214, 0x029b}, {0x0215, 0x029b},
356 {0x0216, 0x029b}, {0x0217, 0x029b}, {0x0900, 0x0000}, {0x0901, 0x0000}, 356 {0x0216, 0x029b}, {0x0217, 0x029b}, {0x0900, 0x0000}, {0x0901, 0x0000},
357 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, 357 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
358 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, 358 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
359 {0x0802, 0x0100}, {0x1700, 0x014C}, {0x0301, 0x00FF}, {0x12AA, 0x0096}, 359 {0x0802, 0x0100}, {0x1700, 0x014C}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
360 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4}, 360 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
361 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340}, 361 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
362 {0x133f, 0x0010}, {0x20A0, 0x1940}, {0x20C0, 0x1940}, {0x20E0, 0x1940}, 362 {0x133f, 0x0010}, {0x20A0, 0x1940}, {0x20C0, 0x1940}, {0x20E0, 0x1940},
363 }; 363 };
364   364  
365 static const struct rtl8367_initval rtl8367_initvals_0_1[] = { 365 static const struct rtl8367_initval rtl8367_initvals_0_1[] = {
366 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006}, 366 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
367 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048}, 367 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
368 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412}, 368 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
369 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0}, 369 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
370 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4}, 370 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
371 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7}, 371 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
372 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003}, 372 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
373 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2}, 373 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
374 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207}, 374 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
375 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620}, 375 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
376 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede}, 376 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
377 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1}, 377 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
378 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00}, 378 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
379 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002}, 379 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
380 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000}, 380 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
381 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f}, 381 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
382 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A}, 382 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
383 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005}, 383 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
384 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA}, 384 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
385 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055}, 385 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
386 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354}, 386 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
387 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB}, 387 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
388 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1b06}, {0x121e, 0x07f0}, 388 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1b06}, {0x121e, 0x07f0},
389 {0x121f, 0x0438}, {0x1220, 0x040f}, {0x1221, 0x040f}, {0x1222, 0x03eb}, 389 {0x121f, 0x0438}, {0x1220, 0x040f}, {0x1221, 0x040f}, {0x1222, 0x03eb},
390 {0x1223, 0x0438}, {0x1224, 0x040f}, {0x1225, 0x040f}, {0x1226, 0x03eb}, 390 {0x1223, 0x0438}, {0x1224, 0x040f}, {0x1225, 0x040f}, {0x1226, 0x03eb},
391 {0x1227, 0x0144}, {0x1228, 0x0138}, {0x122f, 0x0144}, {0x1230, 0x0138}, 391 {0x1227, 0x0144}, {0x1228, 0x0138}, {0x122f, 0x0144}, {0x1230, 0x0138},
392 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024}, 392 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
393 {0x0219, 0x0032}, {0x0200, 0x07d0}, {0x0201, 0x07d0}, {0x0202, 0x07d0}, 393 {0x0219, 0x0032}, {0x0200, 0x07d0}, {0x0201, 0x07d0}, {0x0202, 0x07d0},
394 {0x0203, 0x07d0}, {0x0204, 0x07d0}, {0x0205, 0x07d0}, {0x0206, 0x07d0}, 394 {0x0203, 0x07d0}, {0x0204, 0x07d0}, {0x0205, 0x07d0}, {0x0206, 0x07d0},
395 {0x0207, 0x07d0}, {0x0218, 0x0032}, {0x0208, 0x0190}, {0x0209, 0x0190}, 395 {0x0207, 0x07d0}, {0x0218, 0x0032}, {0x0208, 0x0190}, {0x0209, 0x0190},
396 {0x020a, 0x0190}, {0x020b, 0x0190}, {0x020c, 0x0190}, {0x020d, 0x0190}, 396 {0x020a, 0x0190}, {0x020b, 0x0190}, {0x020c, 0x0190}, {0x020d, 0x0190},
397 {0x020e, 0x0190}, {0x020f, 0x0190}, {0x0210, 0x0190}, {0x0211, 0x0190}, 397 {0x020e, 0x0190}, {0x020f, 0x0190}, {0x0210, 0x0190}, {0x0211, 0x0190},
398 {0x0212, 0x0190}, {0x0213, 0x0190}, {0x0214, 0x0190}, {0x0215, 0x0190}, 398 {0x0212, 0x0190}, {0x0213, 0x0190}, {0x0214, 0x0190}, {0x0215, 0x0190},
399 {0x0216, 0x0190}, {0x0217, 0x0190}, {0x0900, 0x0000}, {0x0901, 0x0000}, 399 {0x0216, 0x0190}, {0x0217, 0x0190}, {0x0900, 0x0000}, {0x0901, 0x0000},
400 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, 400 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
401 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, 401 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
402 {0x0802, 0x0100}, {0x1700, 0x0125}, {0x0301, 0x00FF}, {0x12AA, 0x0096}, 402 {0x0802, 0x0100}, {0x1700, 0x0125}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
403 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4}, 403 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
404 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340}, 404 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
405 {0x133f, 0x0010}, 405 {0x133f, 0x0010},
406 }; 406 };
407   407  
408 static const struct rtl8367_initval rtl8367_initvals_1_0[] = { 408 static const struct rtl8367_initval rtl8367_initvals_1_0[] = {
409 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000}, 409 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
410 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030}, 410 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
411 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82}, 411 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
412 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938}, 412 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
413 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001}, 413 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
414 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007}, 414 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
415 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C}, 415 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
416 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, 416 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
417 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0}, 417 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
418 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7}, 418 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
419 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA}, 419 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
420 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A}, 420 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
421 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D}, 421 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
422 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806}, 422 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
423 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5}, 423 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
424 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB}, 424 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
425 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0}, 425 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
426 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89}, 426 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
427 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF}, 427 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
428 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640}, 428 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
429 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729}, 429 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
430 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00}, 430 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
431 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B}, 431 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
432 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32}, 432 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
433 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52}, 433 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
434 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C}, 434 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
435 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D}, 435 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
436 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053}, 436 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
437 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B}, 437 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
438 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771}, 438 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
439 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7}, 439 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
440 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A}, 440 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
441 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600}, 441 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
442 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000}, 442 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
443 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65}, 443 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
444 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007}, 444 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
445 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010}, 445 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
446 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000}, 446 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
447 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115}, 447 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
448 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C}, 448 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
449 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4}, 449 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
450 {0x121D, 0x7D16}, {0x121E, 0x03E8}, {0x121F, 0x024E}, {0x1220, 0x0230}, 450 {0x121D, 0x7D16}, {0x121E, 0x03E8}, {0x121F, 0x024E}, {0x1220, 0x0230},
451 {0x1221, 0x0244}, {0x1222, 0x0226}, {0x1223, 0x024E}, {0x1224, 0x0230}, 451 {0x1221, 0x0244}, {0x1222, 0x0226}, {0x1223, 0x024E}, {0x1224, 0x0230},
452 {0x1225, 0x0244}, {0x1226, 0x0226}, {0x1227, 0x00C0}, {0x1228, 0x00B4}, 452 {0x1225, 0x0244}, {0x1226, 0x0226}, {0x1227, 0x00C0}, {0x1228, 0x00B4},
453 {0x122F, 0x00C0}, {0x1230, 0x00B4}, {0x0208, 0x03E8}, {0x0209, 0x03E8}, 453 {0x122F, 0x00C0}, {0x1230, 0x00B4}, {0x0208, 0x03E8}, {0x0209, 0x03E8},
454 {0x020A, 0x03E8}, {0x020B, 0x03E8}, {0x020C, 0x03E8}, {0x020D, 0x03E8}, 454 {0x020A, 0x03E8}, {0x020B, 0x03E8}, {0x020C, 0x03E8}, {0x020D, 0x03E8},
455 {0x020E, 0x03E8}, {0x020F, 0x03E8}, {0x0210, 0x03E8}, {0x0211, 0x03E8}, 455 {0x020E, 0x03E8}, {0x020F, 0x03E8}, {0x0210, 0x03E8}, {0x0211, 0x03E8},
456 {0x0212, 0x03E8}, {0x0213, 0x03E8}, {0x0214, 0x03E8}, {0x0215, 0x03E8}, 456 {0x0212, 0x03E8}, {0x0213, 0x03E8}, {0x0214, 0x03E8}, {0x0215, 0x03E8},
457 {0x0216, 0x03E8}, {0x0217, 0x03E8}, {0x0900, 0x0000}, {0x0901, 0x0000}, 457 {0x0216, 0x03E8}, {0x0217, 0x03E8}, {0x0900, 0x0000}, {0x0901, 0x0000},
458 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087B, 0x0000}, 458 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087B, 0x0000},
459 {0x087C, 0xFF00}, {0x087D, 0x0000}, {0x087E, 0x0000}, {0x0801, 0x0100}, 459 {0x087C, 0xFF00}, {0x087D, 0x0000}, {0x087E, 0x0000}, {0x0801, 0x0100},
460 {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, 460 {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040},
461 {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, 461 {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
462 {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, {0x2200, 0x1340}, 462 {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, {0x2200, 0x1340},
463 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x20A0, 0x1940}, 463 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x20A0, 0x1940},
464 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050}, 464 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
465 }; 465 };
466   466  
467 static const struct rtl8367_initval rtl8367_initvals_1_1[] = { 467 static const struct rtl8367_initval rtl8367_initvals_1_1[] = {
468 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000}, 468 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
469 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030}, 469 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
470 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82}, 470 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
471 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938}, 471 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
472 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001}, 472 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
473 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007}, 473 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
474 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C}, 474 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
475 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, 475 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
476 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0}, 476 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
477 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7}, 477 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
478 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA}, 478 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
479 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A}, 479 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
480 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D}, 480 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
481 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806}, 481 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
482 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5}, 482 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
483 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB}, 483 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
484 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0}, 484 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
485 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89}, 485 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
486 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF}, 486 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
487 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640}, 487 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
488 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729}, 488 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
489 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00}, 489 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
490 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B}, 490 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
491 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32}, 491 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
492 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52}, 492 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
493 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C}, 493 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
494 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D}, 494 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
495 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053}, 495 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
496 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B}, 496 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
497 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771}, 497 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
498 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7}, 498 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
499 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A}, 499 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
500 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600}, 500 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
501 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000}, 501 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
502 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65}, 502 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
503 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007}, 503 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
504 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010}, 504 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
505 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000}, 505 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
506 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115}, 506 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
507 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C}, 507 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
508 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4}, 508 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
509 {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, 509 {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000},
510 {0x0865, 0x3210}, {0x087B, 0x0000}, {0x087C, 0xFF00}, {0x087D, 0x0000}, 510 {0x0865, 0x3210}, {0x087B, 0x0000}, {0x087C, 0xFF00}, {0x087D, 0x0000},
511 {0x087E, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, 511 {0x087E, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040},
512 {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, 512 {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040},
513 {0x0A25, 0x2040}, {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, 513 {0x0A25, 0x2040}, {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040},
514 {0x0A29, 0x2040}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, 514 {0x0A29, 0x2040}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000},
515 {0x2200, 0x1340}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, 515 {0x2200, 0x1340}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE},
516 {0x1B03, 0x0876}, 516 {0x1B03, 0x0876},
517 }; 517 };
518   518  
519 static const struct rtl8367_initval rtl8367_initvals_2_0[] = { 519 static const struct rtl8367_initval rtl8367_initvals_2_0[] = {
520 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000}, 520 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
521 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048}, 521 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
522 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8}, 522 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
523 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207}, 523 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
524 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000}, 524 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
525 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005}, 525 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
526 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000}, 526 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
527 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7}, 527 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
528 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e}, 528 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
529 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201}, 529 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
530 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e}, 530 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
531 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000}, 531 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
532 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00}, 532 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
533 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6}, 533 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
534 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140}, 534 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
535 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4}, 535 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
536 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa}, 536 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
537 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a}, 537 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
538 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978}, 538 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
539 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806}, 539 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
540 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5}, 540 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
541 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425}, 541 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
542 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e}, 542 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
543 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68}, 543 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
544 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d}, 544 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
545 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365}, 545 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
546 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d}, 546 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
547 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036}, 547 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
548 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce}, 548 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
549 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530}, 549 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
550 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a}, 550 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
551 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100}, 551 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
552 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306}, 552 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
553 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77}, 553 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
554 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f}, 554 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
555 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405}, 555 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
556 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010}, 556 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
557 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x7D16}, 557 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x7D16},
558 {0x121e, 0x03e8}, {0x121f, 0x024e}, {0x1220, 0x0230}, {0x1221, 0x0244}, 558 {0x121e, 0x03e8}, {0x121f, 0x024e}, {0x1220, 0x0230}, {0x1221, 0x0244},
559 {0x1222, 0x0226}, {0x1223, 0x024e}, {0x1224, 0x0230}, {0x1225, 0x0244}, 559 {0x1222, 0x0226}, {0x1223, 0x024e}, {0x1224, 0x0230}, {0x1225, 0x0244},
560 {0x1226, 0x0226}, {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, 560 {0x1226, 0x0226}, {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0},
561 {0x1230, 0x00b4}, {0x0208, 0x03e8}, {0x0209, 0x03e8}, {0x020a, 0x03e8}, 561 {0x1230, 0x00b4}, {0x0208, 0x03e8}, {0x0209, 0x03e8}, {0x020a, 0x03e8},
562 {0x020b, 0x03e8}, {0x020c, 0x03e8}, {0x020d, 0x03e8}, {0x020e, 0x03e8}, 562 {0x020b, 0x03e8}, {0x020c, 0x03e8}, {0x020d, 0x03e8}, {0x020e, 0x03e8},
563 {0x020f, 0x03e8}, {0x0210, 0x03e8}, {0x0211, 0x03e8}, {0x0212, 0x03e8}, 563 {0x020f, 0x03e8}, {0x0210, 0x03e8}, {0x0211, 0x03e8}, {0x0212, 0x03e8},
564 {0x0213, 0x03e8}, {0x0214, 0x03e8}, {0x0215, 0x03e8}, {0x0216, 0x03e8}, 564 {0x0213, 0x03e8}, {0x0214, 0x03e8}, {0x0215, 0x03e8}, {0x0216, 0x03e8},
565 {0x0217, 0x03e8}, {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, 565 {0x0217, 0x03e8}, {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000},
566 {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, {0x087c, 0xff00}, 566 {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, {0x087c, 0xff00},
567 {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, 567 {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100},
568 {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, 568 {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040},
569 {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, {0x20A0, 0x1940}, 569 {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, {0x20A0, 0x1940},
570 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050}, 570 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
571 }; 571 };
572   572  
573 static const struct rtl8367_initval rtl8367_initvals_2_1[] = { 573 static const struct rtl8367_initval rtl8367_initvals_2_1[] = {
574 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000}, 574 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
575 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048}, 575 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
576 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8}, 576 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
577 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207}, 577 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
578 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000}, 578 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
579 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005}, 579 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
580 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000}, 580 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
581 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7}, 581 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
582 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e}, 582 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
583 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201}, 583 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
584 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e}, 584 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
585 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000}, 585 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
586 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00}, 586 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
587 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6}, 587 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
588 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140}, 588 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
589 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4}, 589 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
590 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa}, 590 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
591 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a}, 591 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
592 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978}, 592 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
593 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806}, 593 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
594 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5}, 594 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
595 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425}, 595 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
596 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e}, 596 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
597 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68}, 597 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
598 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d}, 598 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
599 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365}, 599 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
600 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d}, 600 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
601 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036}, 601 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
602 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce}, 602 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
603 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530}, 603 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
604 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a}, 604 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
605 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100}, 605 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
606 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306}, 606 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
607 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77}, 607 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
608 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f}, 608 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
609 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405}, 609 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
610 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010}, 610 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
611 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x0900, 0x0000}, 611 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x0900, 0x0000},
612 {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, 612 {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210},
613 {0x087b, 0x0000}, {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, 613 {0x087b, 0x0000}, {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000},
614 {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, 614 {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040},
615 {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A25, 0x2040}, 615 {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A25, 0x2040},
616 {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, 616 {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
617 {0x130c, 0x0050}, 617 {0x130c, 0x0050},
618 }; 618 };
619   619  
620 static int rtl8367_write_initvals(struct rtl8366_smi *smi, 620 static int rtl8367_write_initvals(struct rtl8366_smi *smi,
621 const struct rtl8367_initval *initvals, 621 const struct rtl8367_initval *initvals,
622 int count) 622 int count)
623 { 623 {
624 int err; 624 int err;
625 int i; 625 int i;
626   626  
627 for (i = 0; i < count; i++) 627 for (i = 0; i < count; i++)
628 REG_WR(smi, initvals[i].reg, initvals[i].val); 628 REG_WR(smi, initvals[i].reg, initvals[i].val);
629   629  
630 return 0; 630 return 0;
631 } 631 }
632   632  
633 static int rtl8367_read_phy_reg(struct rtl8366_smi *smi, 633 static int rtl8367_read_phy_reg(struct rtl8366_smi *smi,
634 u32 phy_addr, u32 phy_reg, u32 *val) 634 u32 phy_addr, u32 phy_reg, u32 *val)
635 { 635 {
636 int timeout; 636 int timeout;
637 u32 data; 637 u32 data;
638 int err; 638 int err;
639   639  
640 if (phy_addr > RTL8367_PHY_ADDR_MAX) 640 if (phy_addr > RTL8367_PHY_ADDR_MAX)
641 return -EINVAL; 641 return -EINVAL;
642   642  
643 if (phy_reg > RTL8367_PHY_REG_MAX) 643 if (phy_reg > RTL8367_PHY_REG_MAX)
644 return -EINVAL; 644 return -EINVAL;
645   645  
646 REG_RD(smi, RTL8367_IA_STATUS_REG, &data); 646 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
647 if (data & RTL8367_IA_STATUS_PHY_BUSY) 647 if (data & RTL8367_IA_STATUS_PHY_BUSY)
648 return -ETIMEDOUT; 648 return -ETIMEDOUT;
649   649  
650 /* prepare address */ 650 /* prepare address */
651 REG_WR(smi, RTL8367_IA_ADDRESS_REG, 651 REG_WR(smi, RTL8367_IA_ADDRESS_REG,
652 RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg)); 652 RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg));
653   653  
654 /* send read command */ 654 /* send read command */
655 REG_WR(smi, RTL8367_IA_CTRL_REG, 655 REG_WR(smi, RTL8367_IA_CTRL_REG,
656 RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_READ); 656 RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_READ);
657   657  
658 timeout = 5; 658 timeout = 5;
659 do { 659 do {
660 REG_RD(smi, RTL8367_IA_STATUS_REG, &data); 660 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
661 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0) 661 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)
662 break; 662 break;
663   663  
664 if (timeout--) { 664 if (timeout--) {
665 dev_err(smi->parent, "phy read timed out\n"); 665 dev_err(smi->parent, "phy read timed out\n");
666 return -ETIMEDOUT; 666 return -ETIMEDOUT;
667 } 667 }
668   668  
669 udelay(1); 669 udelay(1);
670 } while (1); 670 } while (1);
671   671  
672 /* read data */ 672 /* read data */
673 REG_RD(smi, RTL8367_IA_READ_DATA_REG, val); 673 REG_RD(smi, RTL8367_IA_READ_DATA_REG, val);
674   674  
675 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n", 675 dev_dbg(smi->parent, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
676 phy_addr, phy_reg, *val); 676 phy_addr, phy_reg, *val);
677 return 0; 677 return 0;
678 } 678 }
679   679  
680 static int rtl8367_write_phy_reg(struct rtl8366_smi *smi, 680 static int rtl8367_write_phy_reg(struct rtl8366_smi *smi,
681 u32 phy_addr, u32 phy_reg, u32 val) 681 u32 phy_addr, u32 phy_reg, u32 val)
682 { 682 {
683 int timeout; 683 int timeout;
684 u32 data; 684 u32 data;
685 int err; 685 int err;
686   686  
687 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n", 687 dev_dbg(smi->parent, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
688 phy_addr, phy_reg, val); 688 phy_addr, phy_reg, val);
689   689  
690 if (phy_addr > RTL8367_PHY_ADDR_MAX) 690 if (phy_addr > RTL8367_PHY_ADDR_MAX)
691 return -EINVAL; 691 return -EINVAL;
692   692  
693 if (phy_reg > RTL8367_PHY_REG_MAX) 693 if (phy_reg > RTL8367_PHY_REG_MAX)
694 return -EINVAL; 694 return -EINVAL;
695   695  
696 REG_RD(smi, RTL8367_IA_STATUS_REG, &data); 696 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
697 if (data & RTL8367_IA_STATUS_PHY_BUSY) 697 if (data & RTL8367_IA_STATUS_PHY_BUSY)
698 return -ETIMEDOUT; 698 return -ETIMEDOUT;
699   699  
700 /* preapre data */ 700 /* preapre data */
701 REG_WR(smi, RTL8367_IA_WRITE_DATA_REG, val); 701 REG_WR(smi, RTL8367_IA_WRITE_DATA_REG, val);
702   702  
703 /* prepare address */ 703 /* prepare address */
704 REG_WR(smi, RTL8367_IA_ADDRESS_REG, 704 REG_WR(smi, RTL8367_IA_ADDRESS_REG,
705 RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg)); 705 RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg));
706   706  
707 /* send write command */ 707 /* send write command */
708 REG_WR(smi, RTL8367_IA_CTRL_REG, 708 REG_WR(smi, RTL8367_IA_CTRL_REG,
709 RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_WRITE); 709 RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_WRITE);
710   710  
711 timeout = 5; 711 timeout = 5;
712 do { 712 do {
713 REG_RD(smi, RTL8367_IA_STATUS_REG, &data); 713 REG_RD(smi, RTL8367_IA_STATUS_REG, &data);
714 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0) 714 if ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)
715 break; 715 break;
716   716  
717 if (timeout--) { 717 if (timeout--) {
718 dev_err(smi->parent, "phy write timed out\n"); 718 dev_err(smi->parent, "phy write timed out\n");
719 return -ETIMEDOUT; 719 return -ETIMEDOUT;
720 } 720 }
721   721  
722 udelay(1); 722 udelay(1);
723 } while (1); 723 } while (1);
724   724  
725 return 0; 725 return 0;
726 } 726 }
727   727  
728 static int rtl8367_init_regs0(struct rtl8366_smi *smi, unsigned mode) 728 static int rtl8367_init_regs0(struct rtl8366_smi *smi, unsigned mode)
729 { 729 {
730 const struct rtl8367_initval *initvals; 730 const struct rtl8367_initval *initvals;
731 int count; 731 int count;
732 int err; 732 int err;
733   733  
734 switch (mode) { 734 switch (mode) {
735 case 0: 735 case 0:
736 initvals = rtl8367_initvals_0_0; 736 initvals = rtl8367_initvals_0_0;
737 count = ARRAY_SIZE(rtl8367_initvals_0_0); 737 count = ARRAY_SIZE(rtl8367_initvals_0_0);
738 break; 738 break;
739   739  
740 case 1: 740 case 1:
741 case 2: 741 case 2:
742 initvals = rtl8367_initvals_0_1; 742 initvals = rtl8367_initvals_0_1;
743 count = ARRAY_SIZE(rtl8367_initvals_0_1); 743 count = ARRAY_SIZE(rtl8367_initvals_0_1);
744 break; 744 break;
745   745  
746 default: 746 default:
747 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode); 747 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode);
748 return -ENODEV; 748 return -ENODEV;
749 } 749 }
750   750  
751 err = rtl8367_write_initvals(smi, initvals, count); 751 err = rtl8367_write_initvals(smi, initvals, count);
752 if (err) 752 if (err)
753 return err; 753 return err;
754   754  
755 /* TODO: complete this */ 755 /* TODO: complete this */
756   756  
757 return 0; 757 return 0;
758 } 758 }
759   759  
760 static int rtl8367_init_regs1(struct rtl8366_smi *smi, unsigned mode) 760 static int rtl8367_init_regs1(struct rtl8366_smi *smi, unsigned mode)
761 { 761 {
762 const struct rtl8367_initval *initvals; 762 const struct rtl8367_initval *initvals;
763 int count; 763 int count;
764   764  
765 switch (mode) { 765 switch (mode) {
766 case 0: 766 case 0:
767 initvals = rtl8367_initvals_1_0; 767 initvals = rtl8367_initvals_1_0;
768 count = ARRAY_SIZE(rtl8367_initvals_1_0); 768 count = ARRAY_SIZE(rtl8367_initvals_1_0);
769 break; 769 break;
770   770  
771 case 1: 771 case 1:
772 case 2: 772 case 2:
773 initvals = rtl8367_initvals_1_1; 773 initvals = rtl8367_initvals_1_1;
774 count = ARRAY_SIZE(rtl8367_initvals_1_1); 774 count = ARRAY_SIZE(rtl8367_initvals_1_1);
775 break; 775 break;
776   776  
777 default: 777 default:
778 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode); 778 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode);
779 return -ENODEV; 779 return -ENODEV;
780 } 780 }
781   781  
782 return rtl8367_write_initvals(smi, initvals, count); 782 return rtl8367_write_initvals(smi, initvals, count);
783 } 783 }
784   784  
785 static int rtl8367_init_regs2(struct rtl8366_smi *smi, unsigned mode) 785 static int rtl8367_init_regs2(struct rtl8366_smi *smi, unsigned mode)
786 { 786 {
787 const struct rtl8367_initval *initvals; 787 const struct rtl8367_initval *initvals;
788 int count; 788 int count;
789   789  
790 switch (mode) { 790 switch (mode) {
791 case 0: 791 case 0:
792 initvals = rtl8367_initvals_2_0; 792 initvals = rtl8367_initvals_2_0;
793 count = ARRAY_SIZE(rtl8367_initvals_2_0); 793 count = ARRAY_SIZE(rtl8367_initvals_2_0);
794 break; 794 break;
795   795  
796 case 1: 796 case 1:
797 case 2: 797 case 2:
798 initvals = rtl8367_initvals_2_1; 798 initvals = rtl8367_initvals_2_1;
799 count = ARRAY_SIZE(rtl8367_initvals_2_1); 799 count = ARRAY_SIZE(rtl8367_initvals_2_1);
800 break; 800 break;
801   801  
802 default: 802 default:
803 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode); 803 dev_err(smi->parent, "%s: unknow mode %u\n", __func__, mode);
804 return -ENODEV; 804 return -ENODEV;
805 } 805 }
806   806  
807 return rtl8367_write_initvals(smi, initvals, count); 807 return rtl8367_write_initvals(smi, initvals, count);
808 } 808 }
809   809  
810 static int rtl8367_init_regs(struct rtl8366_smi *smi) 810 static int rtl8367_init_regs(struct rtl8366_smi *smi)
811 { 811 {
812 u32 data; 812 u32 data;
813 u32 rlvid; 813 u32 rlvid;
814 u32 mode; 814 u32 mode;
815 int err; 815 int err;
816   816  
817 REG_WR(smi, RTL8367_RTL_MAGIC_ID_REG, RTL8367_RTL_MAGIC_ID_VAL); 817 REG_WR(smi, RTL8367_RTL_MAGIC_ID_REG, RTL8367_RTL_MAGIC_ID_VAL);
818   818  
819 REG_RD(smi, RTL8367_CHIP_VER_REG, &data); 819 REG_RD(smi, RTL8367_CHIP_VER_REG, &data);
820 rlvid = (data >> RTL8367_CHIP_VER_RLVID_SHIFT) & 820 rlvid = (data >> RTL8367_CHIP_VER_RLVID_SHIFT) &
821 RTL8367_CHIP_VER_RLVID_MASK; 821 RTL8367_CHIP_VER_RLVID_MASK;
822   822  
823 REG_RD(smi, RTL8367_CHIP_MODE_REG, &data); 823 REG_RD(smi, RTL8367_CHIP_MODE_REG, &data);
824 mode = data & RTL8367_CHIP_MODE_MASK; 824 mode = data & RTL8367_CHIP_MODE_MASK;
825   825  
826 switch (rlvid) { 826 switch (rlvid) {
827 case 0: 827 case 0:
828 err = rtl8367_init_regs0(smi, mode); 828 err = rtl8367_init_regs0(smi, mode);
829 break; 829 break;
830   830  
831 case 1: 831 case 1:
832 err = rtl8367_write_phy_reg(smi, 0, 31, 5); 832 err = rtl8367_write_phy_reg(smi, 0, 31, 5);
833 if (err) 833 if (err)
834 break; 834 break;
835   835  
836 err = rtl8367_write_phy_reg(smi, 0, 5, 0x3ffe); 836 err = rtl8367_write_phy_reg(smi, 0, 5, 0x3ffe);
837 if (err) 837 if (err)
838 break; 838 break;
839   839  
840 err = rtl8367_read_phy_reg(smi, 0, 6, &data); 840 err = rtl8367_read_phy_reg(smi, 0, 6, &data);
841 if (err) 841 if (err)
842 break; 842 break;
843   843  
844 if (data == 0x94eb) { 844 if (data == 0x94eb) {
845 err = rtl8367_init_regs1(smi, mode); 845 err = rtl8367_init_regs1(smi, mode);
846 } else if (data == 0x2104) { 846 } else if (data == 0x2104) {
847 err = rtl8367_init_regs2(smi, mode); 847 err = rtl8367_init_regs2(smi, mode);
848 } else { 848 } else {
849 dev_err(smi->parent, "unknow phy data %04x\n", data); 849 dev_err(smi->parent, "unknow phy data %04x\n", data);
850 return -ENODEV; 850 return -ENODEV;
851 } 851 }
852   852  
853 break; 853 break;
854   854  
855 default: 855 default:
856 dev_err(smi->parent, "unknow rlvid %u\n", rlvid); 856 dev_err(smi->parent, "unknow rlvid %u\n", rlvid);
857 err = -ENODEV; 857 err = -ENODEV;
858 break; 858 break;
859 } 859 }
860   860  
861 return err; 861 return err;
862 } 862 }
863   863  
864 static int rtl8367_reset_chip(struct rtl8366_smi *smi) 864 static int rtl8367_reset_chip(struct rtl8366_smi *smi)
865 { 865 {
866 int timeout = 10; 866 int timeout = 10;
867 int err; 867 int err;
868 u32 data; 868 u32 data;
869   869  
870 REG_WR(smi, RTL8367_CHIP_RESET_REG, RTL8367_CHIP_RESET_HW); 870 REG_WR(smi, RTL8367_CHIP_RESET_REG, RTL8367_CHIP_RESET_HW);
871 msleep(RTL8367_RESET_DELAY); 871 msleep(RTL8367_RESET_DELAY);
872   872  
873 do { 873 do {
874 REG_RD(smi, RTL8367_CHIP_RESET_REG, &data); 874 REG_RD(smi, RTL8367_CHIP_RESET_REG, &data);
875 if (!(data & RTL8367_CHIP_RESET_HW)) 875 if (!(data & RTL8367_CHIP_RESET_HW))
876 break; 876 break;
877   877  
878 msleep(1); 878 msleep(1);
879 } while (--timeout); 879 } while (--timeout);
880   880  
881 if (!timeout) { 881 if (!timeout) {
882 dev_err(smi->parent, "chip reset timed out\n"); 882 dev_err(smi->parent, "chip reset timed out\n");
883 return -ETIMEDOUT; 883 return -ETIMEDOUT;
884 } 884 }
885   885  
886 return 0; 886 return 0;
887 } 887 }
888   888  
889 static int rtl8367_extif_set_mode(struct rtl8366_smi *smi, int id, 889 static int rtl8367_extif_set_mode(struct rtl8366_smi *smi, int id,
890 enum rtl8367_extif_mode mode) 890 enum rtl8367_extif_mode mode)
891 { 891 {
892 int err; 892 int err;
893   893  
894 /* set port mode */ 894 /* set port mode */
895 switch (mode) { 895 switch (mode) {
896 case RTL8367_EXTIF_MODE_RGMII: 896 case RTL8367_EXTIF_MODE_RGMII:
897 case RTL8367_EXTIF_MODE_RGMII_33V: 897 case RTL8367_EXTIF_MODE_RGMII_33V:
898 REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367); 898 REG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367);
899 REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777); 899 REG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777);
900 break; 900 break;
901   901  
902 case RTL8367_EXTIF_MODE_TMII_MAC: 902 case RTL8367_EXTIF_MODE_TMII_MAC:
903 case RTL8367_EXTIF_MODE_TMII_PHY: 903 case RTL8367_EXTIF_MODE_TMII_PHY:
904 REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG, 904 REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG,
905 BIT((id + 1) % 2), BIT((id + 1) % 2)); 905 BIT((id + 1) % 2), BIT((id + 1) % 2));
906 break; 906 break;
907   907  
908 case RTL8367_EXTIF_MODE_GMII: 908 case RTL8367_EXTIF_MODE_GMII:
909 REG_RMW(smi, RTL8367_CHIP_DEBUG0_REG, 909 REG_RMW(smi, RTL8367_CHIP_DEBUG0_REG,
910 RTL8367_CHIP_DEBUG0_DUMMY0(id), 910 RTL8367_CHIP_DEBUG0_DUMMY0(id),
911 RTL8367_CHIP_DEBUG0_DUMMY0(id)); 911 RTL8367_CHIP_DEBUG0_DUMMY0(id));
912 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), BIT(6)); 912 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), BIT(6));
913 break; 913 break;
914   914  
915 case RTL8367_EXTIF_MODE_MII_MAC: 915 case RTL8367_EXTIF_MODE_MII_MAC:
916 case RTL8367_EXTIF_MODE_MII_PHY: 916 case RTL8367_EXTIF_MODE_MII_PHY:
917 case RTL8367_EXTIF_MODE_DISABLED: 917 case RTL8367_EXTIF_MODE_DISABLED:
918 REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG, 918 REG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG,
919 BIT((id + 1) % 2), 0); 919 BIT((id + 1) % 2), 0);
920 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), 0); 920 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), 0);
921 break; 921 break;
922   922  
923 default: 923 default:
924 dev_err(smi->parent, 924 dev_err(smi->parent,
925 "invalid mode for external interface %d\n", id); 925 "invalid mode for external interface %d\n", id);
926 return -EINVAL; 926 return -EINVAL;
927 } 927 }
928   928  
929 REG_RMW(smi, RTL8367_DIS_REG, 929 REG_RMW(smi, RTL8367_DIS_REG,
930 RTL8367_DIS_RGMII_MASK << RTL8367_DIS_RGMII_SHIFT(id), 930 RTL8367_DIS_RGMII_MASK << RTL8367_DIS_RGMII_SHIFT(id),
931 mode << RTL8367_DIS_RGMII_SHIFT(id)); 931 mode << RTL8367_DIS_RGMII_SHIFT(id));
932   932  
933 return 0; 933 return 0;
934 } 934 }
935   935  
936 static int rtl8367_extif_set_force(struct rtl8366_smi *smi, int id, 936 static int rtl8367_extif_set_force(struct rtl8366_smi *smi, int id,
937 struct rtl8367_port_ability *pa) 937 struct rtl8367_port_ability *pa)
938 { 938 {
939 u32 mask; 939 u32 mask;
940 u32 val; 940 u32 val;
941 int err; 941 int err;
942   942  
943 mask = (RTL8367_DI_FORCE_MODE | 943 mask = (RTL8367_DI_FORCE_MODE |
944 RTL8367_DI_FORCE_NWAY | 944 RTL8367_DI_FORCE_NWAY |
945 RTL8367_DI_FORCE_TXPAUSE | 945 RTL8367_DI_FORCE_TXPAUSE |
946 RTL8367_DI_FORCE_RXPAUSE | 946 RTL8367_DI_FORCE_RXPAUSE |
947 RTL8367_DI_FORCE_LINK | 947 RTL8367_DI_FORCE_LINK |
948 RTL8367_DI_FORCE_DUPLEX | 948 RTL8367_DI_FORCE_DUPLEX |
949 RTL8367_DI_FORCE_SPEED_MASK); 949 RTL8367_DI_FORCE_SPEED_MASK);
950   950  
951 val = pa->speed; 951 val = pa->speed;
952 val |= pa->force_mode ? RTL8367_DI_FORCE_MODE : 0; 952 val |= pa->force_mode ? RTL8367_DI_FORCE_MODE : 0;
953 val |= pa->nway ? RTL8367_DI_FORCE_NWAY : 0; 953 val |= pa->nway ? RTL8367_DI_FORCE_NWAY : 0;
954 val |= pa->txpause ? RTL8367_DI_FORCE_TXPAUSE : 0; 954 val |= pa->txpause ? RTL8367_DI_FORCE_TXPAUSE : 0;
955 val |= pa->rxpause ? RTL8367_DI_FORCE_RXPAUSE : 0; 955 val |= pa->rxpause ? RTL8367_DI_FORCE_RXPAUSE : 0;
956 val |= pa->link ? RTL8367_DI_FORCE_LINK : 0; 956 val |= pa->link ? RTL8367_DI_FORCE_LINK : 0;
957 val |= pa->duplex ? RTL8367_DI_FORCE_DUPLEX : 0; 957 val |= pa->duplex ? RTL8367_DI_FORCE_DUPLEX : 0;
958   958  
959 REG_RMW(smi, RTL8367_DI_FORCE_REG(id), mask, val); 959 REG_RMW(smi, RTL8367_DI_FORCE_REG(id), mask, val);
960   960  
961 return 0; 961 return 0;
962 } 962 }
963   963  
964 static int rtl8367_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id, 964 static int rtl8367_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,
965 unsigned txdelay, unsigned rxdelay) 965 unsigned txdelay, unsigned rxdelay)
966 { 966 {
967 u32 mask; 967 u32 mask;
968 u32 val; 968 u32 val;
969 int err; 969 int err;
970   970  
971 mask = (RTL8367_EXT_RGMXF_RXDELAY_MASK | 971 mask = (RTL8367_EXT_RGMXF_RXDELAY_MASK |
972 (RTL8367_EXT_RGMXF_TXDELAY_MASK << 972 (RTL8367_EXT_RGMXF_TXDELAY_MASK <<
973 RTL8367_EXT_RGMXF_TXDELAY_SHIFT)); 973 RTL8367_EXT_RGMXF_TXDELAY_SHIFT));
974   974  
975 val = rxdelay; 975 val = rxdelay;
976 val |= txdelay << RTL8367_EXT_RGMXF_TXDELAY_SHIFT; 976 val |= txdelay << RTL8367_EXT_RGMXF_TXDELAY_SHIFT;
977   977  
978 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), mask, val); 978 REG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), mask, val);
979   979  
980 return 0; 980 return 0;
981 } 981 }
982   982  
983 static int rtl8367_extif_init(struct rtl8366_smi *smi, int id, 983 static int rtl8367_extif_init(struct rtl8366_smi *smi, int id,
984 struct rtl8367_extif_config *cfg) 984 struct rtl8367_extif_config *cfg)
985 { 985 {
986 enum rtl8367_extif_mode mode; 986 enum rtl8367_extif_mode mode;
987 int err; 987 int err;
988   988  
989 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED; 989 mode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;
990   990  
991 err = rtl8367_extif_set_mode(smi, id, mode); 991 err = rtl8367_extif_set_mode(smi, id, mode);
992 if (err) 992 if (err)
993 return err; 993 return err;
994   994  
995 if (mode != RTL8367_EXTIF_MODE_DISABLED) { 995 if (mode != RTL8367_EXTIF_MODE_DISABLED) {
996 err = rtl8367_extif_set_force(smi, id, &cfg->ability); 996 err = rtl8367_extif_set_force(smi, id, &cfg->ability);
997 if (err) 997 if (err)
998 return err; 998 return err;
999   999  
1000 err = rtl8367_extif_set_rgmii_delay(smi, id, cfg->txdelay, 1000 err = rtl8367_extif_set_rgmii_delay(smi, id, cfg->txdelay,
1001 cfg->rxdelay); 1001 cfg->rxdelay);
1002 if (err) 1002 if (err)
1003 return err; 1003 return err;
1004 } 1004 }
1005   1005  
1006 return 0; 1006 return 0;
1007 } 1007 }
1008   1008  
1009 static int rtl8367_led_group_set_ports(struct rtl8366_smi *smi, 1009 static int rtl8367_led_group_set_ports(struct rtl8366_smi *smi,
1010 unsigned int group, u16 port_mask) 1010 unsigned int group, u16 port_mask)
1011 { 1011 {
1012 u32 reg; 1012 u32 reg;
1013 u32 s; 1013 u32 s;
1014 int err; 1014 int err;
1015   1015  
1016 port_mask &= RTL8367_PARA_LED_IO_EN_PMASK; 1016 port_mask &= RTL8367_PARA_LED_IO_EN_PMASK;
1017 s = (group % 2) * 8; 1017 s = (group % 2) * 8;
1018 reg = RTL8367_PARA_LED_IO_EN1_REG + (group / 2); 1018 reg = RTL8367_PARA_LED_IO_EN1_REG + (group / 2);
1019   1019  
1020 REG_RMW(smi, reg, (RTL8367_PARA_LED_IO_EN_PMASK << s), port_mask << s); 1020 REG_RMW(smi, reg, (RTL8367_PARA_LED_IO_EN_PMASK << s), port_mask << s);
1021   1021  
1022 return 0; 1022 return 0;
1023 } 1023 }
1024   1024  
1025 static int rtl8367_led_group_set_mode(struct rtl8366_smi *smi, 1025 static int rtl8367_led_group_set_mode(struct rtl8366_smi *smi,
1026 unsigned int mode) 1026 unsigned int mode)
1027 { 1027 {
1028 u16 mask; 1028 u16 mask;
1029 u16 set; 1029 u16 set;
1030 int err; 1030 int err;
1031   1031  
1032 mode &= RTL8367_LED_CONFIG_DATA_M; 1032 mode &= RTL8367_LED_CONFIG_DATA_M;
1033   1033  
1034 mask = (RTL8367_LED_CONFIG_DATA_M << RTL8367_LED_CONFIG_DATA_S) | 1034 mask = (RTL8367_LED_CONFIG_DATA_M << RTL8367_LED_CONFIG_DATA_S) |
1035 RTL8367_LED_CONFIG_SEL; 1035 RTL8367_LED_CONFIG_SEL;
1036 set = (mode << RTL8367_LED_CONFIG_DATA_S) | RTL8367_LED_CONFIG_SEL; 1036 set = (mode << RTL8367_LED_CONFIG_DATA_S) | RTL8367_LED_CONFIG_SEL;
1037   1037  
1038 REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set); 1038 REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set);
1039   1039  
1040 return 0; 1040 return 0;
1041 } 1041 }
1042   1042  
1043 static int rtl8367_led_group_set_config(struct rtl8366_smi *smi, 1043 static int rtl8367_led_group_set_config(struct rtl8366_smi *smi,
1044 unsigned int led, unsigned int cfg) 1044 unsigned int led, unsigned int cfg)
1045 { 1045 {
1046 u16 mask; 1046 u16 mask;
1047 u16 set; 1047 u16 set;
1048 int err; 1048 int err;
1049   1049  
1050 mask = (RTL8367_LED_CONFIG_LED_CFG_M << (led * 4)) | 1050 mask = (RTL8367_LED_CONFIG_LED_CFG_M << (led * 4)) |
1051 RTL8367_LED_CONFIG_SEL; 1051 RTL8367_LED_CONFIG_SEL;
1052 set = (cfg & RTL8367_LED_CONFIG_LED_CFG_M) << (led * 4); 1052 set = (cfg & RTL8367_LED_CONFIG_LED_CFG_M) << (led * 4);
1053   1053  
1054 REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set); 1054 REG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set);
1055 return 0; 1055 return 0;
1056 } 1056 }
1057   1057  
1058 static int rtl8367_led_op_select_parallel(struct rtl8366_smi *smi) 1058 static int rtl8367_led_op_select_parallel(struct rtl8366_smi *smi)
1059 { 1059 {
1060 int err; 1060 int err;
1061   1061  
1062 REG_WR(smi, RTL8367_LED_SYS_CONFIG_REG, 0x1472); 1062 REG_WR(smi, RTL8367_LED_SYS_CONFIG_REG, 0x1472);
1063 return 0; 1063 return 0;
1064 } 1064 }
1065   1065  
1066 static int rtl8367_led_blinkrate_set(struct rtl8366_smi *smi, unsigned int rate) 1066 static int rtl8367_led_blinkrate_set(struct rtl8366_smi *smi, unsigned int rate)
1067 { 1067 {
1068 u16 mask; 1068 u16 mask;
1069 u16 set; 1069 u16 set;
1070 int err; 1070 int err;
1071   1071  
1072 mask = RTL8367_LED_MODE_RATE_M << RTL8367_LED_MODE_RATE_S; 1072 mask = RTL8367_LED_MODE_RATE_M << RTL8367_LED_MODE_RATE_S;
1073 set = (rate & RTL8367_LED_MODE_RATE_M) << RTL8367_LED_MODE_RATE_S; 1073 set = (rate & RTL8367_LED_MODE_RATE_M) << RTL8367_LED_MODE_RATE_S;
1074 REG_RMW(smi, RTL8367_LED_MODE_REG, mask, set); 1074 REG_RMW(smi, RTL8367_LED_MODE_REG, mask, set);
1075   1075  
1076 return 0; 1076 return 0;
1077 } 1077 }
1078   1078  
1079 #ifdef CONFIG_OF 1079 #ifdef CONFIG_OF
1080 static int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id, 1080 static int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id,
1081 const char *name) 1081 const char *name)
1082 { 1082 {
1083 struct rtl8367_extif_config *cfg; 1083 struct rtl8367_extif_config *cfg;
1084 const __be32 *prop; 1084 const __be32 *prop;
1085 int size; 1085 int size;
1086 int err; 1086 int err;
1087   1087  
1088 prop = of_get_property(smi->parent->of_node, name, &size); 1088 prop = of_get_property(smi->parent->of_node, name, &size);
1089 if (!prop) 1089 if (!prop)
1090 return rtl8367_extif_init(smi, id, NULL); 1090 return rtl8367_extif_init(smi, id, NULL);
1091   1091  
1092 if (size != (9 * sizeof(*prop))) { 1092 if (size != (9 * sizeof(*prop))) {
1093 dev_err(smi->parent, "%s property is invalid\n", name); 1093 dev_err(smi->parent, "%s property is invalid\n", name);
1094 return -EINVAL; 1094 return -EINVAL;
1095 } 1095 }
1096   1096  
1097 cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL); 1097 cfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);
1098 if (!cfg) 1098 if (!cfg)
1099 return -ENOMEM; 1099 return -ENOMEM;
1100   1100  
1101 cfg->txdelay = be32_to_cpup(prop++); 1101 cfg->txdelay = be32_to_cpup(prop++);
1102 cfg->rxdelay = be32_to_cpup(prop++); 1102 cfg->rxdelay = be32_to_cpup(prop++);
1103 cfg->mode = be32_to_cpup(prop++); 1103 cfg->mode = be32_to_cpup(prop++);
1104 cfg->ability.force_mode = be32_to_cpup(prop++); 1104 cfg->ability.force_mode = be32_to_cpup(prop++);
1105 cfg->ability.txpause = be32_to_cpup(prop++); 1105 cfg->ability.txpause = be32_to_cpup(prop++);
1106 cfg->ability.rxpause = be32_to_cpup(prop++); 1106 cfg->ability.rxpause = be32_to_cpup(prop++);
1107 cfg->ability.link = be32_to_cpup(prop++); 1107 cfg->ability.link = be32_to_cpup(prop++);
1108 cfg->ability.duplex = be32_to_cpup(prop++); 1108 cfg->ability.duplex = be32_to_cpup(prop++);
1109 cfg->ability.speed = be32_to_cpup(prop++); 1109 cfg->ability.speed = be32_to_cpup(prop++);
1110   1110  
1111 err = rtl8367_extif_init(smi, id, cfg); 1111 err = rtl8367_extif_init(smi, id, cfg);
1112 kfree(cfg); 1112 kfree(cfg);
1113   1113  
1114 return err; 1114 return err;
1115 } 1115 }
1116 #else 1116 #else
1117 static int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id, 1117 static int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id,
1118 const char *name) 1118 const char *name)
1119 { 1119 {
1120 return -EINVAL; 1120 return -EINVAL;
1121 } 1121 }
1122 #endif 1122 #endif
1123   1123  
1124 static int rtl8367_setup(struct rtl8366_smi *smi) 1124 static int rtl8367_setup(struct rtl8366_smi *smi)
1125 { 1125 {
1126 struct rtl8367_platform_data *pdata; 1126 struct rtl8367_platform_data *pdata;
1127 int err; 1127 int err;
1128 int i; 1128 int i;
1129   1129  
1130 pdata = smi->parent->platform_data; 1130 pdata = smi->parent->platform_data;
1131   1131  
1132 err = rtl8367_init_regs(smi); 1132 err = rtl8367_init_regs(smi);
1133 if (err) 1133 if (err)
1134 return err; 1134 return err;
1135   1135  
1136 /* initialize external interfaces */ 1136 /* initialize external interfaces */
1137 if (smi->parent->of_node) { 1137 if (smi->parent->of_node) {
1138 err = rtl8367_extif_init_of(smi, 0, "realtek,extif0"); 1138 err = rtl8367_extif_init_of(smi, 0, "realtek,extif0");
1139 if (err) 1139 if (err)
1140 return err; 1140 return err;
1141   1141  
1142 err = rtl8367_extif_init_of(smi, 1, "realtek,extif1"); 1142 err = rtl8367_extif_init_of(smi, 1, "realtek,extif1");
1143 if (err) 1143 if (err)
1144 return err; 1144 return err;
1145 } else { 1145 } else {
1146 err = rtl8367_extif_init(smi, 0, pdata->extif0_cfg); 1146 err = rtl8367_extif_init(smi, 0, pdata->extif0_cfg);
1147 if (err) 1147 if (err)
1148 return err; 1148 return err;
1149   1149  
1150 err = rtl8367_extif_init(smi, 1, pdata->extif1_cfg); 1150 err = rtl8367_extif_init(smi, 1, pdata->extif1_cfg);
1151 if (err) 1151 if (err)
1152 return err; 1152 return err;
1153 } 1153 }
1154   1154  
1155 /* set maximum packet length to 1536 bytes */ 1155 /* set maximum packet length to 1536 bytes */
1156 REG_RMW(smi, RTL8367_SWC0_REG, RTL8367_SWC0_MAX_LENGTH_MASK, 1156 REG_RMW(smi, RTL8367_SWC0_REG, RTL8367_SWC0_MAX_LENGTH_MASK,
1157 RTL8367_SWC0_MAX_LENGTH_1536); 1157 RTL8367_SWC0_MAX_LENGTH_1536);
1158   1158  
1159 /* 1159 /*
1160 * discard VLAN tagged packets if the port is not a member of 1160 * discard VLAN tagged packets if the port is not a member of
1161 * the VLAN with which the packets is associated. 1161 * the VLAN with which the packets is associated.
1162 */ 1162 */
1163 REG_WR(smi, RTL8367_VLAN_INGRESS_REG, RTL8367_PORTS_ALL); 1163 REG_WR(smi, RTL8367_VLAN_INGRESS_REG, RTL8367_PORTS_ALL);
1164   1164  
1165 /* 1165 /*
1166 * Setup egress tag mode for each port. 1166 * Setup egress tag mode for each port.
1167 */ 1167 */
1168 for (i = 0; i < RTL8367_NUM_PORTS; i++) 1168 for (i = 0; i < RTL8367_NUM_PORTS; i++)
1169 REG_RMW(smi, 1169 REG_RMW(smi,
1170 RTL8367_PORT_CFG_REG(i), 1170 RTL8367_PORT_CFG_REG(i),
1171 RTL8367_PORT_CFG_EGRESS_MODE_MASK << 1171 RTL8367_PORT_CFG_EGRESS_MODE_MASK <<
1172 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT, 1172 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT,
1173 RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL << 1173 RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL <<
1174 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT); 1174 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT);
1175   1175  
1176 /* setup LEDs */ 1176 /* setup LEDs */
1177 err = rtl8367_led_group_set_ports(smi, 0, RTL8367_PORTS_ALL); 1177 err = rtl8367_led_group_set_ports(smi, 0, RTL8367_PORTS_ALL);
1178 if (err) 1178 if (err)
1179 return err; 1179 return err;
1180   1180  
1181 err = rtl8367_led_group_set_mode(smi, 0); 1181 err = rtl8367_led_group_set_mode(smi, 0);
1182 if (err) 1182 if (err)
1183 return err; 1183 return err;
1184   1184  
1185 err = rtl8367_led_op_select_parallel(smi); 1185 err = rtl8367_led_op_select_parallel(smi);
1186 if (err) 1186 if (err)
1187 return err; 1187 return err;
1188   1188  
1189 err = rtl8367_led_blinkrate_set(smi, 1); 1189 err = rtl8367_led_blinkrate_set(smi, 1);
1190 if (err) 1190 if (err)
1191 return err; 1191 return err;
1192   1192  
1193 err = rtl8367_led_group_set_config(smi, 0, 2); 1193 err = rtl8367_led_group_set_config(smi, 0, 2);
1194 if (err) 1194 if (err)
1195 return err; 1195 return err;
1196   1196  
1197 return 0; 1197 return 0;
1198 } 1198 }
1199   1199  
1200 static int rtl8367_get_mib_counter(struct rtl8366_smi *smi, int counter, 1200 static int rtl8367_get_mib_counter(struct rtl8366_smi *smi, int counter,
1201 int port, unsigned long long *val) 1201 int port, unsigned long long *val)
1202 { 1202 {
1203 struct rtl8366_mib_counter *mib; 1203 struct rtl8366_mib_counter *mib;
1204 int offset; 1204 int offset;
1205 int i; 1205 int i;
1206 int err; 1206 int err;
1207 u32 addr, data; 1207 u32 addr, data;
1208 u64 mibvalue; 1208 u64 mibvalue;
1209   1209  
1210 if (port > RTL8367_NUM_PORTS || counter >= RTL8367_MIB_COUNT) 1210 if (port > RTL8367_NUM_PORTS || counter >= RTL8367_MIB_COUNT)
1211 return -EINVAL; 1211 return -EINVAL;
1212   1212  
1213 mib = &rtl8367_mib_counters[counter]; 1213 mib = &rtl8367_mib_counters[counter];
1214 addr = RTL8367_MIB_COUNTER_PORT_OFFSET * port + mib->offset; 1214 addr = RTL8367_MIB_COUNTER_PORT_OFFSET * port + mib->offset;
1215   1215  
1216 /* 1216 /*
1217 * Writing access counter address first 1217 * Writing access counter address first
1218 * then ASIC will prepare 64bits counter wait for being retrived 1218 * then ASIC will prepare 64bits counter wait for being retrived
1219 */ 1219 */
1220 REG_WR(smi, RTL8367_MIB_ADDRESS_REG, addr >> 2); 1220 REG_WR(smi, RTL8367_MIB_ADDRESS_REG, addr >> 2);
1221   1221  
1222 /* read MIB control register */ 1222 /* read MIB control register */
1223 REG_RD(smi, RTL8367_MIB_CTRL_REG(0), &data); 1223 REG_RD(smi, RTL8367_MIB_CTRL_REG(0), &data);
1224   1224  
1225 if (data & RTL8367_MIB_CTRL_BUSY_MASK) 1225 if (data & RTL8367_MIB_CTRL_BUSY_MASK)
1226 return -EBUSY; 1226 return -EBUSY;
1227   1227  
1228 if (data & RTL8367_MIB_CTRL_RESET_MASK) 1228 if (data & RTL8367_MIB_CTRL_RESET_MASK)
1229 return -EIO; 1229 return -EIO;
1230   1230  
1231 if (mib->length == 4) 1231 if (mib->length == 4)
1232 offset = 3; 1232 offset = 3;
1233 else 1233 else
1234 offset = (mib->offset + 1) % 4; 1234 offset = (mib->offset + 1) % 4;
1235   1235  
1236 mibvalue = 0; 1236 mibvalue = 0;
1237 for (i = 0; i < mib->length; i++) { 1237 for (i = 0; i < mib->length; i++) {
1238 REG_RD(smi, RTL8367_MIB_COUNTER_REG(offset - i), &data); 1238 REG_RD(smi, RTL8367_MIB_COUNTER_REG(offset - i), &data);
1239 mibvalue = (mibvalue << 16) | (data & 0xFFFF); 1239 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
1240 } 1240 }
1241   1241  
1242 *val = mibvalue; 1242 *val = mibvalue;
1243 return 0; 1243 return 0;
1244 } 1244 }
1245   1245  
1246 static int rtl8367_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, 1246 static int rtl8367_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
1247 struct rtl8366_vlan_4k *vlan4k) 1247 struct rtl8366_vlan_4k *vlan4k)
1248 { 1248 {
1249 u32 data[RTL8367_TA_VLAN_DATA_SIZE]; 1249 u32 data[RTL8367_TA_VLAN_DATA_SIZE];
1250 int err; 1250 int err;
1251 int i; 1251 int i;
1252   1252  
1253 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); 1253 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1254   1254  
1255 if (vid >= RTL8367_NUM_VIDS) 1255 if (vid >= RTL8367_NUM_VIDS)
1256 return -EINVAL; 1256 return -EINVAL;
1257   1257  
1258 /* write VID */ 1258 /* write VID */
1259 REG_WR(smi, RTL8367_TA_ADDR_REG, vid); 1259 REG_WR(smi, RTL8367_TA_ADDR_REG, vid);
1260   1260  
1261 /* write table access control word */ 1261 /* write table access control word */
1262 REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_READ); 1262 REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_READ);
1263   1263  
1264 for (i = 0; i < ARRAY_SIZE(data); i++) 1264 for (i = 0; i < ARRAY_SIZE(data); i++)
1265 REG_RD(smi, RTL8367_TA_DATA_REG(i), &data[i]); 1265 REG_RD(smi, RTL8367_TA_DATA_REG(i), &data[i]);
1266   1266  
1267 vlan4k->vid = vid; 1267 vlan4k->vid = vid;
1268 vlan4k->member = (data[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT) & 1268 vlan4k->member = (data[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT) &
1269 RTL8367_TA_VLAN_MEMBER_MASK; 1269 RTL8367_TA_VLAN_MEMBER_MASK;
1270 vlan4k->fid = (data[1] >> RTL8367_TA_VLAN_FID_SHIFT) & 1270 vlan4k->fid = (data[1] >> RTL8367_TA_VLAN_FID_SHIFT) &
1271 RTL8367_TA_VLAN_FID_MASK; 1271 RTL8367_TA_VLAN_FID_MASK;
1272 vlan4k->untag = (data[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT) & 1272 vlan4k->untag = (data[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT) &
1273 RTL8367_TA_VLAN_UNTAG1_MASK; 1273 RTL8367_TA_VLAN_UNTAG1_MASK;
1274 vlan4k->untag |= ((data[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT) & 1274 vlan4k->untag |= ((data[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT) &
1275 RTL8367_TA_VLAN_UNTAG2_MASK) << 2; 1275 RTL8367_TA_VLAN_UNTAG2_MASK) << 2;
1276   1276  
1277 return 0; 1277 return 0;
1278 } 1278 }
1279   1279  
1280 static int rtl8367_set_vlan_4k(struct rtl8366_smi *smi, 1280 static int rtl8367_set_vlan_4k(struct rtl8366_smi *smi,
1281 const struct rtl8366_vlan_4k *vlan4k) 1281 const struct rtl8366_vlan_4k *vlan4k)
1282 { 1282 {
1283 u32 data[RTL8367_TA_VLAN_DATA_SIZE]; 1283 u32 data[RTL8367_TA_VLAN_DATA_SIZE];
1284 int err; 1284 int err;
1285 int i; 1285 int i;
1286   1286  
1287 if (vlan4k->vid >= RTL8367_NUM_VIDS || 1287 if (vlan4k->vid >= RTL8367_NUM_VIDS ||
1288 vlan4k->member > RTL8367_TA_VLAN_MEMBER_MASK || 1288 vlan4k->member > RTL8367_TA_VLAN_MEMBER_MASK ||
1289 vlan4k->untag > RTL8367_UNTAG_MASK || 1289 vlan4k->untag > RTL8367_UNTAG_MASK ||
1290 vlan4k->fid > RTL8367_FIDMAX) 1290 vlan4k->fid > RTL8367_FIDMAX)
1291 return -EINVAL; 1291 return -EINVAL;
1292   1292  
1293 data[0] = (vlan4k->member & RTL8367_TA_VLAN_MEMBER_MASK) << 1293 data[0] = (vlan4k->member & RTL8367_TA_VLAN_MEMBER_MASK) <<
1294 RTL8367_TA_VLAN_MEMBER_SHIFT; 1294 RTL8367_TA_VLAN_MEMBER_SHIFT;
1295 data[1] = (vlan4k->fid & RTL8367_TA_VLAN_FID_MASK) << 1295 data[1] = (vlan4k->fid & RTL8367_TA_VLAN_FID_MASK) <<
1296 RTL8367_TA_VLAN_FID_SHIFT; 1296 RTL8367_TA_VLAN_FID_SHIFT;
1297 data[2] = (vlan4k->untag & RTL8367_TA_VLAN_UNTAG1_MASK) << 1297 data[2] = (vlan4k->untag & RTL8367_TA_VLAN_UNTAG1_MASK) <<
1298 RTL8367_TA_VLAN_UNTAG1_SHIFT; 1298 RTL8367_TA_VLAN_UNTAG1_SHIFT;
1299 data[3] = ((vlan4k->untag >> 2) & RTL8367_TA_VLAN_UNTAG2_MASK) << 1299 data[3] = ((vlan4k->untag >> 2) & RTL8367_TA_VLAN_UNTAG2_MASK) <<
1300 RTL8367_TA_VLAN_UNTAG2_SHIFT; 1300 RTL8367_TA_VLAN_UNTAG2_SHIFT;
1301   1301  
1302 for (i = 0; i < ARRAY_SIZE(data); i++) 1302 for (i = 0; i < ARRAY_SIZE(data); i++)
1303 REG_WR(smi, RTL8367_TA_DATA_REG(i), data[i]); 1303 REG_WR(smi, RTL8367_TA_DATA_REG(i), data[i]);
1304   1304  
1305 /* write VID */ 1305 /* write VID */
1306 REG_WR(smi, RTL8367_TA_ADDR_REG, 1306 REG_WR(smi, RTL8367_TA_ADDR_REG,
1307 vlan4k->vid & RTL8367_TA_VLAN_VID_MASK); 1307 vlan4k->vid & RTL8367_TA_VLAN_VID_MASK);
1308   1308  
1309 /* write table access control word */ 1309 /* write table access control word */
1310 REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_WRITE); 1310 REG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_WRITE);
1311   1311  
1312 return 0; 1312 return 0;
1313 } 1313 }
1314   1314  
1315 static int rtl8367_get_vlan_mc(struct rtl8366_smi *smi, u32 index, 1315 static int rtl8367_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
1316 struct rtl8366_vlan_mc *vlanmc) 1316 struct rtl8366_vlan_mc *vlanmc)
1317 { 1317 {
1318 u32 data[RTL8367_VLAN_MC_DATA_SIZE]; 1318 u32 data[RTL8367_VLAN_MC_DATA_SIZE];
1319 int err; 1319 int err;
1320 int i; 1320 int i;
1321   1321  
1322 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); 1322 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1323   1323  
1324 if (index >= RTL8367_NUM_VLANS) 1324 if (index >= RTL8367_NUM_VLANS)
1325 return -EINVAL; 1325 return -EINVAL;
1326   1326  
1327 for (i = 0; i < ARRAY_SIZE(data); i++) 1327 for (i = 0; i < ARRAY_SIZE(data); i++)
1328 REG_RD(smi, RTL8367_VLAN_MC_BASE(index) + i, &data[i]); 1328 REG_RD(smi, RTL8367_VLAN_MC_BASE(index) + i, &data[i]);
1329   1329  
1330 vlanmc->member = (data[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT) & 1330 vlanmc->member = (data[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT) &
1331 RTL8367_VLAN_MC_MEMBER_MASK; 1331 RTL8367_VLAN_MC_MEMBER_MASK;
1332 vlanmc->fid = (data[1] >> RTL8367_VLAN_MC_FID_SHIFT) & 1332 vlanmc->fid = (data[1] >> RTL8367_VLAN_MC_FID_SHIFT) &
1333 RTL8367_VLAN_MC_FID_MASK; 1333 RTL8367_VLAN_MC_FID_MASK;
1334 vlanmc->vid = (data[3] >> RTL8367_VLAN_MC_EVID_SHIFT) & 1334 vlanmc->vid = (data[3] >> RTL8367_VLAN_MC_EVID_SHIFT) &
1335 RTL8367_VLAN_MC_EVID_MASK; 1335 RTL8367_VLAN_MC_EVID_MASK;
1336   1336  
1337 return 0; 1337 return 0;
1338 } 1338 }
1339   1339  
1340 static int rtl8367_set_vlan_mc(struct rtl8366_smi *smi, u32 index, 1340 static int rtl8367_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
1341 const struct rtl8366_vlan_mc *vlanmc) 1341 const struct rtl8366_vlan_mc *vlanmc)
1342 { 1342 {
1343 u32 data[RTL8367_VLAN_MC_DATA_SIZE]; 1343 u32 data[RTL8367_VLAN_MC_DATA_SIZE];
1344 int err; 1344 int err;
1345 int i; 1345 int i;
1346   1346  
1347 if (index >= RTL8367_NUM_VLANS || 1347 if (index >= RTL8367_NUM_VLANS ||
1348 vlanmc->vid >= RTL8367_NUM_VIDS || 1348 vlanmc->vid >= RTL8367_NUM_VIDS ||
1349 vlanmc->priority > RTL8367_PRIORITYMAX || 1349 vlanmc->priority > RTL8367_PRIORITYMAX ||
1350 vlanmc->member > RTL8367_VLAN_MC_MEMBER_MASK || 1350 vlanmc->member > RTL8367_VLAN_MC_MEMBER_MASK ||
1351 vlanmc->untag > RTL8367_UNTAG_MASK || 1351 vlanmc->untag > RTL8367_UNTAG_MASK ||
1352 vlanmc->fid > RTL8367_FIDMAX) 1352 vlanmc->fid > RTL8367_FIDMAX)
1353 return -EINVAL; 1353 return -EINVAL;
1354   1354  
1355 data[0] = (vlanmc->member & RTL8367_VLAN_MC_MEMBER_MASK) << 1355 data[0] = (vlanmc->member & RTL8367_VLAN_MC_MEMBER_MASK) <<
1356 RTL8367_VLAN_MC_MEMBER_SHIFT; 1356 RTL8367_VLAN_MC_MEMBER_SHIFT;
1357 data[1] = (vlanmc->fid & RTL8367_VLAN_MC_FID_MASK) << 1357 data[1] = (vlanmc->fid & RTL8367_VLAN_MC_FID_MASK) <<
1358 RTL8367_VLAN_MC_FID_SHIFT; 1358 RTL8367_VLAN_MC_FID_SHIFT;
1359 data[2] = 0; 1359 data[2] = 0;
1360 data[3] = (vlanmc->vid & RTL8367_VLAN_MC_EVID_MASK) << 1360 data[3] = (vlanmc->vid & RTL8367_VLAN_MC_EVID_MASK) <<
1361 RTL8367_VLAN_MC_EVID_SHIFT; 1361 RTL8367_VLAN_MC_EVID_SHIFT;
1362   1362  
1363 for (i = 0; i < ARRAY_SIZE(data); i++) 1363 for (i = 0; i < ARRAY_SIZE(data); i++)
1364 REG_WR(smi, RTL8367_VLAN_MC_BASE(index) + i, data[i]); 1364 REG_WR(smi, RTL8367_VLAN_MC_BASE(index) + i, data[i]);
1365   1365  
1366 return 0; 1366 return 0;
1367 } 1367 }
1368   1368  
1369 static int rtl8367_get_mc_index(struct rtl8366_smi *smi, int port, int *val) 1369 static int rtl8367_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
1370 { 1370 {
1371 u32 data; 1371 u32 data;
1372 int err; 1372 int err;
1373   1373  
1374 if (port >= RTL8367_NUM_PORTS) 1374 if (port >= RTL8367_NUM_PORTS)
1375 return -EINVAL; 1375 return -EINVAL;
1376   1376  
1377 REG_RD(smi, RTL8367_VLAN_PVID_CTRL_REG(port), &data); 1377 REG_RD(smi, RTL8367_VLAN_PVID_CTRL_REG(port), &data);
1378   1378  
1379 *val = (data >> RTL8367_VLAN_PVID_CTRL_SHIFT(port)) & 1379 *val = (data >> RTL8367_VLAN_PVID_CTRL_SHIFT(port)) &
1380 RTL8367_VLAN_PVID_CTRL_MASK; 1380 RTL8367_VLAN_PVID_CTRL_MASK;
1381   1381  
1382 return 0; 1382 return 0;
1383 } 1383 }
1384   1384  
1385 static int rtl8367_set_mc_index(struct rtl8366_smi *smi, int port, int index) 1385 static int rtl8367_set_mc_index(struct rtl8366_smi *smi, int port, int index)
1386 { 1386 {
1387 if (port >= RTL8367_NUM_PORTS || index >= RTL8367_NUM_VLANS) 1387 if (port >= RTL8367_NUM_PORTS || index >= RTL8367_NUM_VLANS)
1388 return -EINVAL; 1388 return -EINVAL;
1389   1389  
1390 return rtl8366_smi_rmwr(smi, RTL8367_VLAN_PVID_CTRL_REG(port), 1390 return rtl8366_smi_rmwr(smi, RTL8367_VLAN_PVID_CTRL_REG(port),
1391 RTL8367_VLAN_PVID_CTRL_MASK << 1391 RTL8367_VLAN_PVID_CTRL_MASK <<
1392 RTL8367_VLAN_PVID_CTRL_SHIFT(port), 1392 RTL8367_VLAN_PVID_CTRL_SHIFT(port),
1393 (index & RTL8367_VLAN_PVID_CTRL_MASK) << 1393 (index & RTL8367_VLAN_PVID_CTRL_MASK) <<
1394 RTL8367_VLAN_PVID_CTRL_SHIFT(port)); 1394 RTL8367_VLAN_PVID_CTRL_SHIFT(port));
1395 } 1395 }
1396   1396  
1397 static int rtl8367_enable_vlan(struct rtl8366_smi *smi, int enable) 1397 static int rtl8367_enable_vlan(struct rtl8366_smi *smi, int enable)
1398 { 1398 {
1399 return rtl8366_smi_rmwr(smi, RTL8367_VLAN_CTRL_REG, 1399 return rtl8366_smi_rmwr(smi, RTL8367_VLAN_CTRL_REG,
1400 RTL8367_VLAN_CTRL_ENABLE, 1400 RTL8367_VLAN_CTRL_ENABLE,
1401 (enable) ? RTL8367_VLAN_CTRL_ENABLE : 0); 1401 (enable) ? RTL8367_VLAN_CTRL_ENABLE : 0);
1402 } 1402 }
1403   1403  
1404 static int rtl8367_enable_vlan4k(struct rtl8366_smi *smi, int enable) 1404 static int rtl8367_enable_vlan4k(struct rtl8366_smi *smi, int enable)
1405 { 1405 {
1406 return 0; 1406 return 0;
1407 } 1407 }
1408   1408  
1409 static int rtl8367_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) 1409 static int rtl8367_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
1410 { 1410 {
1411 unsigned max = RTL8367_NUM_VLANS; 1411 unsigned max = RTL8367_NUM_VLANS;
1412   1412  
1413 if (smi->vlan4k_enabled) 1413 if (smi->vlan4k_enabled)
1414 max = RTL8367_NUM_VIDS - 1; 1414 max = RTL8367_NUM_VIDS - 1;
1415   1415  
1416 if (vlan == 0 || vlan >= max) 1416 if (vlan == 0 || vlan >= max)
1417 return 0; 1417 return 0;
1418   1418  
1419 return 1; 1419 return 1;
1420 } 1420 }
1421   1421  
1422 static int rtl8367_enable_port(struct rtl8366_smi *smi, int port, int enable) 1422 static int rtl8367_enable_port(struct rtl8366_smi *smi, int port, int enable)
1423 { 1423 {
1424 int err; 1424 int err;
1425   1425  
1426 REG_WR(smi, RTL8367_PORT_ISOLATION_REG(port), 1426 REG_WR(smi, RTL8367_PORT_ISOLATION_REG(port),
1427 (enable) ? RTL8367_PORTS_ALL : 0); 1427 (enable) ? RTL8367_PORTS_ALL : 0);
1428   1428  
1429 return 0; 1429 return 0;
1430 } 1430 }
1431   1431  
1432 static int rtl8367_sw_reset_mibs(struct switch_dev *dev, 1432 static int rtl8367_sw_reset_mibs(struct switch_dev *dev,
1433 const struct switch_attr *attr, 1433 const struct switch_attr *attr,
1434 struct switch_val *val) 1434 struct switch_val *val)
1435 { 1435 {
1436 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); 1436 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1437   1437  
1438 return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(0), 0, 1438 return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(0), 0,
1439 RTL8367_MIB_CTRL_GLOBAL_RESET_MASK); 1439 RTL8367_MIB_CTRL_GLOBAL_RESET_MASK);
1440 } 1440 }
1441   1441  
1442 static int rtl8367_sw_get_port_link(struct switch_dev *dev, 1442 static int rtl8367_sw_get_port_link(struct switch_dev *dev,
1443 int port, 1443 int port,
1444 struct switch_port_link *link) 1444 struct switch_port_link *link)
1445 { 1445 {
1446 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); 1446 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1447 u32 data = 0; 1447 u32 data = 0;
1448 u32 speed; 1448 u32 speed;
1449   1449  
1450 if (port >= RTL8367_NUM_PORTS) 1450 if (port >= RTL8367_NUM_PORTS)
1451 return -EINVAL; 1451 return -EINVAL;
1452   1452  
1453 rtl8366_smi_read_reg(smi, RTL8367_PORT_STATUS_REG(port), &data); 1453 rtl8366_smi_read_reg(smi, RTL8367_PORT_STATUS_REG(port), &data);
1454   1454  
1455 link->link = !!(data & RTL8367_PORT_STATUS_LINK); 1455 link->link = !!(data & RTL8367_PORT_STATUS_LINK);
1456 if (!link->link) 1456 if (!link->link)
1457 return 0; 1457 return 0;
1458   1458  
1459 link->duplex = !!(data & RTL8367_PORT_STATUS_DUPLEX); 1459 link->duplex = !!(data & RTL8367_PORT_STATUS_DUPLEX);
1460 link->rx_flow = !!(data & RTL8367_PORT_STATUS_RXPAUSE); 1460 link->rx_flow = !!(data & RTL8367_PORT_STATUS_RXPAUSE);
1461 link->tx_flow = !!(data & RTL8367_PORT_STATUS_TXPAUSE); 1461 link->tx_flow = !!(data & RTL8367_PORT_STATUS_TXPAUSE);
1462 link->aneg = !!(data & RTL8367_PORT_STATUS_NWAY); 1462 link->aneg = !!(data & RTL8367_PORT_STATUS_NWAY);
1463   1463  
1464 speed = (data & RTL8367_PORT_STATUS_SPEED_MASK); 1464 speed = (data & RTL8367_PORT_STATUS_SPEED_MASK);
1465 switch (speed) { 1465 switch (speed) {
1466 case 0: 1466 case 0:
1467 link->speed = SWITCH_PORT_SPEED_10; 1467 link->speed = SWITCH_PORT_SPEED_10;
1468 break; 1468 break;
1469 case 1: 1469 case 1:
1470 link->speed = SWITCH_PORT_SPEED_100; 1470 link->speed = SWITCH_PORT_SPEED_100;
1471 break; 1471 break;
1472 case 2: 1472 case 2:
1473 link->speed = SWITCH_PORT_SPEED_1000; 1473 link->speed = SWITCH_PORT_SPEED_1000;
1474 break; 1474 break;
1475 default: 1475 default:
1476 link->speed = SWITCH_PORT_SPEED_UNKNOWN; 1476 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1477 break; 1477 break;
1478 } 1478 }
1479   1479  
1480 return 0; 1480 return 0;
1481 } 1481 }
1482   1482  
1483 static int rtl8367_sw_get_max_length(struct switch_dev *dev, 1483 static int rtl8367_sw_get_max_length(struct switch_dev *dev,
1484 const struct switch_attr *attr, 1484 const struct switch_attr *attr,
1485 struct switch_val *val) 1485 struct switch_val *val)
1486 { 1486 {
1487 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); 1487 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1488 u32 data; 1488 u32 data;
1489   1489  
1490 rtl8366_smi_read_reg(smi, RTL8367_SWC0_REG, &data); 1490 rtl8366_smi_read_reg(smi, RTL8367_SWC0_REG, &data);
1491 val->value.i = (data & RTL8367_SWC0_MAX_LENGTH_MASK) >> 1491 val->value.i = (data & RTL8367_SWC0_MAX_LENGTH_MASK) >>
1492 RTL8367_SWC0_MAX_LENGTH_SHIFT; 1492 RTL8367_SWC0_MAX_LENGTH_SHIFT;
1493   1493  
1494 return 0; 1494 return 0;
1495 } 1495 }
1496   1496  
1497 static int rtl8367_sw_set_max_length(struct switch_dev *dev, 1497 static int rtl8367_sw_set_max_length(struct switch_dev *dev,
1498 const struct switch_attr *attr, 1498 const struct switch_attr *attr,
1499 struct switch_val *val) 1499 struct switch_val *val)
1500 { 1500 {
1501 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); 1501 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1502 u32 max_len; 1502 u32 max_len;
1503   1503  
1504 switch (val->value.i) { 1504 switch (val->value.i) {
1505 case 0: 1505 case 0:
1506 max_len = RTL8367_SWC0_MAX_LENGTH_1522; 1506 max_len = RTL8367_SWC0_MAX_LENGTH_1522;
1507 break; 1507 break;
1508 case 1: 1508 case 1:
1509 max_len = RTL8367_SWC0_MAX_LENGTH_1536; 1509 max_len = RTL8367_SWC0_MAX_LENGTH_1536;
1510 break; 1510 break;
1511 case 2: 1511 case 2:
1512 max_len = RTL8367_SWC0_MAX_LENGTH_1552; 1512 max_len = RTL8367_SWC0_MAX_LENGTH_1552;
1513 break; 1513 break;
1514 case 3: 1514 case 3:
1515 max_len = RTL8367_SWC0_MAX_LENGTH_16000; 1515 max_len = RTL8367_SWC0_MAX_LENGTH_16000;
1516 break; 1516 break;
1517 default: 1517 default:
1518 return -EINVAL; 1518 return -EINVAL;
1519 } 1519 }
1520   1520  
1521 return rtl8366_smi_rmwr(smi, RTL8367_SWC0_REG, 1521 return rtl8366_smi_rmwr(smi, RTL8367_SWC0_REG,
1522 RTL8367_SWC0_MAX_LENGTH_MASK, max_len); 1522 RTL8367_SWC0_MAX_LENGTH_MASK, max_len);
1523 } 1523 }
1524   1524  
1525   1525  
1526 static int rtl8367_sw_reset_port_mibs(struct switch_dev *dev, 1526 static int rtl8367_sw_reset_port_mibs(struct switch_dev *dev,
1527 const struct switch_attr *attr, 1527 const struct switch_attr *attr,
1528 struct switch_val *val) 1528 struct switch_val *val)
1529 { 1529 {
1530 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); 1530 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1531 int port; 1531 int port;
1532   1532  
1533 port = val->port_vlan; 1533 port = val->port_vlan;
1534 if (port >= RTL8367_NUM_PORTS) 1534 if (port >= RTL8367_NUM_PORTS)
1535 return -EINVAL; 1535 return -EINVAL;
1536   1536  
1537 return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(port / 8), 0, 1537 return rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(port / 8), 0,
1538 RTL8367_MIB_CTRL_PORT_RESET_MASK(port % 8)); 1538 RTL8367_MIB_CTRL_PORT_RESET_MASK(port % 8));
1539 } 1539 }
1540   1540  
1541 static int rtl8367_sw_get_port_stats(struct switch_dev *dev, int port, 1541 static int rtl8367_sw_get_port_stats(struct switch_dev *dev, int port,
1542 struct switch_port_stats *stats) 1542 struct switch_port_stats *stats)
1543 { 1543 {
1544 return (rtl8366_sw_get_port_stats(dev, port, stats, 1544 return (rtl8366_sw_get_port_stats(dev, port, stats,
1545 RTL8367_MIB_TXB_ID, RTL8367_MIB_RXB_ID)); 1545 RTL8367_MIB_TXB_ID, RTL8367_MIB_RXB_ID));
1546 } 1546 }
1547   1547  
1548 static struct switch_attr rtl8367_globals[] = { 1548 static struct switch_attr rtl8367_globals[] = {
1549 { 1549 {
1550 .type = SWITCH_TYPE_INT, 1550 .type = SWITCH_TYPE_INT,
1551 .name = "enable_vlan", 1551 .name = "enable_vlan",
1552 .description = "Enable VLAN mode", 1552 .description = "Enable VLAN mode",
1553 .set = rtl8366_sw_set_vlan_enable, 1553 .set = rtl8366_sw_set_vlan_enable,
1554 .get = rtl8366_sw_get_vlan_enable, 1554 .get = rtl8366_sw_get_vlan_enable,
1555 .max = 1, 1555 .max = 1,
1556 .ofs = 1 1556 .ofs = 1
1557 }, { 1557 }, {
1558 .type = SWITCH_TYPE_INT, 1558 .type = SWITCH_TYPE_INT,
1559 .name = "enable_vlan4k", 1559 .name = "enable_vlan4k",
1560 .description = "Enable VLAN 4K mode", 1560 .description = "Enable VLAN 4K mode",
1561 .set = rtl8366_sw_set_vlan_enable, 1561 .set = rtl8366_sw_set_vlan_enable,
1562 .get = rtl8366_sw_get_vlan_enable, 1562 .get = rtl8366_sw_get_vlan_enable,
1563 .max = 1, 1563 .max = 1,
1564 .ofs = 2 1564 .ofs = 2
1565 }, { 1565 }, {
1566 .type = SWITCH_TYPE_NOVAL, 1566 .type = SWITCH_TYPE_NOVAL,
1567 .name = "reset_mibs", 1567 .name = "reset_mibs",
1568 .description = "Reset all MIB counters", 1568 .description = "Reset all MIB counters",
1569 .set = rtl8367_sw_reset_mibs, 1569 .set = rtl8367_sw_reset_mibs,
1570 }, { 1570 }, {
1571 .type = SWITCH_TYPE_INT, 1571 .type = SWITCH_TYPE_INT,
1572 .name = "max_length", 1572 .name = "max_length",
1573 .description = "Get/Set the maximum length of valid packets" 1573 .description = "Get/Set the maximum length of valid packets"
1574 "(0:1522, 1:1536, 2:1552, 3:16000)", 1574 "(0:1522, 1:1536, 2:1552, 3:16000)",
1575 .set = rtl8367_sw_set_max_length, 1575 .set = rtl8367_sw_set_max_length,
1576 .get = rtl8367_sw_get_max_length, 1576 .get = rtl8367_sw_get_max_length,
1577 .max = 3, 1577 .max = 3,
1578 } 1578 }
1579 }; 1579 };
1580   1580  
1581 static struct switch_attr rtl8367_port[] = { 1581 static struct switch_attr rtl8367_port[] = {
1582 { 1582 {
1583 .type = SWITCH_TYPE_NOVAL, 1583 .type = SWITCH_TYPE_NOVAL,
1584 .name = "reset_mib", 1584 .name = "reset_mib",
1585 .description = "Reset single port MIB counters", 1585 .description = "Reset single port MIB counters",
1586 .set = rtl8367_sw_reset_port_mibs, 1586 .set = rtl8367_sw_reset_port_mibs,
1587 }, { 1587 }, {
1588 .type = SWITCH_TYPE_STRING, 1588 .type = SWITCH_TYPE_STRING,
1589 .name = "mib", 1589 .name = "mib",
1590 .description = "Get MIB counters for port", 1590 .description = "Get MIB counters for port",
1591 .max = 33, 1591 .max = 33,
1592 .set = NULL, 1592 .set = NULL,
1593 .get = rtl8366_sw_get_port_mib, 1593 .get = rtl8366_sw_get_port_mib,
1594 }, 1594 },
1595 }; 1595 };
1596   1596  
1597 static struct switch_attr rtl8367_vlan[] = { 1597 static struct switch_attr rtl8367_vlan[] = {
1598 { 1598 {
1599 .type = SWITCH_TYPE_STRING, 1599 .type = SWITCH_TYPE_STRING,
1600 .name = "info", 1600 .name = "info",
1601 .description = "Get vlan information", 1601 .description = "Get vlan information",
1602 .max = 1, 1602 .max = 1,
1603 .set = NULL, 1603 .set = NULL,
1604 .get = rtl8366_sw_get_vlan_info, 1604 .get = rtl8366_sw_get_vlan_info,
1605 }, { 1605 }, {
1606 .type = SWITCH_TYPE_INT, 1606 .type = SWITCH_TYPE_INT,
1607 .name = "fid", 1607 .name = "fid",
1608 .description = "Get/Set vlan FID", 1608 .description = "Get/Set vlan FID",
1609 .max = RTL8367_FIDMAX, 1609 .max = RTL8367_FIDMAX,
1610 .set = rtl8366_sw_set_vlan_fid, 1610 .set = rtl8366_sw_set_vlan_fid,
1611 .get = rtl8366_sw_get_vlan_fid, 1611 .get = rtl8366_sw_get_vlan_fid,
1612 }, 1612 },
1613 }; 1613 };
1614   1614  
1615 static const struct switch_dev_ops rtl8367_sw_ops = { 1615 static const struct switch_dev_ops rtl8367_sw_ops = {
1616 .attr_global = { 1616 .attr_global = {
1617 .attr = rtl8367_globals, 1617 .attr = rtl8367_globals,
1618 .n_attr = ARRAY_SIZE(rtl8367_globals), 1618 .n_attr = ARRAY_SIZE(rtl8367_globals),
1619 }, 1619 },
1620 .attr_port = { 1620 .attr_port = {
1621 .attr = rtl8367_port, 1621 .attr = rtl8367_port,
1622 .n_attr = ARRAY_SIZE(rtl8367_port), 1622 .n_attr = ARRAY_SIZE(rtl8367_port),
1623 }, 1623 },
1624 .attr_vlan = { 1624 .attr_vlan = {
1625 .attr = rtl8367_vlan, 1625 .attr = rtl8367_vlan,
1626 .n_attr = ARRAY_SIZE(rtl8367_vlan), 1626 .n_attr = ARRAY_SIZE(rtl8367_vlan),
1627 }, 1627 },
1628   1628  
1629 .get_vlan_ports = rtl8366_sw_get_vlan_ports, 1629 .get_vlan_ports = rtl8366_sw_get_vlan_ports,
1630 .set_vlan_ports = rtl8366_sw_set_vlan_ports, 1630 .set_vlan_ports = rtl8366_sw_set_vlan_ports,
1631 .get_port_pvid = rtl8366_sw_get_port_pvid, 1631 .get_port_pvid = rtl8366_sw_get_port_pvid,
1632 .set_port_pvid = rtl8366_sw_set_port_pvid, 1632 .set_port_pvid = rtl8366_sw_set_port_pvid,
1633 .reset_switch = rtl8366_sw_reset_switch, 1633 .reset_switch = rtl8366_sw_reset_switch,
1634 .get_port_link = rtl8367_sw_get_port_link, 1634 .get_port_link = rtl8367_sw_get_port_link,
1635 .get_port_stats = rtl8367_sw_get_port_stats, 1635 .get_port_stats = rtl8367_sw_get_port_stats,
1636 }; 1636 };
1637   1637  
1638 static int rtl8367_switch_init(struct rtl8366_smi *smi) 1638 static int rtl8367_switch_init(struct rtl8366_smi *smi)
1639 { 1639 {
1640 struct switch_dev *dev = &smi->sw_dev; 1640 struct switch_dev *dev = &smi->sw_dev;
1641 int err; 1641 int err;
1642   1642  
1643 dev->name = "RTL8367"; 1643 dev->name = "RTL8367";
1644 dev->cpu_port = RTL8367_CPU_PORT_NUM; 1644 dev->cpu_port = RTL8367_CPU_PORT_NUM;
1645 dev->ports = RTL8367_NUM_PORTS; 1645 dev->ports = RTL8367_NUM_PORTS;
1646 dev->vlans = RTL8367_NUM_VIDS; 1646 dev->vlans = RTL8367_NUM_VIDS;
1647 dev->ops = &rtl8367_sw_ops; 1647 dev->ops = &rtl8367_sw_ops;
1648 dev->alias = dev_name(smi->parent); 1648 dev->alias = dev_name(smi->parent);
1649   1649  
1650 err = register_switch(dev, NULL); 1650 err = register_switch(dev, NULL);
1651 if (err) 1651 if (err)
1652 dev_err(smi->parent, "switch registration failed\n"); 1652 dev_err(smi->parent, "switch registration failed\n");
1653   1653  
1654 return err; 1654 return err;
1655 } 1655 }
1656   1656  
1657 static void rtl8367_switch_cleanup(struct rtl8366_smi *smi) 1657 static void rtl8367_switch_cleanup(struct rtl8366_smi *smi)
1658 { 1658 {
1659 unregister_switch(&smi->sw_dev); 1659 unregister_switch(&smi->sw_dev);
1660 } 1660 }
1661   1661  
1662 static int rtl8367_mii_read(struct mii_bus *bus, int addr, int reg) 1662 static int rtl8367_mii_read(struct mii_bus *bus, int addr, int reg)
1663 { 1663 {
1664 struct rtl8366_smi *smi = bus->priv; 1664 struct rtl8366_smi *smi = bus->priv;
1665 u32 val = 0; 1665 u32 val = 0;
1666 int err; 1666 int err;
1667   1667  
1668 err = rtl8367_read_phy_reg(smi, addr, reg, &val); 1668 err = rtl8367_read_phy_reg(smi, addr, reg, &val);
1669 if (err) 1669 if (err)
1670 return 0xffff; 1670 return 0xffff;
1671   1671  
1672 return val; 1672 return val;
1673 } 1673 }
1674   1674  
1675 static int rtl8367_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) 1675 static int rtl8367_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1676 { 1676 {
1677 struct rtl8366_smi *smi = bus->priv; 1677 struct rtl8366_smi *smi = bus->priv;
1678 u32 t; 1678 u32 t;
1679 int err; 1679 int err;
1680   1680  
1681 err = rtl8367_write_phy_reg(smi, addr, reg, val); 1681 err = rtl8367_write_phy_reg(smi, addr, reg, val);
1682 if (err) 1682 if (err)
1683 return err; 1683 return err;
1684   1684  
1685 /* flush write */ 1685 /* flush write */
1686 (void) rtl8367_read_phy_reg(smi, addr, reg, &t); 1686 (void) rtl8367_read_phy_reg(smi, addr, reg, &t);
1687   1687  
1688 return err; 1688 return err;
1689 } 1689 }
1690   1690  
1691 static int rtl8367_detect(struct rtl8366_smi *smi) 1691 static int rtl8367_detect(struct rtl8366_smi *smi)
1692 { 1692 {
1693 u32 rtl_no = 0; 1693 u32 rtl_no = 0;
1694 u32 rtl_ver = 0; 1694 u32 rtl_ver = 0;
1695 char *chip_name; 1695 char *chip_name;
1696 int ret; 1696 int ret;
1697   1697  
1698 ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_NO_REG, &rtl_no); 1698 ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_NO_REG, &rtl_no);
1699 if (ret) { 1699 if (ret) {
1700 dev_err(smi->parent, "unable to read chip number\n"); 1700 dev_err(smi->parent, "unable to read chip number\n");
1701 return ret; 1701 return ret;
1702 } 1702 }
1703   1703  
1704 switch (rtl_no) { 1704 switch (rtl_no) {
1705 case RTL8367_RTL_NO_8367R: 1705 case RTL8367_RTL_NO_8367R:
1706 chip_name = "8367R"; 1706 chip_name = "8367R";
1707 break; 1707 break;
1708 case RTL8367_RTL_NO_8367M: 1708 case RTL8367_RTL_NO_8367M:
1709 chip_name = "8367M"; 1709 chip_name = "8367M";
1710 break; 1710 break;
1711 default: 1711 default:
1712 dev_err(smi->parent, "unknown chip number (%04x)\n", rtl_no); 1712 dev_err(smi->parent, "unknown chip number (%04x)\n", rtl_no);
1713 return -ENODEV; 1713 return -ENODEV;
1714 } 1714 }
1715   1715  
1716 ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_VER_REG, &rtl_ver); 1716 ret = rtl8366_smi_read_reg(smi, RTL8367_RTL_VER_REG, &rtl_ver);
1717 if (ret) { 1717 if (ret) {
1718 dev_err(smi->parent, "unable to read chip version\n"); 1718 dev_err(smi->parent, "unable to read chip version\n");
1719 return ret; 1719 return ret;
1720 } 1720 }
1721   1721  
1722 dev_info(smi->parent, "RTL%s ver. %u chip found\n", 1722 dev_info(smi->parent, "RTL%s ver. %u chip found\n",
1723 chip_name, rtl_ver & RTL8367_RTL_VER_MASK); 1723 chip_name, rtl_ver & RTL8367_RTL_VER_MASK);
1724   1724  
1725 return 0; 1725 return 0;
1726 } 1726 }
1727   1727  
1728 static struct rtl8366_smi_ops rtl8367_smi_ops = { 1728 static struct rtl8366_smi_ops rtl8367_smi_ops = {
1729 .detect = rtl8367_detect, 1729 .detect = rtl8367_detect,
1730 .reset_chip = rtl8367_reset_chip, 1730 .reset_chip = rtl8367_reset_chip,
1731 .setup = rtl8367_setup, 1731 .setup = rtl8367_setup,
1732   1732  
1733 .mii_read = rtl8367_mii_read, 1733 .mii_read = rtl8367_mii_read,
1734 .mii_write = rtl8367_mii_write, 1734 .mii_write = rtl8367_mii_write,
1735   1735  
1736 .get_vlan_mc = rtl8367_get_vlan_mc, 1736 .get_vlan_mc = rtl8367_get_vlan_mc,
1737 .set_vlan_mc = rtl8367_set_vlan_mc, 1737 .set_vlan_mc = rtl8367_set_vlan_mc,
1738 .get_vlan_4k = rtl8367_get_vlan_4k, 1738 .get_vlan_4k = rtl8367_get_vlan_4k,
1739 .set_vlan_4k = rtl8367_set_vlan_4k, 1739 .set_vlan_4k = rtl8367_set_vlan_4k,
1740 .get_mc_index = rtl8367_get_mc_index, 1740 .get_mc_index = rtl8367_get_mc_index,
1741 .set_mc_index = rtl8367_set_mc_index, 1741 .set_mc_index = rtl8367_set_mc_index,
1742 .get_mib_counter = rtl8367_get_mib_counter, 1742 .get_mib_counter = rtl8367_get_mib_counter,
1743 .is_vlan_valid = rtl8367_is_vlan_valid, 1743 .is_vlan_valid = rtl8367_is_vlan_valid,
1744 .enable_vlan = rtl8367_enable_vlan, 1744 .enable_vlan = rtl8367_enable_vlan,
1745 .enable_vlan4k = rtl8367_enable_vlan4k, 1745 .enable_vlan4k = rtl8367_enable_vlan4k,
1746 .enable_port = rtl8367_enable_port, 1746 .enable_port = rtl8367_enable_port,
1747 }; 1747 };
1748   1748  
1749 static int rtl8367_probe(struct platform_device *pdev) 1749 static int rtl8367_probe(struct platform_device *pdev)
1750 { 1750 {
1751 struct rtl8366_smi *smi; 1751 struct rtl8366_smi *smi;
1752 int err; 1752 int err;
1753   1753  
1754 smi = rtl8366_smi_probe(pdev); 1754 smi = rtl8366_smi_probe(pdev);
1755 if (IS_ERR(smi)) 1755 if (!smi)
1756 return PTR_ERR(smi); 1756 return -ENODEV;
1757   1757  
1758 smi->clk_delay = 1500; 1758 smi->clk_delay = 1500;
1759 smi->cmd_read = 0xb9; 1759 smi->cmd_read = 0xb9;
1760 smi->cmd_write = 0xb8; 1760 smi->cmd_write = 0xb8;
1761 smi->ops = &rtl8367_smi_ops; 1761 smi->ops = &rtl8367_smi_ops;
1762 smi->cpu_port = RTL8367_CPU_PORT_NUM; 1762 smi->cpu_port = RTL8367_CPU_PORT_NUM;
1763 smi->num_ports = RTL8367_NUM_PORTS; 1763 smi->num_ports = RTL8367_NUM_PORTS;
1764 smi->num_vlan_mc = RTL8367_NUM_VLANS; 1764 smi->num_vlan_mc = RTL8367_NUM_VLANS;
1765 smi->mib_counters = rtl8367_mib_counters; 1765 smi->mib_counters = rtl8367_mib_counters;
1766 smi->num_mib_counters = ARRAY_SIZE(rtl8367_mib_counters); 1766 smi->num_mib_counters = ARRAY_SIZE(rtl8367_mib_counters);
1767   1767  
1768 err = rtl8366_smi_init(smi); 1768 err = rtl8366_smi_init(smi);
1769 if (err) 1769 if (err)
1770 goto err_free_smi; 1770 goto err_free_smi;
1771   1771  
1772 platform_set_drvdata(pdev, smi); 1772 platform_set_drvdata(pdev, smi);
1773   1773  
1774 err = rtl8367_switch_init(smi); 1774 err = rtl8367_switch_init(smi);
1775 if (err) 1775 if (err)
1776 goto err_clear_drvdata; 1776 goto err_clear_drvdata;
1777   1777  
1778 return 0; 1778 return 0;
1779   1779  
1780 err_clear_drvdata: 1780 err_clear_drvdata:
1781 platform_set_drvdata(pdev, NULL); 1781 platform_set_drvdata(pdev, NULL);
1782 rtl8366_smi_cleanup(smi); 1782 rtl8366_smi_cleanup(smi);
1783 err_free_smi: 1783 err_free_smi:
1784 kfree(smi); 1784 kfree(smi);
1785 return err; 1785 return err;
1786 } 1786 }
1787   1787  
1788 static int rtl8367_remove(struct platform_device *pdev) 1788 static int rtl8367_remove(struct platform_device *pdev)
1789 { 1789 {
1790 struct rtl8366_smi *smi = platform_get_drvdata(pdev); 1790 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1791   1791  
1792 if (smi) { 1792 if (smi) {
1793 rtl8367_switch_cleanup(smi); 1793 rtl8367_switch_cleanup(smi);
1794 platform_set_drvdata(pdev, NULL); 1794 platform_set_drvdata(pdev, NULL);
1795 rtl8366_smi_cleanup(smi); 1795 rtl8366_smi_cleanup(smi);
1796 kfree(smi); 1796 kfree(smi);
1797 } 1797 }
1798   1798  
1799 return 0; 1799 return 0;
1800 } 1800 }
1801   1801  
1802 static void rtl8367_shutdown(struct platform_device *pdev) 1802 static void rtl8367_shutdown(struct platform_device *pdev)
1803 { 1803 {
1804 struct rtl8366_smi *smi = platform_get_drvdata(pdev); 1804 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1805   1805  
1806 if (smi) 1806 if (smi)
1807 rtl8367_reset_chip(smi); 1807 rtl8367_reset_chip(smi);
1808 } 1808 }
1809   1809  
1810 #ifdef CONFIG_OF 1810 #ifdef CONFIG_OF
1811 static const struct of_device_id rtl8367_match[] = { 1811 static const struct of_device_id rtl8367_match[] = {
1812 { .compatible = "realtek,rtl8367" }, 1812 { .compatible = "realtek,rtl8367" },
1813 {}, 1813 {},
1814 }; 1814 };
1815 MODULE_DEVICE_TABLE(of, rtl8367_match); 1815 MODULE_DEVICE_TABLE(of, rtl8367_match);
1816 #endif 1816 #endif
1817   1817  
1818 static struct platform_driver rtl8367_driver = { 1818 static struct platform_driver rtl8367_driver = {
1819 .driver = { 1819 .driver = {
1820 .name = RTL8367_DRIVER_NAME, 1820 .name = RTL8367_DRIVER_NAME,
1821 .owner = THIS_MODULE, 1821 .owner = THIS_MODULE,
1822 #ifdef CONFIG_OF 1822 #ifdef CONFIG_OF
1823 .of_match_table = of_match_ptr(rtl8367_match), 1823 .of_match_table = of_match_ptr(rtl8367_match),
1824 #endif 1824 #endif
1825 }, 1825 },
1826 .probe = rtl8367_probe, 1826 .probe = rtl8367_probe,
1827 .remove = rtl8367_remove, 1827 .remove = rtl8367_remove,
1828 .shutdown = rtl8367_shutdown, 1828 .shutdown = rtl8367_shutdown,
1829 }; 1829 };
1830   1830  
1831 static int __init rtl8367_module_init(void) 1831 static int __init rtl8367_module_init(void)
1832 { 1832 {
1833 return platform_driver_register(&rtl8367_driver); 1833 return platform_driver_register(&rtl8367_driver);
1834 } 1834 }
1835 module_init(rtl8367_module_init); 1835 module_init(rtl8367_module_init);
1836   1836  
1837 static void __exit rtl8367_module_exit(void) 1837 static void __exit rtl8367_module_exit(void)
1838 { 1838 {
1839 platform_driver_unregister(&rtl8367_driver); 1839 platform_driver_unregister(&rtl8367_driver);
1840 } 1840 }
1841 module_exit(rtl8367_module_exit); 1841 module_exit(rtl8367_module_exit);
1842   1842  
1843 MODULE_DESCRIPTION("Realtek RTL8367 ethernet switch driver"); 1843 MODULE_DESCRIPTION("Realtek RTL8367 ethernet switch driver");
1844 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); 1844 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1845 MODULE_LICENSE("GPL v2"); 1845 MODULE_LICENSE("GPL v2");
1846 MODULE_ALIAS("platform:" RTL8367_DRIVER_NAME); 1846 MODULE_ALIAS("platform:" RTL8367_DRIVER_NAME);
1847   1847