OpenWrt – Diff between revs 2 and 3
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1 | /* |
1 | /* |
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2 | * Platform driver for the Realtek RTL8366S ethernet switch |
2 | * Platform driver for the Realtek RTL8366S ethernet switch |
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3 | * |
3 | * |
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4 | * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> |
4 | * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com> |
5 | * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com> |
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6 | * |
6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
9 | * by the Free Software Foundation. |
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10 | */ |
10 | */ |
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11 | |
11 | |
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12 | #include <linux/kernel.h> |
12 | #include <linux/kernel.h> |
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13 | #include <linux/module.h> |
13 | #include <linux/module.h> |
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14 | #include <linux/init.h> |
14 | #include <linux/init.h> |
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15 | #include <linux/device.h> |
15 | #include <linux/device.h> |
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16 | #include <linux/of.h> |
16 | #include <linux/of.h> |
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17 | #include <linux/of_platform.h> |
17 | #include <linux/of_platform.h> |
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18 | #include <linux/delay.h> |
18 | #include <linux/delay.h> |
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19 | #include <linux/skbuff.h> |
19 | #include <linux/skbuff.h> |
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20 | #include <linux/rtl8366.h> |
20 | #include <linux/rtl8366.h> |
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21 | |
21 | |
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22 | #include "rtl8366_smi.h" |
22 | #include "rtl8366_smi.h" |
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23 | |
23 | |
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24 | #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver" |
24 | #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver" |
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25 | #define RTL8366S_DRIVER_VER "0.2.2" |
25 | #define RTL8366S_DRIVER_VER "0.2.2" |
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26 | |
26 | |
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27 | #define RTL8366S_PHY_NO_MAX 4 |
27 | #define RTL8366S_PHY_NO_MAX 4 |
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28 | #define RTL8366S_PHY_PAGE_MAX 7 |
28 | #define RTL8366S_PHY_PAGE_MAX 7 |
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29 | #define RTL8366S_PHY_ADDR_MAX 31 |
29 | #define RTL8366S_PHY_ADDR_MAX 31 |
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30 | |
30 | |
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31 | /* Switch Global Configuration register */ |
31 | /* Switch Global Configuration register */ |
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32 | #define RTL8366S_SGCR 0x0000 |
32 | #define RTL8366S_SGCR 0x0000 |
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33 | #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0) |
33 | #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0) |
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34 | #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4) |
34 | #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4) |
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35 | #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3) |
35 | #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3) |
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36 | #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0) |
36 | #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0) |
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37 | #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1) |
37 | #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1) |
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38 | #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2) |
38 | #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2) |
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39 | #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3) |
39 | #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3) |
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40 | #define RTL8366S_SGCR_EN_VLAN BIT(13) |
40 | #define RTL8366S_SGCR_EN_VLAN BIT(13) |
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41 | |
41 | |
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42 | /* Port Enable Control register */ |
42 | /* Port Enable Control register */ |
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43 | #define RTL8366S_PECR 0x0001 |
43 | #define RTL8366S_PECR 0x0001 |
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44 | |
44 | |
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45 | /* Green Ethernet Feature (based on GPL_BELKIN_F5D8235-4_v1000 v1.01.24) */ |
45 | /* Green Ethernet Feature (based on GPL_BELKIN_F5D8235-4_v1000 v1.01.24) */ |
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46 | #define RTL8366S_GREEN_ETHERNET_CTRL_REG 0x000a |
46 | #define RTL8366S_GREEN_ETHERNET_CTRL_REG 0x000a |
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47 | #define RTL8366S_GREEN_ETHERNET_CTRL_MASK 0x0018 |
47 | #define RTL8366S_GREEN_ETHERNET_CTRL_MASK 0x0018 |
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48 | #define RTL8366S_GREEN_ETHERNET_TX_BIT (1 << 3) |
48 | #define RTL8366S_GREEN_ETHERNET_TX_BIT (1 << 3) |
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49 | #define RTL8366S_GREEN_ETHERNET_RX_BIT (1 << 4) |
49 | #define RTL8366S_GREEN_ETHERNET_RX_BIT (1 << 4) |
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50 | |
50 | |
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51 | /* Switch Security Control registers */ |
51 | /* Switch Security Control registers */ |
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52 | #define RTL8366S_SSCR0 0x0002 |
52 | #define RTL8366S_SSCR0 0x0002 |
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53 | #define RTL8366S_SSCR1 0x0003 |
53 | #define RTL8366S_SSCR1 0x0003 |
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54 | #define RTL8366S_SSCR2 0x0004 |
54 | #define RTL8366S_SSCR2 0x0004 |
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55 | #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0) |
55 | #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0) |
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56 | |
56 | |
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57 | #define RTL8366S_RESET_CTRL_REG 0x0100 |
57 | #define RTL8366S_RESET_CTRL_REG 0x0100 |
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58 | #define RTL8366S_CHIP_CTRL_RESET_HW 1 |
58 | #define RTL8366S_CHIP_CTRL_RESET_HW 1 |
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59 | #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1) |
59 | #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1) |
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60 | |
60 | |
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61 | #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104 |
61 | #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104 |
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62 | #define RTL8366S_CHIP_VERSION_MASK 0xf |
62 | #define RTL8366S_CHIP_VERSION_MASK 0xf |
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63 | #define RTL8366S_CHIP_ID_REG 0x0105 |
63 | #define RTL8366S_CHIP_ID_REG 0x0105 |
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64 | #define RTL8366S_CHIP_ID_8366 0x8366 |
64 | #define RTL8366S_CHIP_ID_8366 0x8366 |
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65 | |
65 | |
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66 | /* PHY registers control */ |
66 | /* PHY registers control */ |
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67 | #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028 |
67 | #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028 |
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68 | #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029 |
68 | #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029 |
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69 | |
69 | |
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70 | #define RTL8366S_PHY_CTRL_READ 1 |
70 | #define RTL8366S_PHY_CTRL_READ 1 |
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71 | #define RTL8366S_PHY_CTRL_WRITE 0 |
71 | #define RTL8366S_PHY_CTRL_WRITE 0 |
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72 | |
72 | |
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73 | #define RTL8366S_PHY_REG_MASK 0x1f |
73 | #define RTL8366S_PHY_REG_MASK 0x1f |
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74 | #define RTL8366S_PHY_PAGE_OFFSET 5 |
74 | #define RTL8366S_PHY_PAGE_OFFSET 5 |
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75 | #define RTL8366S_PHY_PAGE_MASK (0x7 << 5) |
75 | #define RTL8366S_PHY_PAGE_MASK (0x7 << 5) |
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76 | #define RTL8366S_PHY_NO_OFFSET 9 |
76 | #define RTL8366S_PHY_NO_OFFSET 9 |
|
77 | #define RTL8366S_PHY_NO_MASK (0x1f << 9) |
77 | #define RTL8366S_PHY_NO_MASK (0x1f << 9) |
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78 | |
78 | |
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79 | /* Green Ethernet Feature for PHY ports */ |
79 | /* Green Ethernet Feature for PHY ports */ |
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80 | #define RTL8366S_PHY_POWER_SAVING_CTRL_REG 12 |
80 | #define RTL8366S_PHY_POWER_SAVING_CTRL_REG 12 |
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81 | #define RTL8366S_PHY_POWER_SAVING_MASK 0x1000 |
81 | #define RTL8366S_PHY_POWER_SAVING_MASK 0x1000 |
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82 | |
82 | |
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83 | /* LED control registers */ |
83 | /* LED control registers */ |
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84 | #define RTL8366S_LED_BLINKRATE_REG 0x0420 |
84 | #define RTL8366S_LED_BLINKRATE_REG 0x0420 |
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85 | #define RTL8366S_LED_BLINKRATE_BIT 0 |
85 | #define RTL8366S_LED_BLINKRATE_BIT 0 |
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86 | #define RTL8366S_LED_BLINKRATE_MASK 0x0007 |
86 | #define RTL8366S_LED_BLINKRATE_MASK 0x0007 |
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87 | |
87 | |
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88 | #define RTL8366S_LED_CTRL_REG 0x0421 |
88 | #define RTL8366S_LED_CTRL_REG 0x0421 |
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89 | #define RTL8366S_LED_0_1_CTRL_REG 0x0422 |
89 | #define RTL8366S_LED_0_1_CTRL_REG 0x0422 |
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90 | #define RTL8366S_LED_2_3_CTRL_REG 0x0423 |
90 | #define RTL8366S_LED_2_3_CTRL_REG 0x0423 |
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91 | |
91 | |
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92 | #define RTL8366S_MIB_COUNT 33 |
92 | #define RTL8366S_MIB_COUNT 33 |
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93 | #define RTL8366S_GLOBAL_MIB_COUNT 1 |
93 | #define RTL8366S_GLOBAL_MIB_COUNT 1 |
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94 | #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040 |
94 | #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040 |
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95 | #define RTL8366S_MIB_COUNTER_BASE 0x1000 |
95 | #define RTL8366S_MIB_COUNTER_BASE 0x1000 |
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96 | #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008 |
96 | #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008 |
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97 | #define RTL8366S_MIB_COUNTER_BASE2 0x1180 |
97 | #define RTL8366S_MIB_COUNTER_BASE2 0x1180 |
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98 | #define RTL8366S_MIB_CTRL_REG 0x11F0 |
98 | #define RTL8366S_MIB_CTRL_REG 0x11F0 |
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99 | #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF |
99 | #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF |
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100 | #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001 |
100 | #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001 |
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101 | #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002 |
101 | #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002 |
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102 | |
102 | |
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103 | #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004 |
103 | #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004 |
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104 | #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003 |
104 | #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003 |
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105 | #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC |
105 | #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC |
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106 | |
106 | |
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107 | |
107 | |
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108 | #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058 |
108 | #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058 |
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109 | #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \ |
109 | #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \ |
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110 | (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4) |
110 | (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4) |
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111 | #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf |
111 | #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf |
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112 | #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) |
112 | #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) |
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113 | |
113 | |
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114 | |
114 | |
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115 | #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B |
115 | #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B |
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116 | #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185 |
116 | #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185 |
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117 | |
117 | |
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118 | #define RTL8366S_VLAN_TB_CTRL_REG 0x010F |
118 | #define RTL8366S_VLAN_TB_CTRL_REG 0x010F |
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119 | |
119 | |
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120 | #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180 |
120 | #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180 |
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121 | #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01 |
121 | #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01 |
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122 | #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01 |
122 | #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01 |
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123 | |
123 | |
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124 | #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2) |
124 | #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2) |
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125 | |
125 | |
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126 | #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379 |
126 | #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379 |
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127 | |
127 | |
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128 | #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060 |
128 | #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060 |
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129 | #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003 |
129 | #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003 |
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130 | #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004 |
130 | #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004 |
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131 | #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010 |
131 | #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010 |
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132 | #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020 |
132 | #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020 |
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133 | #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040 |
133 | #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040 |
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134 | #define RTL8366S_PORT_STATUS_AN_MASK 0x0080 |
134 | #define RTL8366S_PORT_STATUS_AN_MASK 0x0080 |
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135 | |
135 | |
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136 | |
136 | |
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137 | #define RTL8366S_PORT_NUM_CPU 5 |
137 | #define RTL8366S_PORT_NUM_CPU 5 |
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138 | #define RTL8366S_NUM_PORTS 6 |
138 | #define RTL8366S_NUM_PORTS 6 |
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139 | #define RTL8366S_NUM_VLANS 16 |
139 | #define RTL8366S_NUM_VLANS 16 |
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140 | #define RTL8366S_NUM_LEDGROUPS 4 |
140 | #define RTL8366S_NUM_LEDGROUPS 4 |
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141 | #define RTL8366S_NUM_VIDS 4096 |
141 | #define RTL8366S_NUM_VIDS 4096 |
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142 | #define RTL8366S_PRIORITYMAX 7 |
142 | #define RTL8366S_PRIORITYMAX 7 |
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143 | #define RTL8366S_FIDMAX 7 |
143 | #define RTL8366S_FIDMAX 7 |
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144 | |
144 | |
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145 | |
145 | |
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146 | #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */ |
146 | #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */ |
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147 | #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */ |
147 | #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */ |
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148 | #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */ |
148 | #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */ |
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149 | #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */ |
149 | #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */ |
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150 | |
150 | |
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151 | #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */ |
151 | #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */ |
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152 | #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */ |
152 | #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */ |
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153 | |
153 | |
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154 | #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \ |
154 | #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \ |
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155 | RTL8366S_PORT_2 | \ |
155 | RTL8366S_PORT_2 | \ |
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156 | RTL8366S_PORT_3 | \ |
156 | RTL8366S_PORT_3 | \ |
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157 | RTL8366S_PORT_4 | \ |
157 | RTL8366S_PORT_4 | \ |
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158 | RTL8366S_PORT_UNKNOWN | \ |
158 | RTL8366S_PORT_UNKNOWN | \ |
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159 | RTL8366S_PORT_CPU) |
159 | RTL8366S_PORT_CPU) |
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160 | |
160 | |
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161 | #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \ |
161 | #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \ |
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162 | RTL8366S_PORT_2 | \ |
162 | RTL8366S_PORT_2 | \ |
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163 | RTL8366S_PORT_3 | \ |
163 | RTL8366S_PORT_3 | \ |
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164 | RTL8366S_PORT_4 | \ |
164 | RTL8366S_PORT_4 | \ |
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165 | RTL8366S_PORT_UNKNOWN) |
165 | RTL8366S_PORT_UNKNOWN) |
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166 | |
166 | |
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167 | #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \ |
167 | #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \ |
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168 | RTL8366S_PORT_2 | \ |
168 | RTL8366S_PORT_2 | \ |
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169 | RTL8366S_PORT_3 | \ |
169 | RTL8366S_PORT_3 | \ |
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170 | RTL8366S_PORT_4) |
170 | RTL8366S_PORT_4) |
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171 | |
171 | |
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172 | #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \ |
172 | #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \ |
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173 | RTL8366S_PORT_CPU) |
173 | RTL8366S_PORT_CPU) |
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174 | |
174 | |
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175 | #define RTL8366S_VLAN_VID_MASK 0xfff |
175 | #define RTL8366S_VLAN_VID_MASK 0xfff |
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176 | #define RTL8366S_VLAN_PRIORITY_SHIFT 12 |
176 | #define RTL8366S_VLAN_PRIORITY_SHIFT 12 |
|
177 | #define RTL8366S_VLAN_PRIORITY_MASK 0x7 |
177 | #define RTL8366S_VLAN_PRIORITY_MASK 0x7 |
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178 | #define RTL8366S_VLAN_MEMBER_MASK 0x3f |
178 | #define RTL8366S_VLAN_MEMBER_MASK 0x3f |
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179 | #define RTL8366S_VLAN_UNTAG_SHIFT 6 |
179 | #define RTL8366S_VLAN_UNTAG_SHIFT 6 |
|
180 | #define RTL8366S_VLAN_UNTAG_MASK 0x3f |
180 | #define RTL8366S_VLAN_UNTAG_MASK 0x3f |
|
181 | #define RTL8366S_VLAN_FID_SHIFT 12 |
181 | #define RTL8366S_VLAN_FID_SHIFT 12 |
|
182 | #define RTL8366S_VLAN_FID_MASK 0x7 |
182 | #define RTL8366S_VLAN_FID_MASK 0x7 |
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183 | |
183 | |
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184 | #define RTL8366S_MIB_RXB_ID 0 /* IfInOctets */ |
184 | #define RTL8366S_MIB_RXB_ID 0 /* IfInOctets */ |
|
185 | #define RTL8366S_MIB_TXB_ID 20 /* IfOutOctets */ |
185 | #define RTL8366S_MIB_TXB_ID 20 /* IfOutOctets */ |
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186 | |
186 | |
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187 | static struct rtl8366_mib_counter rtl8366s_mib_counters[] = { |
187 | static struct rtl8366_mib_counter rtl8366s_mib_counters[] = { |
|
188 | { 0, 0, 4, "IfInOctets" }, |
188 | { 0, 0, 4, "IfInOctets" }, |
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189 | { 0, 4, 4, "EtherStatsOctets" }, |
189 | { 0, 4, 4, "EtherStatsOctets" }, |
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190 | { 0, 8, 2, "EtherStatsUnderSizePkts" }, |
190 | { 0, 8, 2, "EtherStatsUnderSizePkts" }, |
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191 | { 0, 10, 2, "EtherFragments" }, |
191 | { 0, 10, 2, "EtherFragments" }, |
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192 | { 0, 12, 2, "EtherStatsPkts64Octets" }, |
192 | { 0, 12, 2, "EtherStatsPkts64Octets" }, |
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193 | { 0, 14, 2, "EtherStatsPkts65to127Octets" }, |
193 | { 0, 14, 2, "EtherStatsPkts65to127Octets" }, |
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194 | { 0, 16, 2, "EtherStatsPkts128to255Octets" }, |
194 | { 0, 16, 2, "EtherStatsPkts128to255Octets" }, |
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195 | { 0, 18, 2, "EtherStatsPkts256to511Octets" }, |
195 | { 0, 18, 2, "EtherStatsPkts256to511Octets" }, |
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196 | { 0, 20, 2, "EtherStatsPkts512to1023Octets" }, |
196 | { 0, 20, 2, "EtherStatsPkts512to1023Octets" }, |
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197 | { 0, 22, 2, "EtherStatsPkts1024to1518Octets" }, |
197 | { 0, 22, 2, "EtherStatsPkts1024to1518Octets" }, |
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198 | { 0, 24, 2, "EtherOversizeStats" }, |
198 | { 0, 24, 2, "EtherOversizeStats" }, |
|
199 | { 0, 26, 2, "EtherStatsJabbers" }, |
199 | { 0, 26, 2, "EtherStatsJabbers" }, |
|
200 | { 0, 28, 2, "IfInUcastPkts" }, |
200 | { 0, 28, 2, "IfInUcastPkts" }, |
|
201 | { 0, 30, 2, "EtherStatsMulticastPkts" }, |
201 | { 0, 30, 2, "EtherStatsMulticastPkts" }, |
|
202 | { 0, 32, 2, "EtherStatsBroadcastPkts" }, |
202 | { 0, 32, 2, "EtherStatsBroadcastPkts" }, |
|
203 | { 0, 34, 2, "EtherStatsDropEvents" }, |
203 | { 0, 34, 2, "EtherStatsDropEvents" }, |
|
204 | { 0, 36, 2, "Dot3StatsFCSErrors" }, |
204 | { 0, 36, 2, "Dot3StatsFCSErrors" }, |
|
205 | { 0, 38, 2, "Dot3StatsSymbolErrors" }, |
205 | { 0, 38, 2, "Dot3StatsSymbolErrors" }, |
|
206 | { 0, 40, 2, "Dot3InPauseFrames" }, |
206 | { 0, 40, 2, "Dot3InPauseFrames" }, |
|
207 | { 0, 42, 2, "Dot3ControlInUnknownOpcodes" }, |
207 | { 0, 42, 2, "Dot3ControlInUnknownOpcodes" }, |
|
208 | { 0, 44, 4, "IfOutOctets" }, |
208 | { 0, 44, 4, "IfOutOctets" }, |
|
209 | { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, |
209 | { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, |
|
210 | { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, |
210 | { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, |
|
211 | { 0, 52, 2, "Dot3sDeferredTransmissions" }, |
211 | { 0, 52, 2, "Dot3sDeferredTransmissions" }, |
|
212 | { 0, 54, 2, "Dot3StatsLateCollisions" }, |
212 | { 0, 54, 2, "Dot3StatsLateCollisions" }, |
|
213 | { 0, 56, 2, "EtherStatsCollisions" }, |
213 | { 0, 56, 2, "EtherStatsCollisions" }, |
|
214 | { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, |
214 | { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, |
|
215 | { 0, 60, 2, "Dot3OutPauseFrames" }, |
215 | { 0, 60, 2, "Dot3OutPauseFrames" }, |
|
216 | { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, |
216 | { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, |
|
217 | |
217 | |
|
218 | /* |
218 | /* |
|
219 | * The following counters are accessible at a different |
219 | * The following counters are accessible at a different |
|
220 | * base address. |
220 | * base address. |
|
221 | */ |
221 | */ |
|
222 | { 1, 0, 2, "Dot1dTpPortInDiscards" }, |
222 | { 1, 0, 2, "Dot1dTpPortInDiscards" }, |
|
223 | { 1, 2, 2, "IfOutUcastPkts" }, |
223 | { 1, 2, 2, "IfOutUcastPkts" }, |
|
224 | { 1, 4, 2, "IfOutMulticastPkts" }, |
224 | { 1, 4, 2, "IfOutMulticastPkts" }, |
|
225 | { 1, 6, 2, "IfOutBroadcastPkts" }, |
225 | { 1, 6, 2, "IfOutBroadcastPkts" }, |
|
226 | }; |
226 | }; |
|
227 | |
227 | |
|
228 | #define REG_WR(_smi, _reg, _val) \ |
228 | #define REG_WR(_smi, _reg, _val) \ |
|
229 | do { \ |
229 | do { \ |
|
230 | err = rtl8366_smi_write_reg(_smi, _reg, _val); \ |
230 | err = rtl8366_smi_write_reg(_smi, _reg, _val); \ |
|
231 | if (err) \ |
231 | if (err) \ |
|
232 | return err; \ |
232 | return err; \ |
|
233 | } while (0) |
233 | } while (0) |
|
234 | |
234 | |
|
235 | #define REG_RMW(_smi, _reg, _mask, _val) \ |
235 | #define REG_RMW(_smi, _reg, _mask, _val) \ |
|
236 | do { \ |
236 | do { \ |
|
237 | err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ |
237 | err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \ |
|
238 | if (err) \ |
238 | if (err) \ |
|
239 | return err; \ |
239 | return err; \ |
|
240 | } while (0) |
240 | } while (0) |
|
241 | |
241 | |
|
242 | static int rtl8366s_reset_chip(struct rtl8366_smi *smi) |
242 | static int rtl8366s_reset_chip(struct rtl8366_smi *smi) |
|
243 | { |
243 | { |
|
244 | int timeout = 10; |
244 | int timeout = 10; |
|
245 | u32 data; |
245 | u32 data; |
|
246 | |
246 | |
|
247 | rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG, |
247 | rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG, |
|
248 | RTL8366S_CHIP_CTRL_RESET_HW); |
248 | RTL8366S_CHIP_CTRL_RESET_HW); |
|
249 | do { |
249 | do { |
|
250 | msleep(1); |
250 | msleep(1); |
|
251 | if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data)) |
251 | if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data)) |
|
252 | return -EIO; |
252 | return -EIO; |
|
253 | |
253 | |
|
254 | if (!(data & RTL8366S_CHIP_CTRL_RESET_HW)) |
254 | if (!(data & RTL8366S_CHIP_CTRL_RESET_HW)) |
|
255 | break; |
255 | break; |
|
256 | } while (--timeout); |
256 | } while (--timeout); |
|
257 | |
257 | |
|
258 | if (!timeout) { |
258 | if (!timeout) { |
|
259 | printk("Timeout waiting for the switch to reset\n"); |
259 | printk("Timeout waiting for the switch to reset\n"); |
|
260 | return -EIO; |
260 | return -EIO; |
|
261 | } |
261 | } |
|
262 | |
262 | |
|
263 | return 0; |
263 | return 0; |
|
264 | } |
264 | } |
|
265 | |
265 | |
|
266 | static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi, |
266 | static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi, |
|
267 | u32 phy_no, u32 page, u32 addr, u32 *data) |
267 | u32 phy_no, u32 page, u32 addr, u32 *data) |
|
268 | { |
268 | { |
|
269 | u32 reg; |
269 | u32 reg; |
|
270 | int ret; |
270 | int ret; |
|
271 | |
271 | |
|
272 | if (phy_no > RTL8366S_PHY_NO_MAX) |
272 | if (phy_no > RTL8366S_PHY_NO_MAX) |
|
273 | return -EINVAL; |
273 | return -EINVAL; |
|
274 | |
274 | |
|
275 | if (page > RTL8366S_PHY_PAGE_MAX) |
275 | if (page > RTL8366S_PHY_PAGE_MAX) |
|
276 | return -EINVAL; |
276 | return -EINVAL; |
|
277 | |
277 | |
|
278 | if (addr > RTL8366S_PHY_ADDR_MAX) |
278 | if (addr > RTL8366S_PHY_ADDR_MAX) |
|
279 | return -EINVAL; |
279 | return -EINVAL; |
|
280 | |
280 | |
|
281 | ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
281 | ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
|
282 | RTL8366S_PHY_CTRL_READ); |
282 | RTL8366S_PHY_CTRL_READ); |
|
283 | if (ret) |
283 | if (ret) |
|
284 | return ret; |
284 | return ret; |
|
285 | |
285 | |
|
286 | reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
286 | reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
|
287 | ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
287 | ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
|
288 | (addr & RTL8366S_PHY_REG_MASK); |
288 | (addr & RTL8366S_PHY_REG_MASK); |
|
289 | |
289 | |
|
290 | ret = rtl8366_smi_write_reg(smi, reg, 0); |
290 | ret = rtl8366_smi_write_reg(smi, reg, 0); |
|
291 | if (ret) |
291 | if (ret) |
|
292 | return ret; |
292 | return ret; |
|
293 | |
293 | |
|
294 | ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data); |
294 | ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data); |
|
295 | if (ret) |
295 | if (ret) |
|
296 | return ret; |
296 | return ret; |
|
297 | |
297 | |
|
298 | return 0; |
298 | return 0; |
|
299 | } |
299 | } |
|
300 | |
300 | |
|
301 | static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi, |
301 | static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi, |
|
302 | u32 phy_no, u32 page, u32 addr, u32 data) |
302 | u32 phy_no, u32 page, u32 addr, u32 data) |
|
303 | { |
303 | { |
|
304 | u32 reg; |
304 | u32 reg; |
|
305 | int ret; |
305 | int ret; |
|
306 | |
306 | |
|
307 | if (phy_no > RTL8366S_PHY_NO_MAX) |
307 | if (phy_no > RTL8366S_PHY_NO_MAX) |
|
308 | return -EINVAL; |
308 | return -EINVAL; |
|
309 | |
309 | |
|
310 | if (page > RTL8366S_PHY_PAGE_MAX) |
310 | if (page > RTL8366S_PHY_PAGE_MAX) |
|
311 | return -EINVAL; |
311 | return -EINVAL; |
|
312 | |
312 | |
|
313 | if (addr > RTL8366S_PHY_ADDR_MAX) |
313 | if (addr > RTL8366S_PHY_ADDR_MAX) |
|
314 | return -EINVAL; |
314 | return -EINVAL; |
|
315 | |
315 | |
|
316 | ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
316 | ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG, |
|
317 | RTL8366S_PHY_CTRL_WRITE); |
317 | RTL8366S_PHY_CTRL_WRITE); |
|
318 | if (ret) |
318 | if (ret) |
|
319 | return ret; |
319 | return ret; |
|
320 | |
320 | |
|
321 | reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
321 | reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) | |
|
322 | ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
322 | ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) | |
|
323 | (addr & RTL8366S_PHY_REG_MASK); |
323 | (addr & RTL8366S_PHY_REG_MASK); |
|
324 | |
324 | |
|
325 | ret = rtl8366_smi_write_reg(smi, reg, data); |
325 | ret = rtl8366_smi_write_reg(smi, reg, data); |
|
326 | if (ret) |
326 | if (ret) |
|
327 | return ret; |
327 | return ret; |
|
328 | |
328 | |
|
329 | return 0; |
329 | return 0; |
|
330 | } |
330 | } |
|
331 | |
331 | |
|
332 | static int rtl8366s_set_green_port(struct rtl8366_smi *smi, int port, int enable) |
332 | static int rtl8366s_set_green_port(struct rtl8366_smi *smi, int port, int enable) |
|
333 | { |
333 | { |
|
334 | int err; |
334 | int err; |
|
335 | u32 phyData; |
335 | u32 phyData; |
|
336 | |
336 | |
|
337 | if (port >= RTL8366S_NUM_PORTS) |
337 | if (port >= RTL8366S_NUM_PORTS) |
|
338 | return -EINVAL; |
338 | return -EINVAL; |
|
339 | |
339 | |
|
340 | err = rtl8366s_read_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData); |
340 | err = rtl8366s_read_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData); |
|
341 | if (err) |
341 | if (err) |
|
342 | return err; |
342 | return err; |
|
343 | |
343 | |
|
344 | if (enable) |
344 | if (enable) |
|
345 | phyData |= RTL8366S_PHY_POWER_SAVING_MASK; |
345 | phyData |= RTL8366S_PHY_POWER_SAVING_MASK; |
|
346 | else |
346 | else |
|
347 | phyData &= ~RTL8366S_PHY_POWER_SAVING_MASK; |
347 | phyData &= ~RTL8366S_PHY_POWER_SAVING_MASK; |
|
348 | |
348 | |
|
349 | err = rtl8366s_write_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, phyData); |
349 | err = rtl8366s_write_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, phyData); |
|
350 | if (err) |
350 | if (err) |
|
351 | return err; |
351 | return err; |
|
352 | |
352 | |
|
353 | return 0; |
353 | return 0; |
|
354 | } |
354 | } |
|
355 | |
355 | |
|
356 | static int rtl8366s_set_green(struct rtl8366_smi *smi, int enable) |
356 | static int rtl8366s_set_green(struct rtl8366_smi *smi, int enable) |
|
357 | { |
357 | { |
|
358 | int err; |
358 | int err; |
|
359 | unsigned i; |
359 | unsigned i; |
|
360 | u32 data = 0; |
360 | u32 data = 0; |
|
361 | |
361 | |
|
362 | if (!enable) { |
362 | if (!enable) { |
|
363 | for (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) { |
363 | for (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) { |
|
364 | rtl8366s_set_green_port(smi, i, 0); |
364 | rtl8366s_set_green_port(smi, i, 0); |
|
365 | } |
365 | } |
|
366 | } |
366 | } |
|
367 | |
367 | |
|
368 | if (enable) |
368 | if (enable) |
|
369 | data = (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT); |
369 | data = (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT); |
|
370 | |
370 | |
|
371 | REG_RMW(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, RTL8366S_GREEN_ETHERNET_CTRL_MASK, data); |
371 | REG_RMW(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, RTL8366S_GREEN_ETHERNET_CTRL_MASK, data); |
|
372 | |
372 | |
|
373 | return 0; |
373 | return 0; |
|
374 | } |
374 | } |
|
375 | |
375 | |
|
376 | static int rtl8366s_setup(struct rtl8366_smi *smi) |
376 | static int rtl8366s_setup(struct rtl8366_smi *smi) |
|
377 | { |
377 | { |
|
378 | struct rtl8366_platform_data *pdata; |
378 | struct rtl8366_platform_data *pdata; |
|
379 | int err; |
379 | int err; |
|
380 | unsigned i; |
380 | unsigned i; |
|
381 | #ifdef CONFIG_OF |
381 | #ifdef CONFIG_OF |
|
382 | struct device_node *np; |
382 | struct device_node *np; |
|
383 | unsigned num_initvals; |
383 | unsigned num_initvals; |
|
384 | const __be32 *paddr; |
384 | const __be32 *paddr; |
|
385 | #endif |
385 | #endif |
|
386 | |
386 | |
|
387 | pdata = smi->parent->platform_data; |
387 | pdata = smi->parent->platform_data; |
|
388 | if (pdata && pdata->num_initvals && pdata->initvals) { |
388 | if (pdata && pdata->num_initvals && pdata->initvals) { |
|
389 | dev_info(smi->parent, "applying initvals\n"); |
389 | dev_info(smi->parent, "applying initvals\n"); |
|
390 | for (i = 0; i < pdata->num_initvals; i++) |
390 | for (i = 0; i < pdata->num_initvals; i++) |
|
391 | REG_WR(smi, pdata->initvals[i].reg, |
391 | REG_WR(smi, pdata->initvals[i].reg, |
|
392 | pdata->initvals[i].val); |
392 | pdata->initvals[i].val); |
|
393 | } |
393 | } |
|
394 | |
394 | |
|
395 | #ifdef CONFIG_OF |
395 | #ifdef CONFIG_OF |
|
396 | np = smi->parent->of_node; |
396 | np = smi->parent->of_node; |
|
397 | |
397 | |
|
398 | paddr = of_get_property(np, "realtek,initvals", &num_initvals); |
398 | paddr = of_get_property(np, "realtek,initvals", &num_initvals); |
|
399 | if (paddr) { |
399 | if (paddr) { |
|
400 | dev_info(smi->parent, "applying initvals from DTS\n"); |
400 | dev_info(smi->parent, "applying initvals from DTS\n"); |
|
401 | |
401 | |
|
402 | if (num_initvals < (2 * sizeof(*paddr))) |
402 | if (num_initvals < (2 * sizeof(*paddr))) |
|
403 | return -EINVAL; |
403 | return -EINVAL; |
|
404 | |
404 | |
|
405 | num_initvals /= sizeof(*paddr); |
405 | num_initvals /= sizeof(*paddr); |
|
406 | |
406 | |
|
407 | for (i = 0; i < num_initvals - 1; i += 2) { |
407 | for (i = 0; i < num_initvals - 1; i += 2) { |
|
408 | u32 reg = be32_to_cpup(paddr + i); |
408 | u32 reg = be32_to_cpup(paddr + i); |
|
409 | u32 val = be32_to_cpup(paddr + i + 1); |
409 | u32 val = be32_to_cpup(paddr + i + 1); |
|
410 | |
410 | |
|
411 | REG_WR(smi, reg, val); |
411 | REG_WR(smi, reg, val); |
|
412 | } |
412 | } |
|
413 | } |
413 | } |
|
414 | |
414 | |
|
415 | if (of_property_read_bool(np, "realtek,green-ethernet-features")) { |
415 | if (of_property_read_bool(np, "realtek,green-ethernet-features")) { |
|
416 | dev_info(smi->parent, "activating Green Ethernet features\n"); |
416 | dev_info(smi->parent, "activating Green Ethernet features\n"); |
|
417 | |
417 | |
|
418 | err = rtl8366s_set_green(smi, 1); |
418 | err = rtl8366s_set_green(smi, 1); |
|
419 | if (err) |
419 | if (err) |
|
420 | return err; |
420 | return err; |
|
421 | |
421 | |
|
422 | for (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) { |
422 | for (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) { |
|
423 | err = rtl8366s_set_green_port(smi, i, 1); |
423 | err = rtl8366s_set_green_port(smi, i, 1); |
|
424 | if (err) |
424 | if (err) |
|
425 | return err; |
425 | return err; |
|
426 | } |
426 | } |
|
427 | } |
427 | } |
|
428 | #endif |
428 | #endif |
|
429 | |
429 | |
|
430 | /* set maximum packet length to 1536 bytes */ |
430 | /* set maximum packet length to 1536 bytes */ |
|
431 | REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK, |
431 | REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK, |
|
432 | RTL8366S_SGCR_MAX_LENGTH_1536); |
432 | RTL8366S_SGCR_MAX_LENGTH_1536); |
|
433 | |
433 | |
|
434 | /* enable learning for all ports */ |
434 | /* enable learning for all ports */ |
|
435 | REG_WR(smi, RTL8366S_SSCR0, 0); |
435 | REG_WR(smi, RTL8366S_SSCR0, 0); |
|
436 | |
436 | |
|
437 | /* enable auto ageing for all ports */ |
437 | /* enable auto ageing for all ports */ |
|
438 | REG_WR(smi, RTL8366S_SSCR1, 0); |
438 | REG_WR(smi, RTL8366S_SSCR1, 0); |
|
439 | |
439 | |
|
440 | /* |
440 | /* |
|
441 | * discard VLAN tagged packets if the port is not a member of |
441 | * discard VLAN tagged packets if the port is not a member of |
|
442 | * the VLAN with which the packets is associated. |
442 | * the VLAN with which the packets is associated. |
|
443 | */ |
443 | */ |
|
444 | REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL); |
444 | REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL); |
|
445 | |
445 | |
|
446 | /* don't drop packets whose DA has not been learned */ |
446 | /* don't drop packets whose DA has not been learned */ |
|
447 | REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0); |
447 | REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0); |
|
448 | |
448 | |
|
449 | return 0; |
449 | return 0; |
|
450 | } |
450 | } |
|
451 | |
451 | |
|
452 | static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter, |
452 | static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter, |
|
453 | int port, unsigned long long *val) |
453 | int port, unsigned long long *val) |
|
454 | { |
454 | { |
|
455 | int i; |
455 | int i; |
|
456 | int err; |
456 | int err; |
|
457 | u32 addr, data; |
457 | u32 addr, data; |
|
458 | u64 mibvalue; |
458 | u64 mibvalue; |
|
459 | |
459 | |
|
460 | if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT) |
460 | if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT) |
|
461 | return -EINVAL; |
461 | return -EINVAL; |
|
462 | |
462 | |
|
463 | switch (rtl8366s_mib_counters[counter].base) { |
463 | switch (rtl8366s_mib_counters[counter].base) { |
|
464 | case 0: |
464 | case 0: |
|
465 | addr = RTL8366S_MIB_COUNTER_BASE + |
465 | addr = RTL8366S_MIB_COUNTER_BASE + |
|
466 | RTL8366S_MIB_COUNTER_PORT_OFFSET * port; |
466 | RTL8366S_MIB_COUNTER_PORT_OFFSET * port; |
|
467 | break; |
467 | break; |
|
468 | |
468 | |
|
469 | case 1: |
469 | case 1: |
|
470 | addr = RTL8366S_MIB_COUNTER_BASE2 + |
470 | addr = RTL8366S_MIB_COUNTER_BASE2 + |
|
471 | RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port; |
471 | RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port; |
|
472 | break; |
472 | break; |
|
473 | |
473 | |
|
474 | default: |
474 | default: |
|
475 | return -EINVAL; |
475 | return -EINVAL; |
|
476 | } |
476 | } |
|
477 | |
477 | |
|
478 | addr += rtl8366s_mib_counters[counter].offset; |
478 | addr += rtl8366s_mib_counters[counter].offset; |
|
479 | |
479 | |
|
480 | /* |
480 | /* |
|
481 | * Writing access counter address first |
481 | * Writing access counter address first |
|
482 | * then ASIC will prepare 64bits counter wait for being retrived |
482 | * then ASIC will prepare 64bits counter wait for being retrived |
|
483 | */ |
483 | */ |
|
484 | data = 0; /* writing data will be discard by ASIC */ |
484 | data = 0; /* writing data will be discard by ASIC */ |
|
485 | err = rtl8366_smi_write_reg(smi, addr, data); |
485 | err = rtl8366_smi_write_reg(smi, addr, data); |
|
486 | if (err) |
486 | if (err) |
|
487 | return err; |
487 | return err; |
|
488 | |
488 | |
|
489 | /* read MIB control register */ |
489 | /* read MIB control register */ |
|
490 | err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data); |
490 | err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data); |
|
491 | if (err) |
491 | if (err) |
|
492 | return err; |
492 | return err; |
|
493 | |
493 | |
|
494 | if (data & RTL8366S_MIB_CTRL_BUSY_MASK) |
494 | if (data & RTL8366S_MIB_CTRL_BUSY_MASK) |
|
495 | return -EBUSY; |
495 | return -EBUSY; |
|
496 | |
496 | |
|
497 | if (data & RTL8366S_MIB_CTRL_RESET_MASK) |
497 | if (data & RTL8366S_MIB_CTRL_RESET_MASK) |
|
498 | return -EIO; |
498 | return -EIO; |
|
499 | |
499 | |
|
500 | mibvalue = 0; |
500 | mibvalue = 0; |
|
501 | for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) { |
501 | for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) { |
|
502 | err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data); |
502 | err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data); |
|
503 | if (err) |
503 | if (err) |
|
504 | return err; |
504 | return err; |
|
505 | |
505 | |
|
506 | mibvalue = (mibvalue << 16) | (data & 0xFFFF); |
506 | mibvalue = (mibvalue << 16) | (data & 0xFFFF); |
|
507 | } |
507 | } |
|
508 | |
508 | |
|
509 | *val = mibvalue; |
509 | *val = mibvalue; |
|
510 | return 0; |
510 | return 0; |
|
511 | } |
511 | } |
|
512 | |
512 | |
|
513 | static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, |
513 | static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid, |
|
514 | struct rtl8366_vlan_4k *vlan4k) |
514 | struct rtl8366_vlan_4k *vlan4k) |
|
515 | { |
515 | { |
|
516 | u32 data[2]; |
516 | u32 data[2]; |
|
517 | int err; |
517 | int err; |
|
518 | int i; |
518 | int i; |
|
519 | |
519 | |
|
520 | memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); |
520 | memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); |
|
521 | |
521 | |
|
522 | if (vid >= RTL8366S_NUM_VIDS) |
522 | if (vid >= RTL8366S_NUM_VIDS) |
|
523 | return -EINVAL; |
523 | return -EINVAL; |
|
524 | |
524 | |
|
525 | /* write VID */ |
525 | /* write VID */ |
|
526 | err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, |
526 | err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, |
|
527 | vid & RTL8366S_VLAN_VID_MASK); |
527 | vid & RTL8366S_VLAN_VID_MASK); |
|
528 | if (err) |
528 | if (err) |
|
529 | return err; |
529 | return err; |
|
530 | |
530 | |
|
531 | /* write table access control word */ |
531 | /* write table access control word */ |
|
532 | err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
532 | err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
|
533 | RTL8366S_TABLE_VLAN_READ_CTRL); |
533 | RTL8366S_TABLE_VLAN_READ_CTRL); |
|
534 | if (err) |
534 | if (err) |
|
535 | return err; |
535 | return err; |
|
536 | |
536 | |
|
537 | for (i = 0; i < 2; i++) { |
537 | for (i = 0; i < 2; i++) { |
|
538 | err = rtl8366_smi_read_reg(smi, |
538 | err = rtl8366_smi_read_reg(smi, |
|
539 | RTL8366S_VLAN_TABLE_READ_BASE + i, |
539 | RTL8366S_VLAN_TABLE_READ_BASE + i, |
|
540 | &data[i]); |
540 | &data[i]); |
|
541 | if (err) |
541 | if (err) |
|
542 | return err; |
542 | return err; |
|
543 | } |
543 | } |
|
544 | |
544 | |
|
545 | vlan4k->vid = vid; |
545 | vlan4k->vid = vid; |
|
546 | vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & |
546 | vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & |
|
547 | RTL8366S_VLAN_UNTAG_MASK; |
547 | RTL8366S_VLAN_UNTAG_MASK; |
|
548 | vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; |
548 | vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; |
|
549 | vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & |
549 | vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & |
|
550 | RTL8366S_VLAN_FID_MASK; |
550 | RTL8366S_VLAN_FID_MASK; |
|
551 | |
551 | |
|
552 | return 0; |
552 | return 0; |
|
553 | } |
553 | } |
|
554 | |
554 | |
|
555 | static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi, |
555 | static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi, |
|
556 | const struct rtl8366_vlan_4k *vlan4k) |
556 | const struct rtl8366_vlan_4k *vlan4k) |
|
557 | { |
557 | { |
|
558 | u32 data[2]; |
558 | u32 data[2]; |
|
559 | int err; |
559 | int err; |
|
560 | int i; |
560 | int i; |
|
561 | |
561 | |
|
562 | if (vlan4k->vid >= RTL8366S_NUM_VIDS || |
562 | if (vlan4k->vid >= RTL8366S_NUM_VIDS || |
|
563 | vlan4k->member > RTL8366S_VLAN_MEMBER_MASK || |
563 | vlan4k->member > RTL8366S_VLAN_MEMBER_MASK || |
|
564 | vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK || |
564 | vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK || |
|
565 | vlan4k->fid > RTL8366S_FIDMAX) |
565 | vlan4k->fid > RTL8366S_FIDMAX) |
|
566 | return -EINVAL; |
566 | return -EINVAL; |
|
567 | |
567 | |
|
568 | data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK; |
568 | data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK; |
|
569 | data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) | |
569 | data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) | |
|
570 | ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) << |
570 | ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) << |
|
571 | RTL8366S_VLAN_UNTAG_SHIFT) | |
571 | RTL8366S_VLAN_UNTAG_SHIFT) | |
|
572 | ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) << |
572 | ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) << |
|
573 | RTL8366S_VLAN_FID_SHIFT); |
573 | RTL8366S_VLAN_FID_SHIFT); |
|
574 | |
574 | |
|
575 | for (i = 0; i < 2; i++) { |
575 | for (i = 0; i < 2; i++) { |
|
576 | err = rtl8366_smi_write_reg(smi, |
576 | err = rtl8366_smi_write_reg(smi, |
|
577 | RTL8366S_VLAN_TABLE_WRITE_BASE + i, |
577 | RTL8366S_VLAN_TABLE_WRITE_BASE + i, |
|
578 | data[i]); |
578 | data[i]); |
|
579 | if (err) |
579 | if (err) |
|
580 | return err; |
580 | return err; |
|
581 | } |
581 | } |
|
582 | |
582 | |
|
583 | /* write table access control word */ |
583 | /* write table access control word */ |
|
584 | err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
584 | err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG, |
|
585 | RTL8366S_TABLE_VLAN_WRITE_CTRL); |
585 | RTL8366S_TABLE_VLAN_WRITE_CTRL); |
|
586 | |
586 | |
|
587 | return err; |
587 | return err; |
|
588 | } |
588 | } |
|
589 | |
589 | |
|
590 | static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index, |
590 | static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index, |
|
591 | struct rtl8366_vlan_mc *vlanmc) |
591 | struct rtl8366_vlan_mc *vlanmc) |
|
592 | { |
592 | { |
|
593 | u32 data[2]; |
593 | u32 data[2]; |
|
594 | int err; |
594 | int err; |
|
595 | int i; |
595 | int i; |
|
596 | |
596 | |
|
597 | memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); |
597 | memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); |
|
598 | |
598 | |
|
599 | if (index >= RTL8366S_NUM_VLANS) |
599 | if (index >= RTL8366S_NUM_VLANS) |
|
600 | return -EINVAL; |
600 | return -EINVAL; |
|
601 | |
601 | |
|
602 | for (i = 0; i < 2; i++) { |
602 | for (i = 0; i < 2; i++) { |
|
603 | err = rtl8366_smi_read_reg(smi, |
603 | err = rtl8366_smi_read_reg(smi, |
|
604 | RTL8366S_VLAN_MC_BASE(index) + i, |
604 | RTL8366S_VLAN_MC_BASE(index) + i, |
|
605 | &data[i]); |
605 | &data[i]); |
|
606 | if (err) |
606 | if (err) |
|
607 | return err; |
607 | return err; |
|
608 | } |
608 | } |
|
609 | |
609 | |
|
610 | vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK; |
610 | vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK; |
|
611 | vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) & |
611 | vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) & |
|
612 | RTL8366S_VLAN_PRIORITY_MASK; |
612 | RTL8366S_VLAN_PRIORITY_MASK; |
|
613 | vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & |
613 | vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) & |
|
614 | RTL8366S_VLAN_UNTAG_MASK; |
614 | RTL8366S_VLAN_UNTAG_MASK; |
|
615 | vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; |
615 | vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK; |
|
616 | vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & |
616 | vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) & |
|
617 | RTL8366S_VLAN_FID_MASK; |
617 | RTL8366S_VLAN_FID_MASK; |
|
618 | |
618 | |
|
619 | return 0; |
619 | return 0; |
|
620 | } |
620 | } |
|
621 | |
621 | |
|
622 | static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index, |
622 | static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index, |
|
623 | const struct rtl8366_vlan_mc *vlanmc) |
623 | const struct rtl8366_vlan_mc *vlanmc) |
|
624 | { |
624 | { |
|
625 | u32 data[2]; |
625 | u32 data[2]; |
|
626 | int err; |
626 | int err; |
|
627 | int i; |
627 | int i; |
|
628 | |
628 | |
|
629 | if (index >= RTL8366S_NUM_VLANS || |
629 | if (index >= RTL8366S_NUM_VLANS || |
|
630 | vlanmc->vid >= RTL8366S_NUM_VIDS || |
630 | vlanmc->vid >= RTL8366S_NUM_VIDS || |
|
631 | vlanmc->priority > RTL8366S_PRIORITYMAX || |
631 | vlanmc->priority > RTL8366S_PRIORITYMAX || |
|
632 | vlanmc->member > RTL8366S_VLAN_MEMBER_MASK || |
632 | vlanmc->member > RTL8366S_VLAN_MEMBER_MASK || |
|
633 | vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK || |
633 | vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK || |
|
634 | vlanmc->fid > RTL8366S_FIDMAX) |
634 | vlanmc->fid > RTL8366S_FIDMAX) |
|
635 | return -EINVAL; |
635 | return -EINVAL; |
|
636 | |
636 | |
|
637 | data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) | |
637 | data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) | |
|
638 | ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) << |
638 | ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) << |
|
639 | RTL8366S_VLAN_PRIORITY_SHIFT); |
639 | RTL8366S_VLAN_PRIORITY_SHIFT); |
|
640 | data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) | |
640 | data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) | |
|
641 | ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) << |
641 | ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) << |
|
642 | RTL8366S_VLAN_UNTAG_SHIFT) | |
642 | RTL8366S_VLAN_UNTAG_SHIFT) | |
|
643 | ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) << |
643 | ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) << |
|
644 | RTL8366S_VLAN_FID_SHIFT); |
644 | RTL8366S_VLAN_FID_SHIFT); |
|
645 | |
645 | |
|
646 | for (i = 0; i < 2; i++) { |
646 | for (i = 0; i < 2; i++) { |
|
647 | err = rtl8366_smi_write_reg(smi, |
647 | err = rtl8366_smi_write_reg(smi, |
|
648 | RTL8366S_VLAN_MC_BASE(index) + i, |
648 | RTL8366S_VLAN_MC_BASE(index) + i, |
|
649 | data[i]); |
649 | data[i]); |
|
650 | if (err) |
650 | if (err) |
|
651 | return err; |
651 | return err; |
|
652 | } |
652 | } |
|
653 | |
653 | |
|
654 | return 0; |
654 | return 0; |
|
655 | } |
655 | } |
|
656 | |
656 | |
|
657 | static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val) |
657 | static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val) |
|
658 | { |
658 | { |
|
659 | u32 data; |
659 | u32 data; |
|
660 | int err; |
660 | int err; |
|
661 | |
661 | |
|
662 | if (port >= RTL8366S_NUM_PORTS) |
662 | if (port >= RTL8366S_NUM_PORTS) |
|
663 | return -EINVAL; |
663 | return -EINVAL; |
|
664 | |
664 | |
|
665 | err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
665 | err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
|
666 | &data); |
666 | &data); |
|
667 | if (err) |
667 | if (err) |
|
668 | return err; |
668 | return err; |
|
669 | |
669 | |
|
670 | *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) & |
670 | *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) & |
|
671 | RTL8366S_PORT_VLAN_CTRL_MASK; |
671 | RTL8366S_PORT_VLAN_CTRL_MASK; |
|
672 | |
672 | |
|
673 | return 0; |
673 | return 0; |
|
674 | } |
674 | } |
|
675 | |
675 | |
|
676 | static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index) |
676 | static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index) |
|
677 | { |
677 | { |
|
678 | if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS) |
678 | if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS) |
|
679 | return -EINVAL; |
679 | return -EINVAL; |
|
680 | |
680 | |
|
681 | return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
681 | return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port), |
|
682 | RTL8366S_PORT_VLAN_CTRL_MASK << |
682 | RTL8366S_PORT_VLAN_CTRL_MASK << |
|
683 | RTL8366S_PORT_VLAN_CTRL_SHIFT(port), |
683 | RTL8366S_PORT_VLAN_CTRL_SHIFT(port), |
|
684 | (index & RTL8366S_PORT_VLAN_CTRL_MASK) << |
684 | (index & RTL8366S_PORT_VLAN_CTRL_MASK) << |
|
685 | RTL8366S_PORT_VLAN_CTRL_SHIFT(port)); |
685 | RTL8366S_PORT_VLAN_CTRL_SHIFT(port)); |
|
686 | } |
686 | } |
|
687 | |
687 | |
|
688 | static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable) |
688 | static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable) |
|
689 | { |
689 | { |
|
690 | return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN, |
690 | return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN, |
|
691 | (enable) ? RTL8366S_SGCR_EN_VLAN : 0); |
691 | (enable) ? RTL8366S_SGCR_EN_VLAN : 0); |
|
692 | } |
692 | } |
|
693 | |
693 | |
|
694 | static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable) |
694 | static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable) |
|
695 | { |
695 | { |
|
696 | return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG, |
696 | return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG, |
|
697 | 1, (enable) ? 1 : 0); |
697 | 1, (enable) ? 1 : 0); |
|
698 | } |
698 | } |
|
699 | |
699 | |
|
700 | static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) |
700 | static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan) |
|
701 | { |
701 | { |
|
702 | unsigned max = RTL8366S_NUM_VLANS; |
702 | unsigned max = RTL8366S_NUM_VLANS; |
|
703 | |
703 | |
|
704 | if (smi->vlan4k_enabled) |
704 | if (smi->vlan4k_enabled) |
|
705 | max = RTL8366S_NUM_VIDS - 1; |
705 | max = RTL8366S_NUM_VIDS - 1; |
|
706 | |
706 | |
|
707 | if (vlan == 0 || vlan >= max) |
707 | if (vlan == 0 || vlan >= max) |
|
708 | return 0; |
708 | return 0; |
|
709 | |
709 | |
|
710 | return 1; |
710 | return 1; |
|
711 | } |
711 | } |
|
712 | |
712 | |
|
713 | static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable) |
713 | static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable) |
|
714 | { |
714 | { |
|
715 | return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port), |
715 | return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port), |
|
716 | (enable) ? 0 : (1 << port)); |
716 | (enable) ? 0 : (1 << port)); |
|
717 | } |
717 | } |
|
718 | |
718 | |
|
719 | static int rtl8366s_sw_reset_mibs(struct switch_dev *dev, |
719 | static int rtl8366s_sw_reset_mibs(struct switch_dev *dev, |
|
720 | const struct switch_attr *attr, |
720 | const struct switch_attr *attr, |
|
721 | struct switch_val *val) |
721 | struct switch_val *val) |
|
722 | { |
722 | { |
|
723 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
723 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
724 | |
724 | |
|
725 | return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2)); |
725 | return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2)); |
|
726 | } |
726 | } |
|
727 | |
727 | |
|
728 | static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev, |
728 | static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev, |
|
729 | const struct switch_attr *attr, |
729 | const struct switch_attr *attr, |
|
730 | struct switch_val *val) |
730 | struct switch_val *val) |
|
731 | { |
731 | { |
|
732 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
732 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
733 | u32 data; |
733 | u32 data; |
|
734 | |
734 | |
|
735 | rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data); |
735 | rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data); |
|
736 | |
736 | |
|
737 | val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK)); |
737 | val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK)); |
|
738 | |
738 | |
|
739 | return 0; |
739 | return 0; |
|
740 | } |
740 | } |
|
741 | |
741 | |
|
742 | static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev, |
742 | static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev, |
|
743 | const struct switch_attr *attr, |
743 | const struct switch_attr *attr, |
|
744 | struct switch_val *val) |
744 | struct switch_val *val) |
|
745 | { |
745 | { |
|
746 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
746 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
747 | |
747 | |
|
748 | if (val->value.i >= 6) |
748 | if (val->value.i >= 6) |
|
749 | return -EINVAL; |
749 | return -EINVAL; |
|
750 | |
750 | |
|
751 | return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, |
751 | return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, |
|
752 | RTL8366S_LED_BLINKRATE_MASK, |
752 | RTL8366S_LED_BLINKRATE_MASK, |
|
753 | val->value.i); |
753 | val->value.i); |
|
754 | } |
754 | } |
|
755 | |
755 | |
|
756 | static int rtl8366s_sw_get_max_length(struct switch_dev *dev, |
756 | static int rtl8366s_sw_get_max_length(struct switch_dev *dev, |
|
757 | const struct switch_attr *attr, |
757 | const struct switch_attr *attr, |
|
758 | struct switch_val *val) |
758 | struct switch_val *val) |
|
759 | { |
759 | { |
|
760 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
760 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
761 | u32 data; |
761 | u32 data; |
|
762 | |
762 | |
|
763 | rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data); |
763 | rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data); |
|
764 | |
764 | |
|
765 | val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4); |
765 | val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4); |
|
766 | |
766 | |
|
767 | return 0; |
767 | return 0; |
|
768 | } |
768 | } |
|
769 | |
769 | |
|
770 | static int rtl8366s_sw_set_max_length(struct switch_dev *dev, |
770 | static int rtl8366s_sw_set_max_length(struct switch_dev *dev, |
|
771 | const struct switch_attr *attr, |
771 | const struct switch_attr *attr, |
|
772 | struct switch_val *val) |
772 | struct switch_val *val) |
|
773 | { |
773 | { |
|
774 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
774 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
775 | char length_code; |
775 | char length_code; |
|
776 | |
776 | |
|
777 | switch (val->value.i) { |
777 | switch (val->value.i) { |
|
778 | case 0: |
778 | case 0: |
|
779 | length_code = RTL8366S_SGCR_MAX_LENGTH_1522; |
779 | length_code = RTL8366S_SGCR_MAX_LENGTH_1522; |
|
780 | break; |
780 | break; |
|
781 | case 1: |
781 | case 1: |
|
782 | length_code = RTL8366S_SGCR_MAX_LENGTH_1536; |
782 | length_code = RTL8366S_SGCR_MAX_LENGTH_1536; |
|
783 | break; |
783 | break; |
|
784 | case 2: |
784 | case 2: |
|
785 | length_code = RTL8366S_SGCR_MAX_LENGTH_1552; |
785 | length_code = RTL8366S_SGCR_MAX_LENGTH_1552; |
|
786 | break; |
786 | break; |
|
787 | case 3: |
787 | case 3: |
|
788 | length_code = RTL8366S_SGCR_MAX_LENGTH_16000; |
788 | length_code = RTL8366S_SGCR_MAX_LENGTH_16000; |
|
789 | break; |
789 | break; |
|
790 | default: |
790 | default: |
|
791 | return -EINVAL; |
791 | return -EINVAL; |
|
792 | } |
792 | } |
|
793 | |
793 | |
|
794 | return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, |
794 | return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, |
|
795 | RTL8366S_SGCR_MAX_LENGTH_MASK, |
795 | RTL8366S_SGCR_MAX_LENGTH_MASK, |
|
796 | length_code); |
796 | length_code); |
|
797 | } |
797 | } |
|
798 | |
798 | |
|
799 | static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev, |
799 | static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev, |
|
800 | const struct switch_attr *attr, |
800 | const struct switch_attr *attr, |
|
801 | struct switch_val *val) |
801 | struct switch_val *val) |
|
802 | { |
802 | { |
|
803 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
803 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
804 | u32 data; |
804 | u32 data; |
|
805 | |
805 | |
|
806 | rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data); |
806 | rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data); |
|
807 | val->value.i = !data; |
807 | val->value.i = !data; |
|
808 | |
808 | |
|
809 | return 0; |
809 | return 0; |
|
810 | } |
810 | } |
|
811 | |
811 | |
|
812 | |
812 | |
|
813 | static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev, |
813 | static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev, |
|
814 | const struct switch_attr *attr, |
814 | const struct switch_attr *attr, |
|
815 | struct switch_val *val) |
815 | struct switch_val *val) |
|
816 | { |
816 | { |
|
817 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
817 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
818 | u32 portmask = 0; |
818 | u32 portmask = 0; |
|
819 | int err = 0; |
819 | int err = 0; |
|
820 | |
820 | |
|
821 | if (!val->value.i) |
821 | if (!val->value.i) |
|
822 | portmask = RTL8366S_PORT_ALL; |
822 | portmask = RTL8366S_PORT_ALL; |
|
823 | |
823 | |
|
824 | /* set learning for all ports */ |
824 | /* set learning for all ports */ |
|
825 | REG_WR(smi, RTL8366S_SSCR0, portmask); |
825 | REG_WR(smi, RTL8366S_SSCR0, portmask); |
|
826 | |
826 | |
|
827 | /* set auto ageing for all ports */ |
827 | /* set auto ageing for all ports */ |
|
828 | REG_WR(smi, RTL8366S_SSCR1, portmask); |
828 | REG_WR(smi, RTL8366S_SSCR1, portmask); |
|
829 | |
829 | |
|
830 | return 0; |
830 | return 0; |
|
831 | } |
831 | } |
|
832 | |
832 | |
|
833 | static int rtl8366s_sw_get_green(struct switch_dev *dev, |
833 | static int rtl8366s_sw_get_green(struct switch_dev *dev, |
|
834 | const struct switch_attr *attr, |
834 | const struct switch_attr *attr, |
|
835 | struct switch_val *val) |
835 | struct switch_val *val) |
|
836 | { |
836 | { |
|
837 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
837 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
838 | u32 data; |
838 | u32 data; |
|
839 | int err; |
839 | int err; |
|
840 | |
840 | |
|
841 | err = rtl8366_smi_read_reg(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, &data); |
841 | err = rtl8366_smi_read_reg(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, &data); |
|
842 | if (err) |
842 | if (err) |
|
843 | return err; |
843 | return err; |
|
844 | |
844 | |
|
845 | val->value.i = ((data & (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT)) != 0) ? 1 : 0; |
845 | val->value.i = ((data & (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT)) != 0) ? 1 : 0; |
|
846 | |
846 | |
|
847 | return 0; |
847 | return 0; |
|
848 | } |
848 | } |
|
849 | |
849 | |
|
850 | static int rtl8366s_sw_set_green(struct switch_dev *dev, |
850 | static int rtl8366s_sw_set_green(struct switch_dev *dev, |
|
851 | const struct switch_attr *attr, |
851 | const struct switch_attr *attr, |
|
852 | struct switch_val *val) |
852 | struct switch_val *val) |
|
853 | { |
853 | { |
|
854 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
854 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
855 | |
855 | |
|
856 | return rtl8366s_set_green(smi, val->value.i); |
856 | return rtl8366s_set_green(smi, val->value.i); |
|
857 | } |
857 | } |
|
858 | |
858 | |
|
859 | static int rtl8366s_sw_get_port_link(struct switch_dev *dev, |
859 | static int rtl8366s_sw_get_port_link(struct switch_dev *dev, |
|
860 | int port, |
860 | int port, |
|
861 | struct switch_port_link *link) |
861 | struct switch_port_link *link) |
|
862 | { |
862 | { |
|
863 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
863 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
864 | u32 data = 0; |
864 | u32 data = 0; |
|
865 | u32 speed; |
865 | u32 speed; |
|
866 | |
866 | |
|
867 | if (port >= RTL8366S_NUM_PORTS) |
867 | if (port >= RTL8366S_NUM_PORTS) |
|
868 | return -EINVAL; |
868 | return -EINVAL; |
|
869 | |
869 | |
|
870 | rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2), |
870 | rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2), |
|
871 | &data); |
871 | &data); |
|
872 | |
872 | |
|
873 | if (port % 2) |
873 | if (port % 2) |
|
874 | data = data >> 8; |
874 | data = data >> 8; |
|
875 | |
875 | |
|
876 | link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK); |
876 | link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK); |
|
877 | if (!link->link) |
877 | if (!link->link) |
|
878 | return 0; |
878 | return 0; |
|
879 | |
879 | |
|
880 | link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK); |
880 | link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK); |
|
881 | link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK); |
881 | link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK); |
|
882 | link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK); |
882 | link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK); |
|
883 | link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK); |
883 | link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK); |
|
884 | |
884 | |
|
885 | speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK); |
885 | speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK); |
|
886 | switch (speed) { |
886 | switch (speed) { |
|
887 | case 0: |
887 | case 0: |
|
888 | link->speed = SWITCH_PORT_SPEED_10; |
888 | link->speed = SWITCH_PORT_SPEED_10; |
|
889 | break; |
889 | break; |
|
890 | case 1: |
890 | case 1: |
|
891 | link->speed = SWITCH_PORT_SPEED_100; |
891 | link->speed = SWITCH_PORT_SPEED_100; |
|
892 | break; |
892 | break; |
|
893 | case 2: |
893 | case 2: |
|
894 | link->speed = SWITCH_PORT_SPEED_1000; |
894 | link->speed = SWITCH_PORT_SPEED_1000; |
|
895 | break; |
895 | break; |
|
896 | default: |
896 | default: |
|
897 | link->speed = SWITCH_PORT_SPEED_UNKNOWN; |
897 | link->speed = SWITCH_PORT_SPEED_UNKNOWN; |
|
898 | break; |
898 | break; |
|
899 | } |
899 | } |
|
900 | |
900 | |
|
901 | return 0; |
901 | return 0; |
|
902 | } |
902 | } |
|
903 | |
903 | |
|
904 | static int rtl8366s_sw_set_port_led(struct switch_dev *dev, |
904 | static int rtl8366s_sw_set_port_led(struct switch_dev *dev, |
|
905 | const struct switch_attr *attr, |
905 | const struct switch_attr *attr, |
|
906 | struct switch_val *val) |
906 | struct switch_val *val) |
|
907 | { |
907 | { |
|
908 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
908 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
909 | u32 data; |
909 | u32 data; |
|
910 | u32 mask; |
910 | u32 mask; |
|
911 | u32 reg; |
911 | u32 reg; |
|
912 | |
912 | |
|
913 | if (val->port_vlan >= RTL8366S_NUM_PORTS || |
913 | if (val->port_vlan >= RTL8366S_NUM_PORTS || |
|
914 | (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN) |
914 | (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN) |
|
915 | return -EINVAL; |
915 | return -EINVAL; |
|
916 | |
916 | |
|
917 | if (val->port_vlan == RTL8366S_PORT_NUM_CPU) { |
917 | if (val->port_vlan == RTL8366S_PORT_NUM_CPU) { |
|
918 | reg = RTL8366S_LED_BLINKRATE_REG; |
918 | reg = RTL8366S_LED_BLINKRATE_REG; |
|
919 | mask = 0xF << 4; |
919 | mask = 0xF << 4; |
|
920 | data = val->value.i << 4; |
920 | data = val->value.i << 4; |
|
921 | } else { |
921 | } else { |
|
922 | reg = RTL8366S_LED_CTRL_REG; |
922 | reg = RTL8366S_LED_CTRL_REG; |
|
923 | mask = 0xF << (val->port_vlan * 4), |
923 | mask = 0xF << (val->port_vlan * 4), |
|
924 | data = val->value.i << (val->port_vlan * 4); |
924 | data = val->value.i << (val->port_vlan * 4); |
|
925 | } |
925 | } |
|
926 | |
926 | |
|
927 | return rtl8366_smi_rmwr(smi, reg, mask, data); |
927 | return rtl8366_smi_rmwr(smi, reg, mask, data); |
|
928 | } |
928 | } |
|
929 | |
929 | |
|
930 | static int rtl8366s_sw_get_port_led(struct switch_dev *dev, |
930 | static int rtl8366s_sw_get_port_led(struct switch_dev *dev, |
|
931 | const struct switch_attr *attr, |
931 | const struct switch_attr *attr, |
|
932 | struct switch_val *val) |
932 | struct switch_val *val) |
|
933 | { |
933 | { |
|
934 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
934 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
935 | u32 data = 0; |
935 | u32 data = 0; |
|
936 | |
936 | |
|
937 | if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS) |
937 | if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS) |
|
938 | return -EINVAL; |
938 | return -EINVAL; |
|
939 | |
939 | |
|
940 | rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data); |
940 | rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data); |
|
941 | val->value.i = (data >> (val->port_vlan * 4)) & 0x000F; |
941 | val->value.i = (data >> (val->port_vlan * 4)) & 0x000F; |
|
942 | |
942 | |
|
943 | return 0; |
943 | return 0; |
|
944 | } |
944 | } |
|
945 | |
945 | |
|
946 | static int rtl8366s_sw_get_green_port(struct switch_dev *dev, |
946 | static int rtl8366s_sw_get_green_port(struct switch_dev *dev, |
|
947 | const struct switch_attr *attr, |
947 | const struct switch_attr *attr, |
|
948 | struct switch_val *val) |
948 | struct switch_val *val) |
|
949 | { |
949 | { |
|
950 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
950 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
951 | int err; |
951 | int err; |
|
952 | u32 phyData; |
952 | u32 phyData; |
|
953 | |
953 | |
|
954 | if (val->port_vlan >= RTL8366S_NUM_PORTS) |
954 | if (val->port_vlan >= RTL8366S_NUM_PORTS) |
|
955 | return -EINVAL; |
955 | return -EINVAL; |
|
956 | |
956 | |
|
957 | err = rtl8366s_read_phy_reg(smi, val->port_vlan, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData); |
957 | err = rtl8366s_read_phy_reg(smi, val->port_vlan, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData); |
|
958 | if (err) |
958 | if (err) |
|
959 | return err; |
959 | return err; |
|
960 | |
960 | |
|
961 | val->value.i = ((phyData & RTL8366S_PHY_POWER_SAVING_MASK) != 0) ? 1 : 0; |
961 | val->value.i = ((phyData & RTL8366S_PHY_POWER_SAVING_MASK) != 0) ? 1 : 0; |
|
962 | |
962 | |
|
963 | return 0; |
963 | return 0; |
|
964 | } |
964 | } |
|
965 | |
965 | |
|
966 | static int rtl8366s_sw_set_green_port(struct switch_dev *dev, |
966 | static int rtl8366s_sw_set_green_port(struct switch_dev *dev, |
|
967 | const struct switch_attr *attr, |
967 | const struct switch_attr *attr, |
|
968 | struct switch_val *val) |
968 | struct switch_val *val) |
|
969 | { |
969 | { |
|
970 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
970 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
971 | return rtl8366s_set_green_port(smi, val->port_vlan, val->value.i); |
971 | return rtl8366s_set_green_port(smi, val->port_vlan, val->value.i); |
|
972 | } |
972 | } |
|
973 | |
973 | |
|
974 | static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev, |
974 | static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev, |
|
975 | const struct switch_attr *attr, |
975 | const struct switch_attr *attr, |
|
976 | struct switch_val *val) |
976 | struct switch_val *val) |
|
977 | { |
977 | { |
|
978 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
978 | struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev); |
|
979 | |
979 | |
|
980 | if (val->port_vlan >= RTL8366S_NUM_PORTS) |
980 | if (val->port_vlan >= RTL8366S_NUM_PORTS) |
|
981 | return -EINVAL; |
981 | return -EINVAL; |
|
982 | |
982 | |
|
983 | |
983 | |
|
984 | return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, |
984 | return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, |
|
985 | 0, (1 << (val->port_vlan + 3))); |
985 | 0, (1 << (val->port_vlan + 3))); |
|
986 | } |
986 | } |
|
987 | |
987 | |
|
988 | static int rtl8366s_sw_get_port_stats(struct switch_dev *dev, int port, |
988 | static int rtl8366s_sw_get_port_stats(struct switch_dev *dev, int port, |
|
989 | struct switch_port_stats *stats) |
989 | struct switch_port_stats *stats) |
|
990 | { |
990 | { |
|
991 | return (rtl8366_sw_get_port_stats(dev, port, stats, |
991 | return (rtl8366_sw_get_port_stats(dev, port, stats, |
|
992 | RTL8366S_MIB_TXB_ID, RTL8366S_MIB_RXB_ID)); |
992 | RTL8366S_MIB_TXB_ID, RTL8366S_MIB_RXB_ID)); |
|
993 | } |
993 | } |
|
994 | |
994 | |
|
995 | static struct switch_attr rtl8366s_globals[] = { |
995 | static struct switch_attr rtl8366s_globals[] = { |
|
996 | { |
996 | { |
|
997 | .type = SWITCH_TYPE_INT, |
997 | .type = SWITCH_TYPE_INT, |
|
998 | .name = "enable_learning", |
998 | .name = "enable_learning", |
|
999 | .description = "Enable learning, enable aging", |
999 | .description = "Enable learning, enable aging", |
|
1000 | .set = rtl8366s_sw_set_learning_enable, |
1000 | .set = rtl8366s_sw_set_learning_enable, |
|
1001 | .get = rtl8366s_sw_get_learning_enable, |
1001 | .get = rtl8366s_sw_get_learning_enable, |
|
1002 | .max = 1, |
1002 | .max = 1, |
|
1003 | }, { |
1003 | }, { |
|
1004 | .type = SWITCH_TYPE_INT, |
1004 | .type = SWITCH_TYPE_INT, |
|
1005 | .name = "enable_vlan", |
1005 | .name = "enable_vlan", |
|
1006 | .description = "Enable VLAN mode", |
1006 | .description = "Enable VLAN mode", |
|
1007 | .set = rtl8366_sw_set_vlan_enable, |
1007 | .set = rtl8366_sw_set_vlan_enable, |
|
1008 | .get = rtl8366_sw_get_vlan_enable, |
1008 | .get = rtl8366_sw_get_vlan_enable, |
|
1009 | .max = 1, |
1009 | .max = 1, |
|
1010 | .ofs = 1 |
1010 | .ofs = 1 |
|
1011 | }, { |
1011 | }, { |
|
1012 | .type = SWITCH_TYPE_INT, |
1012 | .type = SWITCH_TYPE_INT, |
|
1013 | .name = "enable_vlan4k", |
1013 | .name = "enable_vlan4k", |
|
1014 | .description = "Enable VLAN 4K mode", |
1014 | .description = "Enable VLAN 4K mode", |
|
1015 | .set = rtl8366_sw_set_vlan_enable, |
1015 | .set = rtl8366_sw_set_vlan_enable, |
|
1016 | .get = rtl8366_sw_get_vlan_enable, |
1016 | .get = rtl8366_sw_get_vlan_enable, |
|
1017 | .max = 1, |
1017 | .max = 1, |
|
1018 | .ofs = 2 |
1018 | .ofs = 2 |
|
1019 | }, { |
1019 | }, { |
|
1020 | .type = SWITCH_TYPE_NOVAL, |
1020 | .type = SWITCH_TYPE_NOVAL, |
|
1021 | .name = "reset_mibs", |
1021 | .name = "reset_mibs", |
|
1022 | .description = "Reset all MIB counters", |
1022 | .description = "Reset all MIB counters", |
|
1023 | .set = rtl8366s_sw_reset_mibs, |
1023 | .set = rtl8366s_sw_reset_mibs, |
|
1024 | }, { |
1024 | }, { |
|
1025 | .type = SWITCH_TYPE_INT, |
1025 | .type = SWITCH_TYPE_INT, |
|
1026 | .name = "blinkrate", |
1026 | .name = "blinkrate", |
|
1027 | .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms," |
1027 | .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms," |
|
1028 | " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)", |
1028 | " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)", |
|
1029 | .set = rtl8366s_sw_set_blinkrate, |
1029 | .set = rtl8366s_sw_set_blinkrate, |
|
1030 | .get = rtl8366s_sw_get_blinkrate, |
1030 | .get = rtl8366s_sw_get_blinkrate, |
|
1031 | .max = 5 |
1031 | .max = 5 |
|
1032 | }, { |
1032 | }, { |
|
1033 | .type = SWITCH_TYPE_INT, |
1033 | .type = SWITCH_TYPE_INT, |
|
1034 | .name = "max_length", |
1034 | .name = "max_length", |
|
1035 | .description = "Get/Set the maximum length of valid packets" |
1035 | .description = "Get/Set the maximum length of valid packets" |
|
1036 | " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))", |
1036 | " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))", |
|
1037 | .set = rtl8366s_sw_set_max_length, |
1037 | .set = rtl8366s_sw_set_max_length, |
|
1038 | .get = rtl8366s_sw_get_max_length, |
1038 | .get = rtl8366s_sw_get_max_length, |
|
1039 | .max = 3, |
1039 | .max = 3, |
|
1040 | }, { |
1040 | }, { |
|
1041 | .type = SWITCH_TYPE_INT, |
1041 | .type = SWITCH_TYPE_INT, |
|
1042 | .name = "green_mode", |
1042 | .name = "green_mode", |
|
1043 | .description = "Get/Set the router green feature", |
1043 | .description = "Get/Set the router green feature", |
|
1044 | .set = rtl8366s_sw_set_green, |
1044 | .set = rtl8366s_sw_set_green, |
|
1045 | .get = rtl8366s_sw_get_green, |
1045 | .get = rtl8366s_sw_get_green, |
|
1046 | .max = 1, |
1046 | .max = 1, |
|
1047 | }, |
1047 | }, |
|
1048 | }; |
1048 | }; |
|
1049 | |
1049 | |
|
1050 | static struct switch_attr rtl8366s_port[] = { |
1050 | static struct switch_attr rtl8366s_port[] = { |
|
1051 | { |
1051 | { |
|
1052 | .type = SWITCH_TYPE_NOVAL, |
1052 | .type = SWITCH_TYPE_NOVAL, |
|
1053 | .name = "reset_mib", |
1053 | .name = "reset_mib", |
|
1054 | .description = "Reset single port MIB counters", |
1054 | .description = "Reset single port MIB counters", |
|
1055 | .set = rtl8366s_sw_reset_port_mibs, |
1055 | .set = rtl8366s_sw_reset_port_mibs, |
|
1056 | }, { |
1056 | }, { |
|
1057 | .type = SWITCH_TYPE_STRING, |
1057 | .type = SWITCH_TYPE_STRING, |
|
1058 | .name = "mib", |
1058 | .name = "mib", |
|
1059 | .description = "Get MIB counters for port", |
1059 | .description = "Get MIB counters for port", |
|
1060 | .max = 33, |
1060 | .max = 33, |
|
1061 | .set = NULL, |
1061 | .set = NULL, |
|
1062 | .get = rtl8366_sw_get_port_mib, |
1062 | .get = rtl8366_sw_get_port_mib, |
|
1063 | }, { |
1063 | }, { |
|
1064 | .type = SWITCH_TYPE_INT, |
1064 | .type = SWITCH_TYPE_INT, |
|
1065 | .name = "led", |
1065 | .name = "led", |
|
1066 | .description = "Get/Set port group (0 - 3) led mode (0 - 15)", |
1066 | .description = "Get/Set port group (0 - 3) led mode (0 - 15)", |
|
1067 | .max = 15, |
1067 | .max = 15, |
|
1068 | .set = rtl8366s_sw_set_port_led, |
1068 | .set = rtl8366s_sw_set_port_led, |
|
1069 | .get = rtl8366s_sw_get_port_led, |
1069 | .get = rtl8366s_sw_get_port_led, |
|
1070 | }, { |
1070 | }, { |
|
1071 | .type = SWITCH_TYPE_INT, |
1071 | .type = SWITCH_TYPE_INT, |
|
1072 | .name = "green_port", |
1072 | .name = "green_port", |
|
1073 | .description = "Get/Set port green feature (0 - 1)", |
1073 | .description = "Get/Set port green feature (0 - 1)", |
|
1074 | .max = 1, |
1074 | .max = 1, |
|
1075 | .set = rtl8366s_sw_set_green_port, |
1075 | .set = rtl8366s_sw_set_green_port, |
|
1076 | .get = rtl8366s_sw_get_green_port, |
1076 | .get = rtl8366s_sw_get_green_port, |
|
1077 | }, |
1077 | }, |
|
1078 | }; |
1078 | }; |
|
1079 | |
1079 | |
|
1080 | static struct switch_attr rtl8366s_vlan[] = { |
1080 | static struct switch_attr rtl8366s_vlan[] = { |
|
1081 | { |
1081 | { |
|
1082 | .type = SWITCH_TYPE_STRING, |
1082 | .type = SWITCH_TYPE_STRING, |
|
1083 | .name = "info", |
1083 | .name = "info", |
|
1084 | .description = "Get vlan information", |
1084 | .description = "Get vlan information", |
|
1085 | .max = 1, |
1085 | .max = 1, |
|
1086 | .set = NULL, |
1086 | .set = NULL, |
|
1087 | .get = rtl8366_sw_get_vlan_info, |
1087 | .get = rtl8366_sw_get_vlan_info, |
|
1088 | }, { |
1088 | }, { |
|
1089 | .type = SWITCH_TYPE_INT, |
1089 | .type = SWITCH_TYPE_INT, |
|
1090 | .name = "fid", |
1090 | .name = "fid", |
|
1091 | .description = "Get/Set vlan FID", |
1091 | .description = "Get/Set vlan FID", |
|
1092 | .max = RTL8366S_FIDMAX, |
1092 | .max = RTL8366S_FIDMAX, |
|
1093 | .set = rtl8366_sw_set_vlan_fid, |
1093 | .set = rtl8366_sw_set_vlan_fid, |
|
1094 | .get = rtl8366_sw_get_vlan_fid, |
1094 | .get = rtl8366_sw_get_vlan_fid, |
|
1095 | }, |
1095 | }, |
|
1096 | }; |
1096 | }; |
|
1097 | |
1097 | |
|
1098 | static const struct switch_dev_ops rtl8366_ops = { |
1098 | static const struct switch_dev_ops rtl8366_ops = { |
|
1099 | .attr_global = { |
1099 | .attr_global = { |
|
1100 | .attr = rtl8366s_globals, |
1100 | .attr = rtl8366s_globals, |
|
1101 | .n_attr = ARRAY_SIZE(rtl8366s_globals), |
1101 | .n_attr = ARRAY_SIZE(rtl8366s_globals), |
|
1102 | }, |
1102 | }, |
|
1103 | .attr_port = { |
1103 | .attr_port = { |
|
1104 | .attr = rtl8366s_port, |
1104 | .attr = rtl8366s_port, |
|
1105 | .n_attr = ARRAY_SIZE(rtl8366s_port), |
1105 | .n_attr = ARRAY_SIZE(rtl8366s_port), |
|
1106 | }, |
1106 | }, |
|
1107 | .attr_vlan = { |
1107 | .attr_vlan = { |
|
1108 | .attr = rtl8366s_vlan, |
1108 | .attr = rtl8366s_vlan, |
|
1109 | .n_attr = ARRAY_SIZE(rtl8366s_vlan), |
1109 | .n_attr = ARRAY_SIZE(rtl8366s_vlan), |
|
1110 | }, |
1110 | }, |
|
1111 | |
1111 | |
|
1112 | .get_vlan_ports = rtl8366_sw_get_vlan_ports, |
1112 | .get_vlan_ports = rtl8366_sw_get_vlan_ports, |
|
1113 | .set_vlan_ports = rtl8366_sw_set_vlan_ports, |
1113 | .set_vlan_ports = rtl8366_sw_set_vlan_ports, |
|
1114 | .get_port_pvid = rtl8366_sw_get_port_pvid, |
1114 | .get_port_pvid = rtl8366_sw_get_port_pvid, |
|
1115 | .set_port_pvid = rtl8366_sw_set_port_pvid, |
1115 | .set_port_pvid = rtl8366_sw_set_port_pvid, |
|
1116 | .reset_switch = rtl8366_sw_reset_switch, |
1116 | .reset_switch = rtl8366_sw_reset_switch, |
|
1117 | .get_port_link = rtl8366s_sw_get_port_link, |
1117 | .get_port_link = rtl8366s_sw_get_port_link, |
|
1118 | .get_port_stats = rtl8366s_sw_get_port_stats, |
1118 | .get_port_stats = rtl8366s_sw_get_port_stats, |
|
1119 | }; |
1119 | }; |
|
1120 | |
1120 | |
|
1121 | static int rtl8366s_switch_init(struct rtl8366_smi *smi) |
1121 | static int rtl8366s_switch_init(struct rtl8366_smi *smi) |
|
1122 | { |
1122 | { |
|
1123 | struct switch_dev *dev = &smi->sw_dev; |
1123 | struct switch_dev *dev = &smi->sw_dev; |
|
1124 | int err; |
1124 | int err; |
|
1125 | |
1125 | |
|
1126 | dev->name = "RTL8366S"; |
1126 | dev->name = "RTL8366S"; |
|
1127 | dev->cpu_port = RTL8366S_PORT_NUM_CPU; |
1127 | dev->cpu_port = RTL8366S_PORT_NUM_CPU; |
|
1128 | dev->ports = RTL8366S_NUM_PORTS; |
1128 | dev->ports = RTL8366S_NUM_PORTS; |
|
1129 | dev->vlans = RTL8366S_NUM_VIDS; |
1129 | dev->vlans = RTL8366S_NUM_VIDS; |
|
1130 | dev->ops = &rtl8366_ops; |
1130 | dev->ops = &rtl8366_ops; |
|
1131 | dev->alias = dev_name(smi->parent); |
1131 | dev->alias = dev_name(smi->parent); |
|
1132 | |
1132 | |
|
1133 | err = register_switch(dev, NULL); |
1133 | err = register_switch(dev, NULL); |
|
1134 | if (err) |
1134 | if (err) |
|
1135 | dev_err(smi->parent, "switch registration failed\n"); |
1135 | dev_err(smi->parent, "switch registration failed\n"); |
|
1136 | |
1136 | |
|
1137 | return err; |
1137 | return err; |
|
1138 | } |
1138 | } |
|
1139 | |
1139 | |
|
1140 | static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi) |
1140 | static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi) |
|
1141 | { |
1141 | { |
|
1142 | unregister_switch(&smi->sw_dev); |
1142 | unregister_switch(&smi->sw_dev); |
|
1143 | } |
1143 | } |
|
1144 | |
1144 | |
|
1145 | static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg) |
1145 | static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg) |
|
1146 | { |
1146 | { |
|
1147 | struct rtl8366_smi *smi = bus->priv; |
1147 | struct rtl8366_smi *smi = bus->priv; |
|
1148 | u32 val = 0; |
1148 | u32 val = 0; |
|
1149 | int err; |
1149 | int err; |
|
1150 | |
1150 | |
|
1151 | err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val); |
1151 | err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val); |
|
1152 | if (err) |
1152 | if (err) |
|
1153 | return 0xffff; |
1153 | return 0xffff; |
|
1154 | |
1154 | |
|
1155 | return val; |
1155 | return val; |
|
1156 | } |
1156 | } |
|
1157 | |
1157 | |
|
1158 | static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) |
1158 | static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val) |
|
1159 | { |
1159 | { |
|
1160 | struct rtl8366_smi *smi = bus->priv; |
1160 | struct rtl8366_smi *smi = bus->priv; |
|
1161 | u32 t; |
1161 | u32 t; |
|
1162 | int err; |
1162 | int err; |
|
1163 | |
1163 | |
|
1164 | err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val); |
1164 | err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val); |
|
1165 | /* flush write */ |
1165 | /* flush write */ |
|
1166 | (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t); |
1166 | (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t); |
|
1167 | |
1167 | |
|
1168 | return err; |
1168 | return err; |
|
1169 | } |
1169 | } |
|
1170 | |
1170 | |
|
1171 | static int rtl8366s_detect(struct rtl8366_smi *smi) |
1171 | static int rtl8366s_detect(struct rtl8366_smi *smi) |
|
1172 | { |
1172 | { |
|
1173 | u32 chip_id = 0; |
1173 | u32 chip_id = 0; |
|
1174 | u32 chip_ver = 0; |
1174 | u32 chip_ver = 0; |
|
1175 | int ret; |
1175 | int ret; |
|
1176 | |
1176 | |
|
1177 | ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id); |
1177 | ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id); |
|
1178 | if (ret) { |
1178 | if (ret) { |
|
1179 | dev_err(smi->parent, "unable to read chip id\n"); |
1179 | dev_err(smi->parent, "unable to read chip id\n"); |
|
1180 | return ret; |
1180 | return ret; |
|
1181 | } |
1181 | } |
|
1182 | |
1182 | |
|
1183 | switch (chip_id) { |
1183 | switch (chip_id) { |
|
1184 | case RTL8366S_CHIP_ID_8366: |
1184 | case RTL8366S_CHIP_ID_8366: |
|
1185 | break; |
1185 | break; |
|
1186 | default: |
1186 | default: |
|
1187 | dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id); |
1187 | dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id); |
|
1188 | return -ENODEV; |
1188 | return -ENODEV; |
|
1189 | } |
1189 | } |
|
1190 | |
1190 | |
|
1191 | ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG, |
1191 | ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG, |
|
1192 | &chip_ver); |
1192 | &chip_ver); |
|
1193 | if (ret) { |
1193 | if (ret) { |
|
1194 | dev_err(smi->parent, "unable to read chip version\n"); |
1194 | dev_err(smi->parent, "unable to read chip version\n"); |
|
1195 | return ret; |
1195 | return ret; |
|
1196 | } |
1196 | } |
|
1197 | |
1197 | |
|
1198 | dev_info(smi->parent, "RTL%04x ver. %u chip found\n", |
1198 | dev_info(smi->parent, "RTL%04x ver. %u chip found\n", |
|
1199 | chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK); |
1199 | chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK); |
|
1200 | |
1200 | |
|
1201 | return 0; |
1201 | return 0; |
|
1202 | } |
1202 | } |
|
1203 | |
1203 | |
|
1204 | static struct rtl8366_smi_ops rtl8366s_smi_ops = { |
1204 | static struct rtl8366_smi_ops rtl8366s_smi_ops = { |
|
1205 | .detect = rtl8366s_detect, |
1205 | .detect = rtl8366s_detect, |
|
1206 | .reset_chip = rtl8366s_reset_chip, |
1206 | .reset_chip = rtl8366s_reset_chip, |
|
1207 | .setup = rtl8366s_setup, |
1207 | .setup = rtl8366s_setup, |
|
1208 | |
1208 | |
|
1209 | .mii_read = rtl8366s_mii_read, |
1209 | .mii_read = rtl8366s_mii_read, |
|
1210 | .mii_write = rtl8366s_mii_write, |
1210 | .mii_write = rtl8366s_mii_write, |
|
1211 | |
1211 | |
|
1212 | .get_vlan_mc = rtl8366s_get_vlan_mc, |
1212 | .get_vlan_mc = rtl8366s_get_vlan_mc, |
|
1213 | .set_vlan_mc = rtl8366s_set_vlan_mc, |
1213 | .set_vlan_mc = rtl8366s_set_vlan_mc, |
|
1214 | .get_vlan_4k = rtl8366s_get_vlan_4k, |
1214 | .get_vlan_4k = rtl8366s_get_vlan_4k, |
|
1215 | .set_vlan_4k = rtl8366s_set_vlan_4k, |
1215 | .set_vlan_4k = rtl8366s_set_vlan_4k, |
|
1216 | .get_mc_index = rtl8366s_get_mc_index, |
1216 | .get_mc_index = rtl8366s_get_mc_index, |
|
1217 | .set_mc_index = rtl8366s_set_mc_index, |
1217 | .set_mc_index = rtl8366s_set_mc_index, |
|
1218 | .get_mib_counter = rtl8366_get_mib_counter, |
1218 | .get_mib_counter = rtl8366_get_mib_counter, |
|
1219 | .is_vlan_valid = rtl8366s_is_vlan_valid, |
1219 | .is_vlan_valid = rtl8366s_is_vlan_valid, |
|
1220 | .enable_vlan = rtl8366s_enable_vlan, |
1220 | .enable_vlan = rtl8366s_enable_vlan, |
|
1221 | .enable_vlan4k = rtl8366s_enable_vlan4k, |
1221 | .enable_vlan4k = rtl8366s_enable_vlan4k, |
|
1222 | .enable_port = rtl8366s_enable_port, |
1222 | .enable_port = rtl8366s_enable_port, |
|
1223 | }; |
1223 | }; |
|
1224 | |
1224 | |
|
1225 | static int rtl8366s_probe(struct platform_device *pdev) |
1225 | static int rtl8366s_probe(struct platform_device *pdev) |
|
1226 | { |
1226 | { |
|
1227 | static int rtl8366_smi_version_printed; |
1227 | static int rtl8366_smi_version_printed; |
|
1228 | struct rtl8366_smi *smi; |
1228 | struct rtl8366_smi *smi; |
|
1229 | int err; |
1229 | int err; |
|
1230 | |
1230 | |
|
1231 | if (!rtl8366_smi_version_printed++) |
1231 | if (!rtl8366_smi_version_printed++) |
|
1232 | printk(KERN_NOTICE RTL8366S_DRIVER_DESC |
1232 | printk(KERN_NOTICE RTL8366S_DRIVER_DESC |
|
1233 | " version " RTL8366S_DRIVER_VER"\n"); |
1233 | " version " RTL8366S_DRIVER_VER"\n"); |
|
1234 | |
1234 | |
|
1235 | smi = rtl8366_smi_probe(pdev); |
1235 | smi = rtl8366_smi_probe(pdev); |
|
1236 | if (IS_ERR(smi)) |
1236 | if (!smi) |
|
1237 | return PTR_ERR(smi); |
1237 | return -ENODEV; |
|
1238 | |
1238 | |
|
1239 | smi->clk_delay = 10; |
1239 | smi->clk_delay = 10; |
|
1240 | smi->cmd_read = 0xa9; |
1240 | smi->cmd_read = 0xa9; |
|
1241 | smi->cmd_write = 0xa8; |
1241 | smi->cmd_write = 0xa8; |
|
1242 | smi->ops = &rtl8366s_smi_ops; |
1242 | smi->ops = &rtl8366s_smi_ops; |
|
1243 | smi->cpu_port = RTL8366S_PORT_NUM_CPU; |
1243 | smi->cpu_port = RTL8366S_PORT_NUM_CPU; |
|
1244 | smi->num_ports = RTL8366S_NUM_PORTS; |
1244 | smi->num_ports = RTL8366S_NUM_PORTS; |
|
1245 | smi->num_vlan_mc = RTL8366S_NUM_VLANS; |
1245 | smi->num_vlan_mc = RTL8366S_NUM_VLANS; |
|
1246 | smi->mib_counters = rtl8366s_mib_counters; |
1246 | smi->mib_counters = rtl8366s_mib_counters; |
|
1247 | smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters); |
1247 | smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters); |
|
1248 | |
1248 | |
|
1249 | err = rtl8366_smi_init(smi); |
1249 | err = rtl8366_smi_init(smi); |
|
1250 | if (err) |
1250 | if (err) |
|
1251 | goto err_free_smi; |
1251 | goto err_free_smi; |
|
1252 | |
1252 | |
|
1253 | platform_set_drvdata(pdev, smi); |
1253 | platform_set_drvdata(pdev, smi); |
|
1254 | |
1254 | |
|
1255 | err = rtl8366s_switch_init(smi); |
1255 | err = rtl8366s_switch_init(smi); |
|
1256 | if (err) |
1256 | if (err) |
|
1257 | goto err_clear_drvdata; |
1257 | goto err_clear_drvdata; |
|
1258 | |
1258 | |
|
1259 | return 0; |
1259 | return 0; |
|
1260 | |
1260 | |
|
1261 | err_clear_drvdata: |
1261 | err_clear_drvdata: |
|
1262 | platform_set_drvdata(pdev, NULL); |
1262 | platform_set_drvdata(pdev, NULL); |
|
1263 | rtl8366_smi_cleanup(smi); |
1263 | rtl8366_smi_cleanup(smi); |
|
1264 | err_free_smi: |
1264 | err_free_smi: |
|
1265 | kfree(smi); |
1265 | kfree(smi); |
|
1266 | return err; |
1266 | return err; |
|
1267 | } |
1267 | } |
|
1268 | |
1268 | |
|
1269 | static int rtl8366s_remove(struct platform_device *pdev) |
1269 | static int rtl8366s_remove(struct platform_device *pdev) |
|
1270 | { |
1270 | { |
|
1271 | struct rtl8366_smi *smi = platform_get_drvdata(pdev); |
1271 | struct rtl8366_smi *smi = platform_get_drvdata(pdev); |
|
1272 | |
1272 | |
|
1273 | if (smi) { |
1273 | if (smi) { |
|
1274 | rtl8366s_switch_cleanup(smi); |
1274 | rtl8366s_switch_cleanup(smi); |
|
1275 | platform_set_drvdata(pdev, NULL); |
1275 | platform_set_drvdata(pdev, NULL); |
|
1276 | rtl8366_smi_cleanup(smi); |
1276 | rtl8366_smi_cleanup(smi); |
|
1277 | kfree(smi); |
1277 | kfree(smi); |
|
1278 | } |
1278 | } |
|
1279 | |
1279 | |
|
1280 | return 0; |
1280 | return 0; |
|
1281 | } |
1281 | } |
|
1282 | |
1282 | |
|
1283 | #ifdef CONFIG_OF |
1283 | #ifdef CONFIG_OF |
|
1284 | static const struct of_device_id rtl8366s_match[] = { |
1284 | static const struct of_device_id rtl8366s_match[] = { |
|
1285 | { .compatible = "realtek,rtl8366s" }, |
1285 | { .compatible = "realtek,rtl8366s" }, |
|
1286 | {}, |
1286 | {}, |
|
1287 | }; |
1287 | }; |
|
1288 | MODULE_DEVICE_TABLE(of, rtl8366s_match); |
1288 | MODULE_DEVICE_TABLE(of, rtl8366s_match); |
|
1289 | #endif |
1289 | #endif |
|
1290 | |
1290 | |
|
1291 | static struct platform_driver rtl8366s_driver = { |
1291 | static struct platform_driver rtl8366s_driver = { |
|
1292 | .driver = { |
1292 | .driver = { |
|
1293 | .name = RTL8366S_DRIVER_NAME, |
1293 | .name = RTL8366S_DRIVER_NAME, |
|
1294 | .owner = THIS_MODULE, |
1294 | .owner = THIS_MODULE, |
|
1295 | #ifdef CONFIG_OF |
1295 | #ifdef CONFIG_OF |
|
1296 | .of_match_table = of_match_ptr(rtl8366s_match), |
1296 | .of_match_table = of_match_ptr(rtl8366s_match), |
|
1297 | #endif |
1297 | #endif |
|
1298 | }, |
1298 | }, |
|
1299 | .probe = rtl8366s_probe, |
1299 | .probe = rtl8366s_probe, |
|
1300 | .remove = rtl8366s_remove, |
1300 | .remove = rtl8366s_remove, |
|
1301 | }; |
1301 | }; |
|
1302 | |
1302 | |
|
1303 | static int __init rtl8366s_module_init(void) |
1303 | static int __init rtl8366s_module_init(void) |
|
1304 | { |
1304 | { |
|
1305 | return platform_driver_register(&rtl8366s_driver); |
1305 | return platform_driver_register(&rtl8366s_driver); |
|
1306 | } |
1306 | } |
|
1307 | module_init(rtl8366s_module_init); |
1307 | module_init(rtl8366s_module_init); |
|
1308 | |
1308 | |
|
1309 | static void __exit rtl8366s_module_exit(void) |
1309 | static void __exit rtl8366s_module_exit(void) |
|
1310 | { |
1310 | { |
|
1311 | platform_driver_unregister(&rtl8366s_driver); |
1311 | platform_driver_unregister(&rtl8366s_driver); |
|
1312 | } |
1312 | } |
|
1313 | module_exit(rtl8366s_module_exit); |
1313 | module_exit(rtl8366s_module_exit); |
|
1314 | |
1314 | |
|
1315 | MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC); |
1315 | MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC); |
|
1316 | MODULE_VERSION(RTL8366S_DRIVER_VER); |
1316 | MODULE_VERSION(RTL8366S_DRIVER_VER); |
|
1317 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
1317 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
|
1318 | MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>"); |
1318 | MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>"); |
|
1319 | MODULE_LICENSE("GPL v2"); |
1319 | MODULE_LICENSE("GPL v2"); |
|
1320 | MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME); |
1320 | MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME); |
|
1321 | |
1321 | |