OpenWrt – Diff between revs 2 and 3
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| 1 | /* |
1 | /* |
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| 2 | * ar8327.h: AR8216 switch driver |
2 | * ar8327.h: AR8216 switch driver |
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| 3 | * |
3 | * |
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| 4 | * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> |
4 | * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> |
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| 5 | * |
5 | * |
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| 6 | * This program is free software; you can redistribute it and/or |
6 | * This program is free software; you can redistribute it and/or |
|
| 7 | * modify it under the terms of the GNU General Public License |
7 | * modify it under the terms of the GNU General Public License |
|
| 8 | * as published by the Free Software Foundation; either version 2 |
8 | * as published by the Free Software Foundation; either version 2 |
|
| 9 | * of the License, or (at your option) any later version. |
9 | * of the License, or (at your option) any later version. |
|
| 10 | * |
10 | * |
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| 11 | * This program is distributed in the hope that it will be useful, |
11 | * This program is distributed in the hope that it will be useful, |
|
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 14 | * GNU General Public License for more details. |
14 | * GNU General Public License for more details. |
|
| 15 | */ |
15 | */ |
|
| 16 | |
16 | |
|
| 17 | #ifndef __AR8327_H |
17 | #ifndef __AR8327_H |
|
| 18 | #define __AR8327_H |
18 | #define __AR8327_H |
|
| 19 | |
19 | |
|
| 20 | #define AR8327_NUM_PORTS 7 |
20 | #define AR8327_NUM_PORTS 7 |
|
| 21 | #define AR8327_NUM_LEDS 15 |
21 | #define AR8327_NUM_LEDS 15 |
|
| 22 | #define AR8327_PORTS_ALL 0x7f |
22 | #define AR8327_PORTS_ALL 0x7f |
|
| 23 | #define AR8327_NUM_LED_CTRL_REGS 4 |
23 | #define AR8327_NUM_LED_CTRL_REGS 4 |
|
| 24 | |
24 | |
|
| 25 | #define AR8327_REG_MASK 0x000 |
25 | #define AR8327_REG_MASK 0x000 |
|
| 26 | |
26 | |
|
| 27 | #define AR8327_REG_PAD0_MODE 0x004 |
27 | #define AR8327_REG_PAD0_MODE 0x004 |
|
| 28 | #define AR8327_REG_PAD5_MODE 0x008 |
28 | #define AR8327_REG_PAD5_MODE 0x008 |
|
| 29 | #define AR8327_REG_PAD6_MODE 0x00c |
29 | #define AR8327_REG_PAD6_MODE 0x00c |
|
| 30 | #define AR8327_PAD_MAC_MII_RXCLK_SEL BIT(0) |
30 | #define AR8327_PAD_MAC_MII_RXCLK_SEL BIT(0) |
|
| 31 | #define AR8327_PAD_MAC_MII_TXCLK_SEL BIT(1) |
31 | #define AR8327_PAD_MAC_MII_TXCLK_SEL BIT(1) |
|
| 32 | #define AR8327_PAD_MAC_MII_EN BIT(2) |
32 | #define AR8327_PAD_MAC_MII_EN BIT(2) |
|
| 33 | #define AR8327_PAD_MAC_GMII_RXCLK_SEL BIT(4) |
33 | #define AR8327_PAD_MAC_GMII_RXCLK_SEL BIT(4) |
|
| 34 | #define AR8327_PAD_MAC_GMII_TXCLK_SEL BIT(5) |
34 | #define AR8327_PAD_MAC_GMII_TXCLK_SEL BIT(5) |
|
| 35 | #define AR8327_PAD_MAC_GMII_EN BIT(6) |
35 | #define AR8327_PAD_MAC_GMII_EN BIT(6) |
|
| 36 | #define AR8327_PAD_SGMII_EN BIT(7) |
36 | #define AR8327_PAD_SGMII_EN BIT(7) |
|
| 37 | #define AR8327_PAD_PHY_MII_RXCLK_SEL BIT(8) |
37 | #define AR8327_PAD_PHY_MII_RXCLK_SEL BIT(8) |
|
| 38 | #define AR8327_PAD_PHY_MII_TXCLK_SEL BIT(9) |
38 | #define AR8327_PAD_PHY_MII_TXCLK_SEL BIT(9) |
|
| 39 | #define AR8327_PAD_PHY_MII_EN BIT(10) |
39 | #define AR8327_PAD_PHY_MII_EN BIT(10) |
|
| 40 | #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL BIT(11) |
40 | #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL BIT(11) |
|
| 41 | #define AR8327_PAD_PHY_GMII_RXCLK_SEL BIT(12) |
41 | #define AR8327_PAD_PHY_GMII_RXCLK_SEL BIT(12) |
|
| 42 | #define AR8327_PAD_PHY_GMII_TXCLK_SEL BIT(13) |
42 | #define AR8327_PAD_PHY_GMII_TXCLK_SEL BIT(13) |
|
| 43 | #define AR8327_PAD_PHY_GMII_EN BIT(14) |
43 | #define AR8327_PAD_PHY_GMII_EN BIT(14) |
|
| 44 | #define AR8327_PAD_PHYX_GMII_EN BIT(16) |
44 | #define AR8327_PAD_PHYX_GMII_EN BIT(16) |
|
| 45 | #define AR8327_PAD_PHYX_RGMII_EN BIT(17) |
45 | #define AR8327_PAD_PHYX_RGMII_EN BIT(17) |
|
| 46 | #define AR8327_PAD_PHYX_MII_EN BIT(18) |
46 | #define AR8327_PAD_PHYX_MII_EN BIT(18) |
|
| 47 | #define AR8327_PAD_SGMII_DELAY_EN BIT(19) |
47 | #define AR8327_PAD_SGMII_DELAY_EN BIT(19) |
|
| 48 | #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) |
48 | #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2) |
|
| 49 | #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 |
49 | #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20 |
|
| 50 | #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) |
50 | #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2) |
|
| 51 | #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 |
51 | #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22 |
|
| 52 | #define AR8327_PAD_RGMII_RXCLK_DELAY_EN BIT(24) |
52 | #define AR8327_PAD_RGMII_RXCLK_DELAY_EN BIT(24) |
|
| 53 | #define AR8327_PAD_RGMII_TXCLK_DELAY_EN BIT(25) |
53 | #define AR8327_PAD_RGMII_TXCLK_DELAY_EN BIT(25) |
|
| 54 | #define AR8327_PAD_RGMII_EN BIT(26) |
54 | #define AR8327_PAD_RGMII_EN BIT(26) |
|
| 55 | |
55 | |
|
| 56 | #define AR8327_REG_POWER_ON_STRIP 0x010 |
56 | #define AR8327_REG_POWER_ON_STRIP 0x010 |
|
| 57 | #define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31) |
57 | #define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31) |
|
| 58 | #define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24) |
58 | #define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24) |
|
| 59 | #define AR8327_POWER_ON_STRIP_SERDES_AEN BIT(7) |
59 | #define AR8327_POWER_ON_STRIP_SERDES_AEN BIT(7) |
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| 60 | |
60 | |
|
| 61 | #define AR8327_REG_INT_STATUS0 0x020 |
61 | #define AR8327_REG_INT_STATUS0 0x020 |
|
| 62 | #define AR8327_INT0_VT_DONE BIT(20) |
62 | #define AR8327_INT0_VT_DONE BIT(20) |
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| 63 | |
63 | |
|
| 64 | #define AR8327_REG_INT_STATUS1 0x024 |
64 | #define AR8327_REG_INT_STATUS1 0x024 |
|
| 65 | #define AR8327_REG_INT_MASK0 0x028 |
65 | #define AR8327_REG_INT_MASK0 0x028 |
|
| 66 | #define AR8327_REG_INT_MASK1 0x02c |
66 | #define AR8327_REG_INT_MASK1 0x02c |
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| 67 | |
67 | |
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| 68 | #define AR8327_REG_MODULE_EN 0x030 |
68 | #define AR8327_REG_MODULE_EN 0x030 |
|
| 69 | #define AR8327_MODULE_EN_MIB BIT(0) |
69 | #define AR8327_MODULE_EN_MIB BIT(0) |
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| 70 | |
70 | |
|
| 71 | #define AR8327_REG_MIB_FUNC 0x034 |
71 | #define AR8327_REG_MIB_FUNC 0x034 |
|
| 72 | #define AR8327_MIB_CPU_KEEP BIT(20) |
72 | #define AR8327_MIB_CPU_KEEP BIT(20) |
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| 73 | |
73 | |
|
| 74 | #define AR8327_REG_SERVICE_TAG 0x048 |
74 | #define AR8327_REG_SERVICE_TAG 0x048 |
|
| 75 | #define AR8327_REG_LED_CTRL(_i) (0x050 + (_i) * 4) |
75 | #define AR8327_REG_LED_CTRL(_i) (0x050 + (_i) * 4) |
|
| 76 | #define AR8327_REG_LED_CTRL0 0x050 |
76 | #define AR8327_REG_LED_CTRL0 0x050 |
|
| 77 | #define AR8327_REG_LED_CTRL1 0x054 |
77 | #define AR8327_REG_LED_CTRL1 0x054 |
|
| 78 | #define AR8327_REG_LED_CTRL2 0x058 |
78 | #define AR8327_REG_LED_CTRL2 0x058 |
|
| 79 | #define AR8327_REG_LED_CTRL3 0x05c |
79 | #define AR8327_REG_LED_CTRL3 0x05c |
|
| 80 | #define AR8327_REG_MAC_ADDR0 0x060 |
80 | #define AR8327_REG_MAC_ADDR0 0x060 |
|
| 81 | #define AR8327_REG_MAC_ADDR1 0x064 |
81 | #define AR8327_REG_MAC_ADDR1 0x064 |
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| 82 | |
82 | |
|
| 83 | #define AR8327_REG_MAX_FRAME_SIZE 0x078 |
83 | #define AR8327_REG_MAX_FRAME_SIZE 0x078 |
|
| 84 | #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) |
84 | #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14) |
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| 85 | |
85 | |
|
| 86 | #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) |
86 | #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) |
|
| 87 | #define AR8327_PORT_STATUS_TXFLOW_AUTO BIT(10) |
87 | #define AR8327_PORT_STATUS_TXFLOW_AUTO BIT(10) |
|
| 88 | #define AR8327_PORT_STATUS_RXFLOW_AUTO BIT(11) |
88 | #define AR8327_PORT_STATUS_RXFLOW_AUTO BIT(11) |
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| 89 | |
89 | |
|
| 90 | #define AR8327_REG_HEADER_CTRL 0x098 |
90 | #define AR8327_REG_HEADER_CTRL 0x098 |
|
| 91 | #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) |
91 | #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4) |
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| 92 | |
92 | |
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| 93 | #define AR8327_REG_SGMII_CTRL 0x0e0 |
93 | #define AR8327_REG_SGMII_CTRL 0x0e0 |
|
| 94 | #define AR8327_SGMII_CTRL_EN_PLL BIT(1) |
94 | #define AR8327_SGMII_CTRL_EN_PLL BIT(1) |
|
| 95 | #define AR8327_SGMII_CTRL_EN_RX BIT(2) |
95 | #define AR8327_SGMII_CTRL_EN_RX BIT(2) |
|
| 96 | #define AR8327_SGMII_CTRL_EN_TX BIT(3) |
96 | #define AR8327_SGMII_CTRL_EN_TX BIT(3) |
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| 97 | |
97 | |
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| 98 | #define AR8327_REG_EEE_CTRL 0x100 |
98 | #define AR8327_REG_EEE_CTRL 0x100 |
|
| 99 | #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) |
99 | #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2) |
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| 100 | |
100 | |
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| 101 | #define AR8327_REG_FRAME_ACK_CTRL0 0x210 |
101 | #define AR8327_REG_FRAME_ACK_CTRL0 0x210 |
|
| 102 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN0 BIT(0) |
102 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN0 BIT(0) |
|
| 103 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN0 BIT(1) |
103 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN0 BIT(1) |
|
| 104 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN0 BIT(2) |
104 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN0 BIT(2) |
|
| 105 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN0 BIT(3) |
105 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN0 BIT(3) |
|
| 106 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN0 BIT(4) |
106 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN0 BIT(4) |
|
| 107 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN0 BIT(5) |
107 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN0 BIT(5) |
|
| 108 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN0 BIT(6) |
108 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN0 BIT(6) |
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| 109 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN1 BIT(8) |
109 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN1 BIT(8) |
|
| 110 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN1 BIT(9) |
110 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN1 BIT(9) |
|
| 111 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN1 BIT(10) |
111 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN1 BIT(10) |
|
| 112 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN1 BIT(11) |
112 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN1 BIT(11) |
|
| 113 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN1 BIT(12) |
113 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN1 BIT(12) |
|
| 114 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN1 BIT(13) |
114 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN1 BIT(13) |
|
| 115 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN1 BIT(14) |
115 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN1 BIT(14) |
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| 116 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN2 BIT(16) |
116 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN2 BIT(16) |
|
| 117 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN2 BIT(17) |
117 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN2 BIT(17) |
|
| 118 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN2 BIT(18) |
118 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN2 BIT(18) |
|
| 119 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN2 BIT(19) |
119 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN2 BIT(19) |
|
| 120 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN2 BIT(20) |
120 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN2 BIT(20) |
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| 121 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN2 BIT(21) |
121 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN2 BIT(21) |
|
| 122 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN2 BIT(22) |
122 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN2 BIT(22) |
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| 123 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN3 BIT(24) |
123 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN3 BIT(24) |
|
| 124 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN3 BIT(25) |
124 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN3 BIT(25) |
|
| 125 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN3 BIT(26) |
125 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN3 BIT(26) |
|
| 126 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN3 BIT(27) |
126 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN3 BIT(27) |
|
| 127 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN3 BIT(28) |
127 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN3 BIT(28) |
|
| 128 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN3 BIT(29) |
128 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN3 BIT(29) |
|
| 129 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN3 BIT(30) |
129 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN3 BIT(30) |
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| 130 | |
130 | |
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| 131 | #define AR8327_REG_FRAME_ACK_CTRL1 0x214 |
131 | #define AR8327_REG_FRAME_ACK_CTRL1 0x214 |
|
| 132 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN4 BIT(0) |
132 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN4 BIT(0) |
|
| 133 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN4 BIT(1) |
133 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN4 BIT(1) |
|
| 134 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN4 BIT(2) |
134 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN4 BIT(2) |
|
| 135 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN4 BIT(3) |
135 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN4 BIT(3) |
|
| 136 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN4 BIT(4) |
136 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN4 BIT(4) |
|
| 137 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN4 BIT(5) |
137 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN4 BIT(5) |
|
| 138 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN4 BIT(6) |
138 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN4 BIT(6) |
|
| 139 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN5 BIT(8) |
139 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN5 BIT(8) |
|
| 140 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN5 BIT(9) |
140 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN5 BIT(9) |
|
| 141 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN5 BIT(10) |
141 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN5 BIT(10) |
|
| 142 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN5 BIT(11) |
142 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN5 BIT(11) |
|
| 143 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN5 BIT(12) |
143 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN5 BIT(12) |
|
| 144 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN5 BIT(13) |
144 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN5 BIT(13) |
|
| 145 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN5 BIT(14) |
145 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN5 BIT(14) |
|
| 146 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN6 BIT(16) |
146 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN6 BIT(16) |
|
| 147 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN6 BIT(17) |
147 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN6 BIT(17) |
|
| 148 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN6 BIT(18) |
148 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN6 BIT(18) |
|
| 149 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN6 BIT(19) |
149 | #define AR8327_FRAME_ACK_CTRL_EAPOL_EN6 BIT(19) |
|
| 150 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN6 BIT(20) |
150 | #define AR8327_FRAME_ACK_CTRL_DHCP_EN6 BIT(20) |
|
| 151 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN6 BIT(21) |
151 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN6 BIT(21) |
|
| 152 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN6 BIT(22) |
152 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN6 BIT(22) |
|
| 153 | #define AR8327_FRAME_ACK_CTRL_IGMP_V3_EN BIT(24) |
153 | #define AR8327_FRAME_ACK_CTRL_IGMP_V3_EN BIT(24) |
|
| 154 | #define AR8327_FRAME_ACK_CTRL_PPPOE_EN BIT(25) |
154 | #define AR8327_FRAME_ACK_CTRL_PPPOE_EN BIT(25) |
|
| 155 | |
155 | |
|
| 156 | #define AR8327_REG_FRAME_ACK_CTRL(_i) (0x210 + ((_i) / 4) * 0x4) |
156 | #define AR8327_REG_FRAME_ACK_CTRL(_i) (0x210 + ((_i) / 4) * 0x4) |
|
| 157 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD BIT(0) |
157 | #define AR8327_FRAME_ACK_CTRL_IGMP_MLD BIT(0) |
|
| 158 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN BIT(1) |
158 | #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN BIT(1) |
|
| 159 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE BIT(2) |
159 | #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE BIT(2) |
|
| 160 | #define AR8327_FRAME_ACK_CTRL_EAPOL BIT(3) |
160 | #define AR8327_FRAME_ACK_CTRL_EAPOL BIT(3) |
|
| 161 | #define AR8327_FRAME_ACK_CTRL_DHCP BIT(4) |
161 | #define AR8327_FRAME_ACK_CTRL_DHCP BIT(4) |
|
| 162 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK BIT(5) |
162 | #define AR8327_FRAME_ACK_CTRL_ARP_ACK BIT(5) |
|
| 163 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ BIT(6) |
163 | #define AR8327_FRAME_ACK_CTRL_ARP_REQ BIT(6) |
|
| 164 | #define AR8327_FRAME_ACK_CTRL_S(_i) (((_i) % 4) * 8) |
164 | #define AR8327_FRAME_ACK_CTRL_S(_i) (((_i) % 4) * 8) |
|
| 165 | |
165 | |
|
| 166 | #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) |
166 | #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8) |
|
| 167 | #define AR8327_PORT_VLAN0_DEF_PRI_MASK BITS(0, 3) |
167 | #define AR8327_PORT_VLAN0_DEF_PRI_MASK BITS(0, 3) |
|
| 168 | #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) |
168 | #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12) |
|
| 169 | #define AR8327_PORT_VLAN0_DEF_SVID_S 0 |
169 | #define AR8327_PORT_VLAN0_DEF_SVID_S 0 |
|
| 170 | #define AR8327_PORT_VLAN0_DEF_SPRI BITS(13, 3) |
170 | #define AR8327_PORT_VLAN0_DEF_SPRI BITS(13, 3) |
|
| 171 | #define AR8327_PORT_VLAN0_DEF_SPRI_S 13 |
171 | #define AR8327_PORT_VLAN0_DEF_SPRI_S 13 |
|
| 172 | #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) |
172 | #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12) |
|
| 173 | #define AR8327_PORT_VLAN0_DEF_CVID_S 16 |
173 | #define AR8327_PORT_VLAN0_DEF_CVID_S 16 |
|
| 174 | #define AR8327_PORT_VLAN0_DEF_CPRI BITS(29, 3) |
174 | #define AR8327_PORT_VLAN0_DEF_CPRI BITS(29, 3) |
|
| 175 | #define AR8327_PORT_VLAN0_DEF_CPRI_S 29 |
175 | #define AR8327_PORT_VLAN0_DEF_CPRI_S 29 |
|
| 176 | |
176 | |
|
| 177 | #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) |
177 | #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8) |
|
| 178 | #define AR8327_PORT_VLAN1_VLAN_PRI_PROP BIT(4) |
178 | #define AR8327_PORT_VLAN1_VLAN_PRI_PROP BIT(4) |
|
| 179 | #define AR8327_PORT_VLAN1_PORT_VLAN_PROP BIT(6) |
179 | #define AR8327_PORT_VLAN1_PORT_VLAN_PROP BIT(6) |
|
| 180 | #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) |
180 | #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2) |
|
| 181 | #define AR8327_PORT_VLAN1_OUT_MODE_S 12 |
181 | #define AR8327_PORT_VLAN1_OUT_MODE_S 12 |
|
| 182 | #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 |
182 | #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0 |
|
| 183 | #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 |
183 | #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1 |
|
| 184 | #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 |
184 | #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2 |
|
| 185 | #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 |
185 | #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3 |
|
| 186 | |
186 | |
|
| 187 | #define AR8327_REG_ATU_DATA0 0x600 |
187 | #define AR8327_REG_ATU_DATA0 0x600 |
|
| 188 | #define AR8327_ATU_ADDR0 BITS(0, 8) |
188 | #define AR8327_ATU_ADDR0 BITS(0, 8) |
|
| 189 | #define AR8327_ATU_ADDR0_S 0 |
189 | #define AR8327_ATU_ADDR0_S 0 |
|
| 190 | #define AR8327_ATU_ADDR1 BITS(8, 8) |
190 | #define AR8327_ATU_ADDR1 BITS(8, 8) |
|
| 191 | #define AR8327_ATU_ADDR1_S 8 |
191 | #define AR8327_ATU_ADDR1_S 8 |
|
| 192 | #define AR8327_ATU_ADDR2 BITS(16, 8) |
192 | #define AR8327_ATU_ADDR2 BITS(16, 8) |
|
| 193 | #define AR8327_ATU_ADDR2_S 16 |
193 | #define AR8327_ATU_ADDR2_S 16 |
|
| 194 | #define AR8327_ATU_ADDR3 BITS(24, 8) |
194 | #define AR8327_ATU_ADDR3 BITS(24, 8) |
|
| 195 | #define AR8327_ATU_ADDR3_S 24 |
195 | #define AR8327_ATU_ADDR3_S 24 |
|
| 196 | #define AR8327_REG_ATU_DATA1 0x604 |
196 | #define AR8327_REG_ATU_DATA1 0x604 |
|
| 197 | #define AR8327_ATU_ADDR4 BITS(0, 8) |
197 | #define AR8327_ATU_ADDR4 BITS(0, 8) |
|
| 198 | #define AR8327_ATU_ADDR4_S 0 |
198 | #define AR8327_ATU_ADDR4_S 0 |
|
| 199 | #define AR8327_ATU_ADDR5 BITS(8, 8) |
199 | #define AR8327_ATU_ADDR5 BITS(8, 8) |
|
| 200 | #define AR8327_ATU_ADDR5_S 8 |
200 | #define AR8327_ATU_ADDR5_S 8 |
|
| 201 | #define AR8327_ATU_PORTS BITS(16, 7) |
201 | #define AR8327_ATU_PORTS BITS(16, 7) |
|
| 202 | #define AR8327_ATU_PORTS_S 16 |
- | ||
| 203 | #define AR8327_ATU_PORT0 BIT(16) |
202 | #define AR8327_ATU_PORT0 BIT(16) |
|
| 204 | #define AR8327_ATU_PORT1 BIT(17) |
203 | #define AR8327_ATU_PORT1 BIT(17) |
|
| 205 | #define AR8327_ATU_PORT2 BIT(18) |
204 | #define AR8327_ATU_PORT2 BIT(18) |
|
| 206 | #define AR8327_ATU_PORT3 BIT(19) |
205 | #define AR8327_ATU_PORT3 BIT(19) |
|
| 207 | #define AR8327_ATU_PORT4 BIT(20) |
206 | #define AR8327_ATU_PORT4 BIT(20) |
|
| 208 | #define AR8327_ATU_PORT5 BIT(21) |
207 | #define AR8327_ATU_PORT5 BIT(21) |
|
| 209 | #define AR8327_ATU_PORT6 BIT(22) |
208 | #define AR8327_ATU_PORT6 BIT(22) |
|
| 210 | #define AR8327_REG_ATU_DATA2 0x608 |
209 | #define AR8327_REG_ATU_DATA2 0x608 |
|
| 211 | #define AR8327_ATU_STATUS BITS(0, 4) |
210 | #define AR8327_ATU_STATUS BITS(0, 4) |
|
| 212 | |
211 | |
|
| 213 | #define AR8327_REG_ATU_FUNC 0x60c |
212 | #define AR8327_REG_ATU_FUNC 0x60c |
|
| 214 | #define AR8327_ATU_FUNC_OP BITS(0, 4) |
213 | #define AR8327_ATU_FUNC_OP BITS(0, 4) |
|
| 215 | #define AR8327_ATU_FUNC_OP_NOOP 0x0 |
214 | #define AR8327_ATU_FUNC_OP_NOOP 0x0 |
|
| 216 | #define AR8327_ATU_FUNC_OP_FLUSH 0x1 |
215 | #define AR8327_ATU_FUNC_OP_FLUSH 0x1 |
|
| 217 | #define AR8327_ATU_FUNC_OP_LOAD 0x2 |
216 | #define AR8327_ATU_FUNC_OP_LOAD 0x2 |
|
| 218 | #define AR8327_ATU_FUNC_OP_PURGE 0x3 |
217 | #define AR8327_ATU_FUNC_OP_PURGE 0x3 |
|
| 219 | #define AR8327_ATU_FUNC_OP_FLUSH_UNLOCKED 0x4 |
218 | #define AR8327_ATU_FUNC_OP_FLUSH_UNLOCKED 0x4 |
|
| 220 | #define AR8327_ATU_FUNC_OP_FLUSH_PORT 0x5 |
219 | #define AR8327_ATU_FUNC_OP_FLUSH_PORT 0x5 |
|
| 221 | #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 |
220 | #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6 |
|
| 222 | #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 |
221 | #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7 |
|
| 223 | #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 |
222 | #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8 |
|
| 224 | #define AR8327_ATU_PORT_NUM BITS(8, 4) |
223 | #define AR8327_ATU_PORT_NUM BITS(8, 4) |
|
| 225 | #define AR8327_ATU_PORT_NUM_S 8 |
224 | #define AR8327_ATU_PORT_NUM_S 8 |
|
| 226 | #define AR8327_ATU_FUNC_BUSY BIT(31) |
225 | #define AR8327_ATU_FUNC_BUSY BIT(31) |
|
| 227 | |
226 | |
|
| 228 | #define AR8327_REG_VTU_FUNC0 0x0610 |
227 | #define AR8327_REG_VTU_FUNC0 0x0610 |
|
| 229 | #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) |
228 | #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14) |
|
| 230 | #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) |
229 | #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) |
|
| 231 | #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 |
230 | #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0 |
|
| 232 | #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 |
231 | #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1 |
|
| 233 | #define AR8327_VTU_FUNC0_EG_MODE_TAG 2 |
232 | #define AR8327_VTU_FUNC0_EG_MODE_TAG 2 |
|
| 234 | #define AR8327_VTU_FUNC0_EG_MODE_NOT 3 |
233 | #define AR8327_VTU_FUNC0_EG_MODE_NOT 3 |
|
| 235 | #define AR8327_VTU_FUNC0_IVL BIT(19) |
234 | #define AR8327_VTU_FUNC0_IVL BIT(19) |
|
| 236 | #define AR8327_VTU_FUNC0_VALID BIT(20) |
235 | #define AR8327_VTU_FUNC0_VALID BIT(20) |
|
| 237 | |
236 | |
|
| 238 | #define AR8327_REG_VTU_FUNC1 0x0614 |
237 | #define AR8327_REG_VTU_FUNC1 0x0614 |
|
| 239 | #define AR8327_VTU_FUNC1_OP BITS(0, 3) |
238 | #define AR8327_VTU_FUNC1_OP BITS(0, 3) |
|
| 240 | #define AR8327_VTU_FUNC1_OP_NOOP 0 |
239 | #define AR8327_VTU_FUNC1_OP_NOOP 0 |
|
| 241 | #define AR8327_VTU_FUNC1_OP_FLUSH 1 |
240 | #define AR8327_VTU_FUNC1_OP_FLUSH 1 |
|
| 242 | #define AR8327_VTU_FUNC1_OP_LOAD 2 |
241 | #define AR8327_VTU_FUNC1_OP_LOAD 2 |
|
| 243 | #define AR8327_VTU_FUNC1_OP_PURGE 3 |
242 | #define AR8327_VTU_FUNC1_OP_PURGE 3 |
|
| 244 | #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 |
243 | #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4 |
|
| 245 | #define AR8327_VTU_FUNC1_OP_GET_NEXT 5 |
244 | #define AR8327_VTU_FUNC1_OP_GET_NEXT 5 |
|
| 246 | #define AR8327_VTU_FUNC1_OP_GET_ONE 6 |
245 | #define AR8327_VTU_FUNC1_OP_GET_ONE 6 |
|
| 247 | #define AR8327_VTU_FUNC1_FULL BIT(4) |
246 | #define AR8327_VTU_FUNC1_FULL BIT(4) |
|
| 248 | #define AR8327_VTU_FUNC1_PORT BIT(8, 4) |
247 | #define AR8327_VTU_FUNC1_PORT BIT(8, 4) |
|
| 249 | #define AR8327_VTU_FUNC1_PORT_S 8 |
248 | #define AR8327_VTU_FUNC1_PORT_S 8 |
|
| 250 | #define AR8327_VTU_FUNC1_VID BIT(16, 12) |
249 | #define AR8327_VTU_FUNC1_VID BIT(16, 12) |
|
| 251 | #define AR8327_VTU_FUNC1_VID_S 16 |
250 | #define AR8327_VTU_FUNC1_VID_S 16 |
|
| 252 | #define AR8327_VTU_FUNC1_BUSY BIT(31) |
251 | #define AR8327_VTU_FUNC1_BUSY BIT(31) |
|
| 253 | |
252 | |
|
| 254 | #define AR8327_REG_ARL_CTRL 0x0618 |
253 | #define AR8327_REG_ARL_CTRL 0x0618 |
|
| 255 | |
254 | |
|
| 256 | #define AR8327_REG_FWD_CTRL0 0x620 |
255 | #define AR8327_REG_FWD_CTRL0 0x620 |
|
| 257 | #define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10) |
256 | #define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10) |
|
| 258 | #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) |
257 | #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4) |
|
| 259 | #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 |
258 | #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4 |
|
| 260 | |
259 | |
|
| 261 | #define AR8327_REG_FWD_CTRL1 0x624 |
260 | #define AR8327_REG_FWD_CTRL1 0x624 |
|
| 262 | #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) |
261 | #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7) |
|
| 263 | #define AR8327_FWD_CTRL1_UC_FLOOD_S 0 |
262 | #define AR8327_FWD_CTRL1_UC_FLOOD_S 0 |
|
| 264 | #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) |
263 | #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7) |
|
| 265 | #define AR8327_FWD_CTRL1_MC_FLOOD_S 8 |
264 | #define AR8327_FWD_CTRL1_MC_FLOOD_S 8 |
|
| 266 | #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) |
265 | #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7) |
|
| 267 | #define AR8327_FWD_CTRL1_BC_FLOOD_S 16 |
266 | #define AR8327_FWD_CTRL1_BC_FLOOD_S 16 |
|
| 268 | #define AR8327_FWD_CTRL1_IGMP BITS(24, 7) |
267 | #define AR8327_FWD_CTRL1_IGMP BITS(24, 7) |
|
| 269 | #define AR8327_FWD_CTRL1_IGMP_S 24 |
268 | #define AR8327_FWD_CTRL1_IGMP_S 24 |
|
| 270 | |
269 | |
|
| 271 | #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) |
270 | #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc) |
|
| 272 | #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) |
271 | #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7) |
|
| 273 | #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) |
272 | #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2) |
|
| 274 | #define AR8327_PORT_LOOKUP_IN_MODE_S 8 |
273 | #define AR8327_PORT_LOOKUP_IN_MODE_S 8 |
|
| 275 | #define AR8327_PORT_LOOKUP_STATE BITS(16, 3) |
274 | #define AR8327_PORT_LOOKUP_STATE BITS(16, 3) |
|
| 276 | #define AR8327_PORT_LOOKUP_STATE_S 16 |
275 | #define AR8327_PORT_LOOKUP_STATE_S 16 |
|
| 277 | #define AR8327_PORT_LOOKUP_LEARN BIT(20) |
276 | #define AR8327_PORT_LOOKUP_LEARN BIT(20) |
|
| 278 | #define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25) |
277 | #define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25) |
|
| 279 | |
278 | |
|
| 280 | #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) |
279 | #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc) |
|
| - | 280 | |
||
| - | 281 | #define AR8327_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) |
||
| - | 282 | #define AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF BITS(0, 4) |
||
| - | 283 | #define AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S 0 |
||
| - | 284 | #define AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF BITS(4, 4) |
||
| - | 285 | #define AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S 4 |
||
| - | 286 | #define AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF BITS(8, 4) |
||
| - | 287 | #define AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S 8 |
||
| - | 288 | #define AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF BITS(12, 4) |
||
| - | 289 | #define AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S 12 |
||
| - | 290 | #define AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF BITS(16, 4) |
||
| - | 291 | #define AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF_S 16 |
||
| - | 292 | #define AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF BITS(20, 4) |
||
| - | 293 | #define AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF_S 20 |
||
| - | 294 | #define AR8327_PORT_HOL_CTRL0_EG_PORT_BUF BITS(24, 6) |
||
| - | 295 | #define AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S 24 |
||
| 281 | |
296 | |
|
| - | 297 | #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) |
||
| - | 298 | #define AR8327_PORT_HOL_CTRL1_ING_BUF BITS(0, 4) |
||
| - | 299 | #define AR8327_PORT_HOL_CTRL1_ING_BUF_S 0 |
||
| - | 300 | #define AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) |
||
| - | 301 | #define AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) |
||
| 282 | #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) |
302 | #define AR8327_PORT_HOL_CTRL1_WRED_EN BIT(8) |
|
| 283 | #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) |
303 | #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) |
|
| 284 | |
304 | |
|
| 285 | #define AR8337_PAD_MAC06_EXCHANGE_EN BIT(31) |
305 | #define AR8337_PAD_MAC06_EXCHANGE_EN BIT(31) |
|
| 286 | |
- | ||
| 287 | #define AR8327_PHY_MODE_SEL 0x12 |
- | ||
| 288 | #define AR8327_PHY_MODE_SEL_RGMII BIT(3) |
- | ||
| 289 | #define AR8327_PHY_TEST_CTRL 0x0 |
- | ||
| 290 | #define AR8327_PHY_TEST_CTRL_RGMII_RX_DELAY BIT(15) |
- | ||
| 291 | #define AR8327_PHY_SYS_CTRL 0x5 |
- | ||
| 292 | #define AR8327_PHY_SYS_CTRL_RGMII_TX_DELAY BIT(8) |
- | ||
| 293 | |
306 | |
|
| 294 | enum ar8327_led_pattern { |
307 | enum ar8327_led_pattern { |
|
| 295 | AR8327_LED_PATTERN_OFF = 0, |
308 | AR8327_LED_PATTERN_OFF = 0, |
|
| 296 | AR8327_LED_PATTERN_BLINK, |
309 | AR8327_LED_PATTERN_BLINK, |
|
| 297 | AR8327_LED_PATTERN_ON, |
310 | AR8327_LED_PATTERN_ON, |
|
| 298 | AR8327_LED_PATTERN_RULE, |
311 | AR8327_LED_PATTERN_RULE, |
|
| 299 | }; |
312 | }; |
|
| 300 | |
313 | |
|
| 301 | struct ar8327_led_entry { |
314 | struct ar8327_led_entry { |
|
| 302 | unsigned reg; |
315 | unsigned reg; |
|
| 303 | unsigned shift; |
316 | unsigned shift; |
|
| 304 | }; |
317 | }; |
|
| 305 | |
318 | |
|
| 306 | struct ar8327_led { |
319 | struct ar8327_led { |
|
| 307 | struct led_classdev cdev; |
320 | struct led_classdev cdev; |
|
| 308 | struct ar8xxx_priv *sw_priv; |
321 | struct ar8xxx_priv *sw_priv; |
|
| 309 | |
322 | |
|
| 310 | char *name; |
323 | char *name; |
|
| 311 | bool active_low; |
324 | bool active_low; |
|
| 312 | u8 led_num; |
325 | u8 led_num; |
|
| 313 | enum ar8327_led_mode mode; |
326 | enum ar8327_led_mode mode; |
|
| 314 | |
327 | |
|
| 315 | struct mutex mutex; |
328 | struct mutex mutex; |
|
| 316 | spinlock_t lock; |
329 | spinlock_t lock; |
|
| 317 | struct work_struct led_work; |
330 | struct work_struct led_work; |
|
| 318 | bool enable_hw_mode; |
331 | bool enable_hw_mode; |
|
| 319 | enum ar8327_led_pattern pattern; |
332 | enum ar8327_led_pattern pattern; |
|
| 320 | }; |
333 | }; |
|
| 321 | |
334 | |
|
| 322 | struct ar8327_data { |
335 | struct ar8327_data { |
|
| 323 | u32 port0_status; |
336 | u32 port0_status; |
|
| 324 | u32 port6_status; |
337 | u32 port6_status; |
|
| 325 | |
338 | |
|
| 326 | struct ar8327_led **leds; |
339 | struct ar8327_led **leds; |
|
| 327 | unsigned int num_leds; |
340 | unsigned int num_leds; |
|
| 328 | |
341 | |
|
| 329 | /* all fields below are cleared on reset */ |
342 | /* all fields below are cleared on reset */ |
|
| 330 | bool eee[AR8XXX_NUM_PHYS]; |
343 | bool eee[AR8XXX_NUM_PHYS]; |
|
| 331 | }; |
344 | }; |
|
| 332 | |
345 | |
|
| 333 | #endif |
346 | #endif |
|
| 334 | |
347 | |
|