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/branches/gl-inet/package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/Makefile
@@ -0,0 +1,13 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
 
obj-y += reset.o
obj-y += timer.o
obj-y += clock.o
obj-y += pinmux.o
/branches/gl-inet/package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/clock.c
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#include <common.h>
#include <asm/arch/sysctl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
 
typedef struct {
unsigned short mhz;
unsigned char refdiv;
unsigned char outdiv;
unsigned int fbdiv;
unsigned short bwadj;
unsigned short sfreq;
unsigned int sslope;
} PLL_CONFIG;
 
const PLL_CONFIG C_PLL_CONFIG[] = {
{ 500, 1, 2, 3932160, 119, 208, 189 }, // 500 MHz
{ 525, 2, 1, 4128768, 125, 139, 297 }, // 525 MHz
{ 550, 2, 1, 4325376, 131, 139, 311 }, // 550 MHz
{ 575, 2, 1, 4521984, 137, 139, 326 }, // 575 MHz
{ 600, 2, 1, 4718592, 143, 138, 339 }, // 600 MHz
{ 625, 1, 1, 3276800, 99, 208, 157 }, // 625 MHz
{ 650, 1, 1, 3407872, 103, 208, 164 }, // 650 MHz
{ 675, 1, 1, 3538944, 107, 208, 170 }, // 675 MHz
{ 700, 0, 0, 917504, 27, 416, 22 }, // 700 MHz
{ 725, 1, 1, 3801088, 115, 208, 182 }, // 725 MHz
{ 750, 0, 0, 983040, 29, 416, 23 }, // 750 MHz
{ 775, 3, 0, 4063232, 123, 104, 390 }, // 775 MHz
{ 800, 3, 0, 4194304, 127, 104, 403 }, // 800 MHz
{ 825, 3, 0, 4325376, 131, 104, 415 }, // 825 MHz
{ 850, 2, 0, 3342336, 101, 139, 241 }, // 850 MHz
{ 875, 2, 0, 3440640, 104, 139, 248 }, // 875 MHz
{ 900, 2, 0, 3538944, 107, 139, 255 }, // 900 MHz
{ 925, 2, 0, 3637248, 110, 139, 262 }, // 925 MHz
{ 950, 2, 0, 3735552, 113, 139, 269 }, // 950 MHz
{ 975, 2, 0, 3833856, 116, 139, 276 }, // 975 MHz
{ 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz
};
 
#define PLL_BYPASS (1<<1)
#define SAT_ENABLE (1<<3)
 
#define PLL_OUTDIV_SHIFT 4
#define PLL_REFDIV_SHIFT 8
#define PLL_BWADJ_SHIFT 16
 
#define PLL_LOW_FREQ 500
#define PLL_FREQ_STEP 25
static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,
int sfreq, int sslope)
{
setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);
udelay(10);
reset_block(SYS_CTRL_RST_PLLA, 1);
udelay(10);
 
writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |
SAT_ENABLE | PLL_BYPASS,
SYS_CTRL_PLLA_CTRL0);
 
writel(fbdiv, SYS_CTRL_PLLA_CTRL1);
writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);
writel(sslope, SYS_CTRL_PLLA_CTRL3);
 
udelay(10); // 5us delay required (from TCI datasheet), use 10us
 
reset_block(SYS_CTRL_RST_PLLA, 0);
 
udelay(100); // Delay for PLL to lock
 
printf(" plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0));
printf(" plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1));
printf(" plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2));
printf(" plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3));
 
clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass
puts("\nPLLA Set\n");
}
 
int plla_set_config(int mhz)
{
int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;
const PLL_CONFIG *cfg;
 
if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {
debug("Freq %d MHz out of range, default to lowest\n", mhz);
index = 0;
}
cfg = &C_PLL_CONFIG[index];
 
printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz);
plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,
cfg->sfreq, cfg->sslope);
 
return cfg->mhz;
}
 
/branches/gl-inet/package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/pinmux.c
@@ -0,0 +1,43 @@
#include <common.h>
#include <asm/arch/pinmux.h>
 
void pinmux_set(int bank, int pin, int func)
{
u32 reg;
u32 base;
/* TODO: check parameters */
 
if (bank == PINMUX_BANK_MFA)
base = SYS_CONTROL_BASE;
else
base = SEC_CONTROL_BASE;
 
clrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin));
clrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin));
clrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin));
clrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin));
clrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin));
 
switch (func) {
case PINMUX_GPIO:
default:
return;
break;
case PINMUX_2:
reg = base + PINMUX_SECONDARY_SEL;
break;
case PINMUX_3:
reg = base + PINMUX_TERTIARY_SEL;
break;
case PINMUX_4:
reg = base + PINMUX_QUATERNARY_SEL;
break;
case PINMUX_DEBUG:
reg = base + PINMUX_DEBUG_SEL;
break;
case PINMUX_ALT:
reg = base + PINMUX_ALTERNATIVE_SEL;
break;
}
setbits_le32(reg, BIT(pin));
}
/branches/gl-inet/package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/reset.c
@@ -0,0 +1,91 @@
#include <common.h>
#include <asm/arch/sysctl.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/clock.h>
 
void reset_cpu(ulong addr)
{
u32 value;
 
// Assert reset to cores as per power on defaults
// Don't touch the DDR interface as things will come to an impromptu stop
// NB Possibly should be asserting reset for PLLB, but there are timing
// concerns here according to the docs
 
value =
BIT(SYS_CTRL_RST_COPRO ) |
BIT(SYS_CTRL_RST_USBHS ) |
BIT(SYS_CTRL_RST_USBHSPHYA ) |
BIT(SYS_CTRL_RST_MACA ) |
BIT(SYS_CTRL_RST_PCIEA ) |
BIT(SYS_CTRL_RST_SGDMA ) |
BIT(SYS_CTRL_RST_CIPHER ) |
BIT(SYS_CTRL_RST_SATA ) |
BIT(SYS_CTRL_RST_SATA_LINK ) |
BIT(SYS_CTRL_RST_SATA_PHY ) |
BIT(SYS_CTRL_RST_PCIEPHY ) |
BIT(SYS_CTRL_RST_STATIC ) |
BIT(SYS_CTRL_RST_UART1 ) |
BIT(SYS_CTRL_RST_UART2 ) |
BIT(SYS_CTRL_RST_MISC ) |
BIT(SYS_CTRL_RST_I2S ) |
BIT(SYS_CTRL_RST_SD ) |
BIT(SYS_CTRL_RST_MACB ) |
BIT(SYS_CTRL_RST_PCIEB ) |
BIT(SYS_CTRL_RST_VIDEO ) |
BIT(SYS_CTRL_RST_USBHSPHYB ) |
BIT(SYS_CTRL_RST_USBDEV );
 
writel(value, SYS_CTRL_RST_SET_CTRL);
 
// Release reset to cores as per power on defaults
writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
 
// Disable clocks to cores as per power-on defaults - must leave DDR
// related clocks enabled otherwise we'll stop rather abruptly.
value =
BIT(SYS_CTRL_CLK_COPRO) |
BIT(SYS_CTRL_CLK_DMA) |
BIT(SYS_CTRL_CLK_CIPHER) |
BIT(SYS_CTRL_CLK_SD) |
BIT(SYS_CTRL_CLK_SATA) |
BIT(SYS_CTRL_CLK_I2S) |
BIT(SYS_CTRL_CLK_USBHS) |
BIT(SYS_CTRL_CLK_MAC) |
BIT(SYS_CTRL_CLK_PCIEA) |
BIT(SYS_CTRL_CLK_STATIC) |
BIT(SYS_CTRL_CLK_MACB) |
BIT(SYS_CTRL_CLK_PCIEB) |
BIT(SYS_CTRL_CLK_REF600) |
BIT(SYS_CTRL_CLK_USBDEV);
 
writel(value, SYS_CTRL_CLK_CLR_CTRL);
 
// Enable clocks to cores as per power-on defaults
 
// Set sys-control pin mux'ing as per power-on defaults
 
writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);
writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);
writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);
writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);
 
writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);
writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);
writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);
writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);
 
// No need to save any state, as the ROM loader can determine whether reset
// is due to power cycling or programatic action, just hit the (self-
// clearing) CPU reset bit of the block reset register
value =
BIT(SYS_CTRL_RST_SCU) |
BIT(SYS_CTRL_RST_ARM0) |
BIT(SYS_CTRL_RST_ARM1);
 
writel(value, SYS_CTRL_RST_SET_CTRL);
}
/branches/gl-inet/package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/timer.c
@@ -0,0 +1,129 @@
/*
* (C) Copyright 2004
* Texas Instruments
* Richard Woodruff <r-woodruff2@ti.com>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
 
#include <common.h>
#include <asm/io.h>
 
#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4)))
#define TIMER_LOAD_VAL 0xFFFFFF
 
/* macro to read the 32 bit timer */
#define READ_TIMER (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \
/ (TIMER_CLOCK / CONFIG_SYS_HZ)
 
#define READ_TIMER_HW (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR))
 
DECLARE_GLOBAL_DATA_PTR;
 
int timer_init (void)
{
int32_t val;
 
/* Start the counter ticking up */
writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD); /* reload value on overflow*/
 
val = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) |
(TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) |
(TIMER_ENABLE << TIMER_ENABLE_SHIFT); /* mask to enable timer*/
writel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL); /* start timer */
 
/* reset time */
gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */
gd->arch.tbl = 0; /* start "advancing" time stamp */
 
return(0);
}
/*
* timer without interrupts
*/
ulong get_timer (ulong base)
{
return get_timer_masked () - base;
}
 
/* delay x useconds AND preserve advance timestamp value */
void __udelay (unsigned long usec)
{
ulong tmo, tmp;
 
if (usec > 100000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
 
tmp = get_timer (0); /* get current timestamp */
while (get_timer (tmp) < tmo)/* loop till event */
/*NOP*/;
} else { /* else small number, convert to hw ticks */
tmo = usec * (TIMER_CLOCK / 1000) / 1000;
/* timeout is no more than 0.1s, and the hw timer will roll over at most once */
tmp = READ_TIMER_HW;
while (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */
/*NOP*/;
}
}
 
ulong get_timer_masked (void)
{
ulong now = READ_TIMER; /* current tick value */
 
if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
/* move stamp fordward with absoulte diff ticks */
gd->arch.tbl += (now - gd->arch.lastinc);
} else {
/* we have rollover of incrementer */
gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- gd->arch.lastinc) + now;
}
gd->arch.lastinc = now;
return gd->arch.tbl;
}
 
 
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}