| /branches/gl-inet/target/linux/sunxi/patches-4.9/0071-arm-sun8i-sunxi-h3-h5-add-dwmac-sun8i-ethernet-drive.patch |
|---|
| @@ -0,0 +1,67 @@ |
|---|
| From 0eba511a3cac29d6338b22b5b727f40cf8d163df Mon Sep 17 00:00:00 2001 |
| From: Corentin Labbe <clabbe.montjoie@gmail.com> |
| Date: Wed, 31 May 2017 09:18:38 +0200 |
| Subject: arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver |
| |
| The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 |
| speed. |
| |
| This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree. |
| SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set. |
| |
| Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> |
| Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
| --- |
| arch/arm/boot/dts/sunxi-h3-h5.dtsi | 34 ++++++++++++++++++++++++++++++++++ |
| 1 file changed, 34 insertions(+) |
| |
| --- a/arch/arm/boot/dts/sun8i-h3.dtsi |
| +++ b/arch/arm/boot/dts/sun8i-h3.dtsi |
| @@ -333,6 +333,14 @@ |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| |
| + emac_rgmii_pins: emac0 { |
| + pins = "PD0", "PD1", "PD2", "PD3", "PD4", |
| + "PD5", "PD7", "PD8", "PD9", "PD10", |
| + "PD12", "PD13", "PD15", "PD16", "PD17"; |
| + function = "emac"; |
| + drive-strength = <40>; |
| + }; |
| + |
| i2c0_pins: i2c0 { |
| allwinner,pins = "PA11", "PA12"; |
| allwinner,function = "i2c0"; |
| @@ -431,6 +439,32 @@ |
| clocks = <&osc24M>; |
| }; |
| |
| + emac: ethernet@1c30000 { |
| + compatible = "allwinner,sun8i-h3-emac"; |
| + syscon = <&syscon>; |
| + reg = <0x01c30000 0x104>; |
| + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| + interrupt-names = "macirq"; |
| + resets = <&ccu RST_BUS_EMAC>; |
| + reset-names = "stmmaceth"; |
| + clocks = <&ccu CLK_BUS_EMAC>; |
| + clock-names = "stmmaceth"; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + status = "disabled"; |
| + |
| + mdio: mdio { |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + int_mii_phy: ethernet-phy@1 { |
| + compatible = "ethernet-phy-ieee802.3-c22"; |
| + reg = <1>; |
| + clocks = <&ccu CLK_BUS_EPHY>; |
| + resets = <&ccu RST_BUS_EPHY>; |
| + }; |
| + }; |
| + }; |
| + |
| wdt0: watchdog@01c20ca0 { |
| compatible = "allwinner,sun6i-a31-wdt"; |
| reg = <0x01c20ca0 0x20>; |
