| /branches/18.06.1/target/linux/ramips/dts/mt7621.dtsi |
|---|
| @@ -1,5 +1,4 @@ |
|---|
| #include <dt-bindings/interrupt-controller/mips-gic.h> |
| #include <dt-bindings/clock/mt7621-clk.h> |
| |
| / { |
| #address-cells = <1>; |
| @@ -7,23 +6,16 @@ |
|---|
| compatible = "mediatek,mt7621-soc"; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "mips,mips1004Kc"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "mips,mips1004Kc"; |
| reg = <1>; |
| }; |
| }; |
| |
| cpuintc: cpuintc { |
| cpuintc: cpuintc@0 { |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| @@ -34,14 +26,15 @@ |
|---|
| serial0 = &uartlite; |
| }; |
| |
| pll: pll { |
| compatible = "mediatek,mt7621-pll", "syscon"; |
| cpuclock: cpuclock@0 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| |
| #clock-cells = <1>; |
| clock-output-names = "cpu", "bus"; |
| /* FIXME: there should be way to detect this */ |
| clock-frequency = <880000000>; |
| }; |
| |
| sysclock: sysclock { |
| sysclock: sysclock@0 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| |
| @@ -138,9 +131,9 @@ |
|---|
| status = "disabled"; |
| }; |
| |
| systick: systick@500 { |
| systick: systick@d00 { |
| compatible = "ralink,mt7621-systick", "ralink,cevt-systick"; |
| reg = <0x500 0x10>; |
| reg = <0xd00 0x10>; |
| |
| resets = <&rstctrl 28>; |
| reset-names = "intc"; |
| @@ -151,23 +144,24 @@ |
|---|
| |
| memc: memc@5000 { |
| compatible = "mtk,mt7621-memc"; |
| reg = <0x5000 0x1000>; |
| reg = <0x300 0x100>; |
| }; |
| |
| cpc: cpc@1fbf0000 { |
| compatible = "mtk,mt7621-cpc"; |
| reg = <0x1fbf0000 0x8000>; |
| compatible = "mtk,mt7621-cpc"; |
| reg = <0x1fbf0000 0x8000>; |
| }; |
| |
| mc: mc@1fbf8000 { |
| compatible = "mtk,mt7621-mc"; |
| reg = <0x1fbf8000 0x8000>; |
| }; |
| compatible = "mtk,mt7621-mc"; |
| reg = <0x1fbf8000 0x8000>; |
| }; |
| |
| uartlite: uartlite@c00 { |
| compatible = "ns16550a"; |
| reg = <0xc00 0x100>; |
| |
| clocks = <&sysclock>; |
| clock-frequency = <50000000>; |
| |
| interrupt-parent = <&gic>; |
| @@ -178,42 +172,6 @@ |
|---|
| no-loopback-test; |
| }; |
| |
| uartlite2: uartlite2@d00 { |
| compatible = "ns16550a"; |
| reg = <0xd00 0x100>; |
| |
| clock-frequency = <50000000>; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>; |
| |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| |
| status = "disabled"; |
| }; |
| |
| uartlite3: uartlite3@e00 { |
| compatible = "ns16550a"; |
| reg = <0xe00 0x100>; |
| |
| clock-frequency = <50000000>; |
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>; |
| |
| reg-shift = <2>; |
| reg-io-width = <4>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart3_pins>; |
| |
| status = "disabled"; |
| }; |
| |
| spi0: spi@b00 { |
| status = "disabled"; |
| |
| @@ -220,7 +178,7 @@ |
|---|
| compatible = "ralink,mt7621-spi"; |
| reg = <0xb00 0x100>; |
| |
| clocks = <&pll MT7621_CLK_BUS>; |
| clocks = <&sysclock>; |
| |
| resets = <&rstctrl 18>; |
| reset-names = "spi"; |
| @@ -275,15 +233,15 @@ |
|---|
| state_default: pinctrl0 { |
| }; |
| |
| i2c_pins: i2c_pins { |
| i2c_pins { |
| i2c_pins: i2c { |
| i2c { |
| ralink,group = "i2c"; |
| ralink,function = "i2c"; |
| }; |
| }; |
| |
| spi_pins: spi_pins { |
| spi_pins { |
| spi_pins: spi { |
| spi { |
| ralink,group = "spi"; |
| ralink,function = "spi"; |
| }; |
| @@ -376,14 +334,9 @@ |
|---|
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&sdhci_pins>; |
| }; |
| |
| xhci: xhci@1E1C0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| |
| compatible = "mediatek,mt8173-xhci"; |
| @@ -396,25 +349,6 @@ |
|---|
| |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; |
| |
| /* |
| * Port 1 of both hubs is one usb slot and referenced here. |
| * The binding doesn't allow to address individual hubs. |
| * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci. |
| */ |
| xhci_ehci_port1: port@1 { |
| reg = <1>; |
| #trigger-source-cells = <0>; |
| }; |
| |
| /* |
| * Only the second usb hub has a second port. That port serves |
| * ehci and ohci. |
| */ |
| ehci_port2: port@2 { |
| reg = <2>; |
| #trigger-source-cells = <0>; |
| }; |
| }; |
| |
| gic: interrupt-controller@1fbc0000 { |
| @@ -429,7 +363,7 @@ |
|---|
| timer { |
| compatible = "mti,gic-timer"; |
| interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
| clocks = <&pll MT7621_CLK_CPU>; |
| clocks = <&cpuclock>; |
| }; |
| }; |
| |
| @@ -440,14 +374,26 @@ |
|---|
| bank-width = <2>; |
| reg = <0x1e003000 0x800 |
| 0x1e003800 0x800>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| hnat: hnat@1e100000 { |
| compatible = "mediatek,mt7623-hnat"; |
| reg = <0x1e100000 0x10000>; |
| mtketh-ppd = "eth0"; |
| mtketh-lan = "eth0"; |
| mtketh-wan = "eth0"; |
| resets = <&rstctrl 0>; |
| reset-names = "mtketh"; |
| }; |
| |
| ethernet: ethernet@1e100000 { |
| compatible = "mediatek,mt7621-eth"; |
| reg = <0x1e100000 0x10000>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| #size-cells = <0>; |
| |
| resets = <&rstctrl 6 &rstctrl 23>; |
| reset-names = "fe", "eth"; |
| @@ -466,16 +412,6 @@ |
|---|
| phy-mode = "rgmii"; |
| }; |
| }; |
| |
| hnat: hnat@0 { |
| compatible = "mediatek,mt7623-hnat"; |
| reg = <0 0x10000>; |
| mtketh-ppd = "eth0"; |
| mtketh-lan = "eth0"; |
| mtketh-wan = "eth0"; |
| resets = <&rstctrl 0>; |
| reset-names = "mtketh"; |
| }; |
| }; |
| |
| gsw: gsw@1e110000 { |
| @@ -516,31 +452,31 @@ |
|---|
| clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; |
| clock-names = "pcie0", "pcie1", "pcie2"; |
| |
| pcie0: pcie@0,0 { |
| pcie0 { |
| reg = <0x0000 0 0 0 0>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges; |
| device_type = "pci"; |
| }; |
| |
| pcie1: pcie@1,0 { |
| pcie1 { |
| reg = <0x0800 0 0 0 0>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges; |
| device_type = "pci"; |
| }; |
| |
| pcie2: pcie@2,0 { |
| pcie2 { |
| reg = <0x1000 0 0 0 0>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges; |
| device_type = "pci"; |
| }; |
| }; |
| }; |
