/branches/18.06.1/target/linux/ramips/dts/mt7621.dtsi |
@@ -0,0 +1,546 @@ |
#include <dt-bindings/interrupt-controller/mips-gic.h> |
#include <dt-bindings/clock/mt7621-clk.h> |
|
/ { |
#address-cells = <1>; |
#size-cells = <1>; |
compatible = "mediatek,mt7621-soc"; |
|
cpus { |
#address-cells = <1>; |
#size-cells = <0>; |
|
cpu@0 { |
device_type = "cpu"; |
compatible = "mips,mips1004Kc"; |
reg = <0>; |
}; |
|
cpu@1 { |
device_type = "cpu"; |
compatible = "mips,mips1004Kc"; |
reg = <1>; |
}; |
}; |
|
cpuintc: cpuintc { |
#address-cells = <0>; |
#interrupt-cells = <1>; |
interrupt-controller; |
compatible = "mti,cpu-interrupt-controller"; |
}; |
|
aliases { |
serial0 = &uartlite; |
}; |
|
pll: pll { |
compatible = "mediatek,mt7621-pll", "syscon"; |
|
#clock-cells = <1>; |
clock-output-names = "cpu", "bus"; |
}; |
|
sysclock: sysclock { |
#clock-cells = <0>; |
compatible = "fixed-clock"; |
|
/* FIXME: there should be way to detect this */ |
clock-frequency = <50000000>; |
}; |
|
|
|
palmbus: palmbus@1E000000 { |
compatible = "palmbus"; |
reg = <0x1E000000 0x100000>; |
ranges = <0x0 0x1E000000 0x0FFFFF>; |
|
#address-cells = <1>; |
#size-cells = <1>; |
|
sysc: sysc@0 { |
compatible = "mtk,mt7621-sysc"; |
reg = <0x0 0x100>; |
}; |
|
wdt: wdt@100 { |
compatible = "mediatek,mt7621-wdt"; |
reg = <0x100 0x100>; |
}; |
|
gpio@600 { |
#address-cells = <1>; |
#size-cells = <0>; |
|
compatible = "mtk,mt7621-gpio"; |
reg = <0x600 0x100>; |
|
gpio0: bank@0 { |
reg = <0>; |
compatible = "mtk,mt7621-gpio-bank"; |
gpio-controller; |
#gpio-cells = <2>; |
}; |
|
gpio1: bank@1 { |
reg = <1>; |
compatible = "mtk,mt7621-gpio-bank"; |
gpio-controller; |
#gpio-cells = <2>; |
}; |
|
gpio2: bank@2 { |
reg = <2>; |
compatible = "mtk,mt7621-gpio-bank"; |
gpio-controller; |
#gpio-cells = <2>; |
}; |
}; |
|
i2c: i2c@900 { |
compatible = "mediatek,mt7621-i2c"; |
reg = <0x900 0x100>; |
|
clocks = <&sysclock>; |
|
resets = <&rstctrl 16>; |
reset-names = "i2c"; |
|
#address-cells = <1>; |
#size-cells = <0>; |
|
status = "disabled"; |
|
pinctrl-names = "default"; |
pinctrl-0 = <&i2c_pins>; |
}; |
|
i2s: i2s@a00 { |
compatible = "mediatek,mt7621-i2s"; |
reg = <0xa00 0x100>; |
|
clocks = <&sysclock>; |
|
resets = <&rstctrl 17>; |
reset-names = "i2s"; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>; |
|
txdma-req = <2>; |
rxdma-req = <3>; |
|
dmas = <&gdma 4>, |
<&gdma 6>; |
dma-names = "tx", "rx"; |
|
status = "disabled"; |
}; |
|
systick: systick@500 { |
compatible = "ralink,mt7621-systick", "ralink,cevt-systick"; |
reg = <0x500 0x10>; |
|
resets = <&rstctrl 28>; |
reset-names = "intc"; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>; |
}; |
|
memc: memc@5000 { |
compatible = "mtk,mt7621-memc"; |
reg = <0x5000 0x1000>; |
}; |
|
cpc: cpc@1fbf0000 { |
compatible = "mtk,mt7621-cpc"; |
reg = <0x1fbf0000 0x8000>; |
}; |
|
mc: mc@1fbf8000 { |
compatible = "mtk,mt7621-mc"; |
reg = <0x1fbf8000 0x8000>; |
}; |
|
uartlite: uartlite@c00 { |
compatible = "ns16550a"; |
reg = <0xc00 0x100>; |
|
clock-frequency = <50000000>; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>; |
|
reg-shift = <2>; |
reg-io-width = <4>; |
no-loopback-test; |
}; |
|
uartlite2: uartlite2@d00 { |
compatible = "ns16550a"; |
reg = <0xd00 0x100>; |
|
clock-frequency = <50000000>; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>; |
|
reg-shift = <2>; |
reg-io-width = <4>; |
|
pinctrl-names = "default"; |
pinctrl-0 = <&uart2_pins>; |
|
status = "disabled"; |
}; |
|
uartlite3: uartlite3@e00 { |
compatible = "ns16550a"; |
reg = <0xe00 0x100>; |
|
clock-frequency = <50000000>; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>; |
|
reg-shift = <2>; |
reg-io-width = <4>; |
|
pinctrl-names = "default"; |
pinctrl-0 = <&uart3_pins>; |
|
status = "disabled"; |
}; |
|
spi0: spi@b00 { |
status = "disabled"; |
|
compatible = "ralink,mt7621-spi"; |
reg = <0xb00 0x100>; |
|
clocks = <&pll MT7621_CLK_BUS>; |
|
resets = <&rstctrl 18>; |
reset-names = "spi"; |
|
#address-cells = <1>; |
#size-cells = <0>; |
|
pinctrl-names = "default"; |
pinctrl-0 = <&spi_pins>; |
}; |
|
gdma: gdma@2800 { |
compatible = "ralink,rt3883-gdma"; |
reg = <0x2800 0x800>; |
|
resets = <&rstctrl 14>; |
reset-names = "dma"; |
|
interrupt-parent = <&gic>; |
interrupts = <0 13 4>; |
|
#dma-cells = <1>; |
#dma-channels = <16>; |
#dma-requests = <16>; |
|
status = "disabled"; |
}; |
|
hsdma: hsdma@7000 { |
compatible = "mediatek,mt7621-hsdma"; |
reg = <0x7000 0x1000>; |
|
resets = <&rstctrl 5>; |
reset-names = "hsdma"; |
|
interrupt-parent = <&gic>; |
interrupts = <0 11 4>; |
|
#dma-cells = <1>; |
#dma-channels = <1>; |
#dma-requests = <1>; |
|
status = "disabled"; |
}; |
}; |
|
pinctrl: pinctrl { |
compatible = "ralink,rt2880-pinmux"; |
pinctrl-names = "default"; |
pinctrl-0 = <&state_default>; |
|
state_default: pinctrl0 { |
}; |
|
i2c_pins: i2c_pins { |
i2c_pins { |
ralink,group = "i2c"; |
ralink,function = "i2c"; |
}; |
}; |
|
spi_pins: spi_pins { |
spi_pins { |
ralink,group = "spi"; |
ralink,function = "spi"; |
}; |
}; |
|
uart1_pins: uart1 { |
uart1 { |
ralink,group = "uart1"; |
ralink,function = "uart1"; |
}; |
}; |
|
uart2_pins: uart2 { |
uart2 { |
ralink,group = "uart2"; |
ralink,function = "uart2"; |
}; |
}; |
|
uart3_pins: uart3 { |
uart3 { |
ralink,group = "uart3"; |
ralink,function = "uart3"; |
}; |
}; |
|
rgmii1_pins: rgmii1 { |
rgmii1 { |
ralink,group = "rgmii1"; |
ralink,function = "rgmii1"; |
}; |
}; |
|
rgmii2_pins: rgmii2 { |
rgmii2 { |
ralink,group = "rgmii2"; |
ralink,function = "rgmii2"; |
}; |
}; |
|
mdio_pins: mdio { |
mdio { |
ralink,group = "mdio"; |
ralink,function = "mdio"; |
}; |
}; |
|
pcie_pins: pcie { |
pcie { |
ralink,group = "pcie"; |
ralink,function = "pcie rst"; |
}; |
}; |
|
nand_pins: nand { |
spi-nand { |
ralink,group = "spi"; |
ralink,function = "nand1"; |
}; |
|
sdhci-nand { |
ralink,group = "sdhci"; |
ralink,function = "nand2"; |
}; |
}; |
|
sdhci_pins: sdhci { |
sdhci { |
ralink,group = "sdhci"; |
ralink,function = "sdhci"; |
}; |
}; |
}; |
|
rstctrl: rstctrl { |
compatible = "ralink,rt2880-reset"; |
#reset-cells = <1>; |
}; |
|
clkctrl: clkctrl { |
compatible = "ralink,rt2880-clock"; |
#clock-cells = <1>; |
}; |
|
sdhci: sdhci@1E130000 { |
status = "disabled"; |
|
compatible = "ralink,mt7620-sdhci"; |
reg = <0x1E130000 0x4000>; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; |
|
pinctrl-names = "default"; |
pinctrl-0 = <&sdhci_pins>; |
}; |
|
xhci: xhci@1E1C0000 { |
#address-cells = <1>; |
#size-cells = <0>; |
status = "okay"; |
|
compatible = "mediatek,mt8173-xhci"; |
reg = <0x1e1c0000 0x1000 |
0x1e1d0700 0x0100>; |
reg-names = "mac", "ippc"; |
|
clocks = <&sysclock>; |
clock-names = "sys_ck"; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; |
|
/* |
* Port 1 of both hubs is one usb slot and referenced here. |
* The binding doesn't allow to address individual hubs. |
* hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci. |
*/ |
xhci_ehci_port1: port@1 { |
reg = <1>; |
#trigger-source-cells = <0>; |
}; |
|
/* |
* Only the second usb hub has a second port. That port serves |
* ehci and ohci. |
*/ |
ehci_port2: port@2 { |
reg = <2>; |
#trigger-source-cells = <0>; |
}; |
}; |
|
gic: interrupt-controller@1fbc0000 { |
compatible = "mti,gic"; |
reg = <0x1fbc0000 0x2000>; |
|
interrupt-controller; |
#interrupt-cells = <3>; |
|
mti,reserved-cpu-vectors = <7>; |
|
timer { |
compatible = "mti,gic-timer"; |
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
clocks = <&pll MT7621_CLK_CPU>; |
}; |
}; |
|
nand: nand@1e003000 { |
status = "disabled"; |
|
compatible = "mtk,mt7621-nand"; |
bank-width = <2>; |
reg = <0x1e003000 0x800 |
0x1e003800 0x800>; |
}; |
|
ethernet: ethernet@1e100000 { |
compatible = "mediatek,mt7621-eth"; |
reg = <0x1e100000 0x10000>; |
|
#address-cells = <1>; |
#size-cells = <1>; |
|
resets = <&rstctrl 6 &rstctrl 23>; |
reset-names = "fe", "eth"; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; |
|
mediatek,switch = <&gsw>; |
|
mdio-bus { |
#address-cells = <1>; |
#size-cells = <0>; |
|
phy1f: ethernet-phy@1f { |
reg = <0x1f>; |
phy-mode = "rgmii"; |
}; |
}; |
|
hnat: hnat@0 { |
compatible = "mediatek,mt7623-hnat"; |
reg = <0 0x10000>; |
mtketh-ppd = "eth0"; |
mtketh-lan = "eth0"; |
mtketh-wan = "eth0"; |
resets = <&rstctrl 0>; |
reset-names = "mtketh"; |
}; |
}; |
|
gsw: gsw@1e110000 { |
compatible = "mediatek,mt7621-gsw"; |
reg = <0x1e110000 0x8000>; |
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; |
}; |
|
pcie: pcie@1e140000 { |
compatible = "mediatek,mt7621-pci"; |
reg = <0x1e140000 0x100 |
0x1e142000 0x100>; |
|
#address-cells = <3>; |
#size-cells = <2>; |
|
pinctrl-names = "default"; |
pinctrl-0 = <&pcie_pins>; |
|
device_type = "pci"; |
|
bus-range = <0 255>; |
ranges = < |
0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ |
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ |
>; |
|
interrupt-parent = <&gic>; |
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH |
GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH |
GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; |
|
status = "disabled"; |
|
resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; |
reset-names = "pcie0", "pcie1", "pcie2"; |
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; |
clock-names = "pcie0", "pcie1", "pcie2"; |
|
pcie0: pcie@0,0 { |
reg = <0x0000 0 0 0 0>; |
|
#address-cells = <3>; |
#size-cells = <2>; |
|
ranges; |
}; |
|
pcie1: pcie@1,0 { |
reg = <0x0800 0 0 0 0>; |
|
#address-cells = <3>; |
#size-cells = <2>; |
|
ranges; |
}; |
|
pcie2: pcie@2,0 { |
reg = <0x1000 0 0 0 0>; |
|
#address-cells = <3>; |
#size-cells = <2>; |
|
ranges; |
}; |
}; |
}; |