/branches/18.06.1/target/linux/brcm63xx/patches-4.14/382-pinctrl-add-a-pincontrol-driver-for-BCM6318.patch |
@@ -0,0 +1,609 @@ |
From bd9c250ef85e6f99aa5d59b21abb87d0a48f2f61 Mon Sep 17 00:00:00 2001 |
From: Jonas Gorski <jonas.gorski@gmail.com> |
Date: Fri, 24 Jun 2016 22:20:39 +0200 |
Subject: [PATCH 15/16] pinctrl: add a pincontrol driver for BCM6318 |
|
Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs |
to different functions. BCM6318 is similar to BCM6328 with the addition |
of a pad register, and the GPIO meaning of the mux register changes |
based on the GPIO number. |
|
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
--- |
drivers/pinctrl/bcm63xx/Kconfig | 7 + |
drivers/pinctrl/bcm63xx/Makefile | 1 + |
drivers/pinctrl/bcm63xx/pinctrl-bcm6318.c | 564 ++++++++++++++++++++++++++++++ |
3 files changed, 572 insertions(+) |
create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6318.c |
|
--- a/drivers/pinctrl/bcm63xx/Kconfig |
+++ b/drivers/pinctrl/bcm63xx/Kconfig |
@@ -2,6 +2,13 @@ config PINCTRL_BCM63XX |
bool |
select GPIO_GENERIC |
|
+config PINCTRL_BCM6318 |
+ bool "BCM6318 pincontrol driver" if COMPILE_TEST |
+ select PINMUX |
+ select PINCONF |
+ select PINCTRL_BCM63XX |
+ select GENERIC_PINCONF |
+ |
config PINCTRL_BCM6328 |
bool "BCM6328 pincontrol driver" if COMPILE_TEST |
select PINMUX |
--- a/drivers/pinctrl/bcm63xx/Makefile |
+++ b/drivers/pinctrl/bcm63xx/Makefile |
@@ -1,4 +1,5 @@ |
obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o |
+obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o |
obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o |
obj-$(CONFIG_PINCTRL_BCM6348) += pinctrl-bcm6348.o |
obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o |
--- /dev/null |
+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6318.c |
@@ -0,0 +1,564 @@ |
+/* |
+ * This file is subject to the terms and conditions of the GNU General Public |
+ * License. See the file "COPYING" in the main directory of this archive |
+ * for more details. |
+ * |
+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> |
+ */ |
+ |
+#include <linux/kernel.h> |
+#include <linux/spinlock.h> |
+#include <linux/bitops.h> |
+#include <linux/gpio.h> |
+#include <linux/gpio/driver.h> |
+#include <linux/of.h> |
+#include <linux/of_gpio.h> |
+#include <linux/slab.h> |
+#include <linux/platform_device.h> |
+ |
+#include <linux/pinctrl/pinconf.h> |
+#include <linux/pinctrl/pinconf-generic.h> |
+#include <linux/pinctrl/pinmux.h> |
+#include <linux/pinctrl/machine.h> |
+ |
+#include "../core.h" |
+#include "../pinctrl-utils.h" |
+ |
+#include "pinctrl-bcm63xx.h" |
+ |
+#define BCM6318_NGPIO 50 |
+ |
+struct bcm6318_pingroup { |
+ const char *name; |
+ const unsigned * const pins; |
+ const unsigned num_pins; |
+}; |
+ |
+struct bcm6318_function { |
+ const char *name; |
+ const char * const *groups; |
+ const unsigned num_groups; |
+ |
+ unsigned mode_val:1; |
+ unsigned mux_val:2; |
+}; |
+ |
+struct bcm6318_pinctrl { |
+ struct pinctrl_dev *pctldev; |
+ struct pinctrl_desc desc; |
+ |
+ void __iomem *mode; |
+ void __iomem *mux[3]; |
+ void __iomem *pad[6]; |
+ |
+ /* register access lock */ |
+ spinlock_t lock; |
+ |
+ struct gpio_chip gpio[2]; |
+}; |
+ |
+static const struct pinctrl_pin_desc bcm6318_pins[] = { |
+ PINCTRL_PIN(0, "gpio0"), |
+ PINCTRL_PIN(1, "gpio1"), |
+ PINCTRL_PIN(2, "gpio2"), |
+ PINCTRL_PIN(3, "gpio3"), |
+ PINCTRL_PIN(4, "gpio4"), |
+ PINCTRL_PIN(5, "gpio5"), |
+ PINCTRL_PIN(6, "gpio6"), |
+ PINCTRL_PIN(7, "gpio7"), |
+ PINCTRL_PIN(8, "gpio8"), |
+ PINCTRL_PIN(9, "gpio9"), |
+ PINCTRL_PIN(10, "gpio10"), |
+ PINCTRL_PIN(11, "gpio11"), |
+ PINCTRL_PIN(12, "gpio12"), |
+ PINCTRL_PIN(13, "gpio13"), |
+ PINCTRL_PIN(14, "gpio14"), |
+ PINCTRL_PIN(15, "gpio15"), |
+ PINCTRL_PIN(16, "gpio16"), |
+ PINCTRL_PIN(17, "gpio17"), |
+ PINCTRL_PIN(18, "gpio18"), |
+ PINCTRL_PIN(19, "gpio19"), |
+ PINCTRL_PIN(20, "gpio20"), |
+ PINCTRL_PIN(21, "gpio21"), |
+ PINCTRL_PIN(22, "gpio22"), |
+ PINCTRL_PIN(23, "gpio23"), |
+ PINCTRL_PIN(24, "gpio24"), |
+ PINCTRL_PIN(25, "gpio25"), |
+ PINCTRL_PIN(26, "gpio26"), |
+ PINCTRL_PIN(27, "gpio27"), |
+ PINCTRL_PIN(28, "gpio28"), |
+ PINCTRL_PIN(29, "gpio29"), |
+ PINCTRL_PIN(30, "gpio30"), |
+ PINCTRL_PIN(31, "gpio31"), |
+ PINCTRL_PIN(32, "gpio32"), |
+ PINCTRL_PIN(33, "gpio33"), |
+ PINCTRL_PIN(34, "gpio34"), |
+ PINCTRL_PIN(35, "gpio35"), |
+ PINCTRL_PIN(36, "gpio36"), |
+ PINCTRL_PIN(37, "gpio37"), |
+ PINCTRL_PIN(38, "gpio38"), |
+ PINCTRL_PIN(39, "gpio39"), |
+ PINCTRL_PIN(40, "gpio40"), |
+ PINCTRL_PIN(41, "gpio41"), |
+ PINCTRL_PIN(42, "gpio42"), |
+ PINCTRL_PIN(43, "gpio43"), |
+ PINCTRL_PIN(44, "gpio44"), |
+ PINCTRL_PIN(45, "gpio45"), |
+ PINCTRL_PIN(46, "gpio46"), |
+ PINCTRL_PIN(47, "gpio47"), |
+ PINCTRL_PIN(48, "gpio48"), |
+ PINCTRL_PIN(49, "gpio49"), |
+}; |
+ |
+static unsigned gpio0_pins[] = { 0 }; |
+static unsigned gpio1_pins[] = { 1 }; |
+static unsigned gpio2_pins[] = { 2 }; |
+static unsigned gpio3_pins[] = { 3 }; |
+static unsigned gpio4_pins[] = { 4 }; |
+static unsigned gpio5_pins[] = { 5 }; |
+static unsigned gpio6_pins[] = { 6 }; |
+static unsigned gpio7_pins[] = { 7 }; |
+static unsigned gpio8_pins[] = { 8 }; |
+static unsigned gpio9_pins[] = { 9 }; |
+static unsigned gpio10_pins[] = { 10 }; |
+static unsigned gpio11_pins[] = { 11 }; |
+static unsigned gpio12_pins[] = { 12 }; |
+static unsigned gpio13_pins[] = { 13 }; |
+static unsigned gpio14_pins[] = { 14 }; |
+static unsigned gpio15_pins[] = { 15 }; |
+static unsigned gpio16_pins[] = { 16 }; |
+static unsigned gpio17_pins[] = { 17 }; |
+static unsigned gpio18_pins[] = { 18 }; |
+static unsigned gpio19_pins[] = { 19 }; |
+static unsigned gpio20_pins[] = { 20 }; |
+static unsigned gpio21_pins[] = { 21 }; |
+static unsigned gpio22_pins[] = { 22 }; |
+static unsigned gpio23_pins[] = { 23 }; |
+static unsigned gpio24_pins[] = { 24 }; |
+static unsigned gpio25_pins[] = { 25 }; |
+static unsigned gpio26_pins[] = { 26 }; |
+static unsigned gpio27_pins[] = { 27 }; |
+static unsigned gpio28_pins[] = { 28 }; |
+static unsigned gpio29_pins[] = { 29 }; |
+static unsigned gpio30_pins[] = { 30 }; |
+static unsigned gpio31_pins[] = { 31 }; |
+static unsigned gpio32_pins[] = { 32 }; |
+static unsigned gpio33_pins[] = { 33 }; |
+static unsigned gpio34_pins[] = { 34 }; |
+static unsigned gpio35_pins[] = { 35 }; |
+static unsigned gpio36_pins[] = { 36 }; |
+static unsigned gpio37_pins[] = { 37 }; |
+static unsigned gpio38_pins[] = { 38 }; |
+static unsigned gpio39_pins[] = { 39 }; |
+static unsigned gpio40_pins[] = { 40 }; |
+static unsigned gpio41_pins[] = { 41 }; |
+static unsigned gpio42_pins[] = { 42 }; |
+static unsigned gpio43_pins[] = { 43 }; |
+static unsigned gpio44_pins[] = { 44 }; |
+static unsigned gpio45_pins[] = { 45 }; |
+static unsigned gpio46_pins[] = { 46 }; |
+static unsigned gpio47_pins[] = { 47 }; |
+static unsigned gpio48_pins[] = { 48 }; |
+static unsigned gpio49_pins[] = { 49 }; |
+ |
+#define BCM6318_GROUP(n) \ |
+ { \ |
+ .name = #n, \ |
+ .pins = n##_pins, \ |
+ .num_pins = ARRAY_SIZE(n##_pins), \ |
+ } |
+ |
+static struct bcm6318_pingroup bcm6318_groups[] = { |
+ BCM6318_GROUP(gpio0), |
+ BCM6318_GROUP(gpio1), |
+ BCM6318_GROUP(gpio2), |
+ BCM6318_GROUP(gpio3), |
+ BCM6318_GROUP(gpio4), |
+ BCM6318_GROUP(gpio5), |
+ BCM6318_GROUP(gpio6), |
+ BCM6318_GROUP(gpio7), |
+ BCM6318_GROUP(gpio8), |
+ BCM6318_GROUP(gpio9), |
+ BCM6318_GROUP(gpio10), |
+ BCM6318_GROUP(gpio11), |
+ BCM6318_GROUP(gpio12), |
+ BCM6318_GROUP(gpio13), |
+ BCM6318_GROUP(gpio14), |
+ BCM6318_GROUP(gpio15), |
+ BCM6318_GROUP(gpio16), |
+ BCM6318_GROUP(gpio17), |
+ BCM6318_GROUP(gpio18), |
+ BCM6318_GROUP(gpio19), |
+ BCM6318_GROUP(gpio20), |
+ BCM6318_GROUP(gpio21), |
+ BCM6318_GROUP(gpio22), |
+ BCM6318_GROUP(gpio23), |
+ BCM6318_GROUP(gpio24), |
+ BCM6318_GROUP(gpio25), |
+ BCM6318_GROUP(gpio26), |
+ BCM6318_GROUP(gpio27), |
+ BCM6318_GROUP(gpio28), |
+ BCM6318_GROUP(gpio29), |
+ BCM6318_GROUP(gpio30), |
+ BCM6318_GROUP(gpio31), |
+ BCM6318_GROUP(gpio32), |
+ BCM6318_GROUP(gpio33), |
+ BCM6318_GROUP(gpio34), |
+ BCM6318_GROUP(gpio35), |
+ BCM6318_GROUP(gpio36), |
+ BCM6318_GROUP(gpio37), |
+ BCM6318_GROUP(gpio38), |
+ BCM6318_GROUP(gpio39), |
+ BCM6318_GROUP(gpio40), |
+ BCM6318_GROUP(gpio41), |
+ BCM6318_GROUP(gpio42), |
+ BCM6318_GROUP(gpio43), |
+ BCM6318_GROUP(gpio44), |
+ BCM6318_GROUP(gpio45), |
+ BCM6318_GROUP(gpio46), |
+ BCM6318_GROUP(gpio47), |
+ BCM6318_GROUP(gpio48), |
+ BCM6318_GROUP(gpio49), |
+}; |
+ |
+/* GPIO_MODE */ |
+static const char * const led_groups[] = { |
+ "gpio0", |
+ "gpio1", |
+ "gpio2", |
+ "gpio3", |
+ "gpio4", |
+ "gpio5", |
+ "gpio6", |
+ "gpio7", |
+ "gpio8", |
+ "gpio9", |
+ "gpio10", |
+ "gpio11", |
+ "gpio12", |
+ "gpio13", |
+ "gpio14", |
+ "gpio15", |
+ "gpio16", |
+ "gpio17", |
+ "gpio18", |
+ "gpio19", |
+ "gpio20", |
+ "gpio21", |
+ "gpio22", |
+ "gpio23", |
+}; |
+ |
+/* PINMUX_SEL */ |
+static const char * const ephy0_spd_led_groups[] = { |
+ "gpio0", |
+}; |
+ |
+static const char * const ephy1_spd_led_groups[] = { |
+ "gpio1", |
+}; |
+ |
+static const char * const ephy2_spd_led_groups[] = { |
+ "gpio2", |
+}; |
+ |
+static const char * const ephy3_spd_led_groups[] = { |
+ "gpio3", |
+}; |
+ |
+static const char * const ephy0_act_led_groups[] = { |
+ "gpio4", |
+}; |
+ |
+static const char * const ephy1_act_led_groups[] = { |
+ "gpio5", |
+}; |
+ |
+static const char * const ephy2_act_led_groups[] = { |
+ "gpio6", |
+}; |
+ |
+static const char * const ephy3_act_led_groups[] = { |
+ "gpio7", |
+}; |
+ |
+static const char * const serial_led_data_groups[] = { |
+ "gpio6", |
+}; |
+ |
+static const char * const serial_led_clk_groups[] = { |
+ "gpio7", |
+}; |
+ |
+static const char * const inet_act_led_groups[] = { |
+ "gpio8", |
+}; |
+ |
+static const char * const inet_fail_led_groups[] = { |
+ "gpio9", |
+}; |
+ |
+static const char * const dsl_led_groups[] = { |
+ "gpio10", |
+}; |
+ |
+static const char * const post_fail_led_groups[] = { |
+ "gpio11", |
+}; |
+ |
+static const char * const wlan_wps_led_groups[] = { |
+ "gpio12", |
+}; |
+ |
+static const char * const usb_pwron_groups[] = { |
+ "gpio13", |
+}; |
+ |
+static const char * const usb_device_led_groups[] = { |
+ "gpio13", |
+}; |
+ |
+static const char * const usb_active_groups[] = { |
+ "gpio40", |
+}; |
+ |
+#define BCM6318_MODE_FUN(n) \ |
+ { \ |
+ .name = #n, \ |
+ .groups = n##_groups, \ |
+ .num_groups = ARRAY_SIZE(n##_groups), \ |
+ .mode_val = 1, \ |
+ } |
+ |
+#define BCM6318_MUX_FUN(n, mux) \ |
+ { \ |
+ .name = #n, \ |
+ .groups = n##_groups, \ |
+ .num_groups = ARRAY_SIZE(n##_groups), \ |
+ .mux_val = mux, \ |
+ } |
+ |
+static const struct bcm6318_function bcm6318_funcs[] = { |
+ BCM6318_MODE_FUN(led), |
+ BCM6318_MUX_FUN(ephy0_spd_led, 1), |
+ BCM6318_MUX_FUN(ephy1_spd_led, 1), |
+ BCM6318_MUX_FUN(ephy2_spd_led, 1), |
+ BCM6318_MUX_FUN(ephy3_spd_led, 1), |
+ BCM6318_MUX_FUN(ephy0_act_led, 1), |
+ BCM6318_MUX_FUN(ephy1_act_led, 1), |
+ BCM6318_MUX_FUN(ephy2_act_led, 1), |
+ BCM6318_MUX_FUN(ephy3_act_led, 1), |
+ BCM6318_MUX_FUN(serial_led_data, 3), |
+ BCM6318_MUX_FUN(serial_led_clk, 3), |
+ BCM6318_MUX_FUN(inet_act_led, 1), |
+ BCM6318_MUX_FUN(inet_fail_led, 1), |
+ BCM6318_MUX_FUN(dsl_led, 1), |
+ BCM6318_MUX_FUN(post_fail_led, 1), |
+ BCM6318_MUX_FUN(wlan_wps_led, 1), |
+ BCM6318_MUX_FUN(usb_pwron, 1), |
+ BCM6318_MUX_FUN(usb_device_led, 2), |
+ BCM6318_MUX_FUN(usb_active, 2), |
+}; |
+ |
+static int bcm6318_pinctrl_get_group_count(struct pinctrl_dev *pctldev) |
+{ |
+ return ARRAY_SIZE(bcm6318_groups); |
+} |
+ |
+static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
+ unsigned group) |
+{ |
+ return bcm6318_groups[group].name; |
+} |
+ |
+static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, |
+ unsigned group, const unsigned **pins, |
+ unsigned *num_pins) |
+{ |
+ *pins = bcm6318_groups[group].pins; |
+ *num_pins = bcm6318_groups[group].num_pins; |
+ |
+ return 0; |
+} |
+ |
+static int bcm6318_pinctrl_get_func_count(struct pinctrl_dev *pctldev) |
+{ |
+ return ARRAY_SIZE(bcm6318_funcs); |
+} |
+ |
+static const char *bcm6318_pinctrl_get_func_name(struct pinctrl_dev *pctldev, |
+ unsigned selector) |
+{ |
+ return bcm6318_funcs[selector].name; |
+} |
+ |
+static int bcm6318_pinctrl_get_groups(struct pinctrl_dev *pctldev, |
+ unsigned selector, |
+ const char * const **groups, |
+ unsigned * const num_groups) |
+{ |
+ *groups = bcm6318_funcs[selector].groups; |
+ *num_groups = bcm6318_funcs[selector].num_groups; |
+ |
+ return 0; |
+} |
+ |
+static void bcm6318_rmw_mux(struct bcm6318_pinctrl *pctl, unsigned pin, |
+ u32 mode, u32 mux) |
+{ |
+ unsigned long flags; |
+ u32 reg; |
+ |
+ spin_lock_irqsave(&pctl->lock, flags); |
+ if (pin < 32) { |
+ reg = __raw_readl(pctl->mode); |
+ reg &= ~BIT(pin); |
+ if (mode) |
+ reg |= BIT(pin); |
+ __raw_writel(reg, pctl->mode); |
+ } |
+ |
+ if (pin < 48) { |
+ reg = __raw_readl(pctl->mux[pin / 16]); |
+ reg &= ~(3UL << ((pin % 16) * 2)); |
+ reg |= mux << ((pin % 16) * 2); |
+ __raw_writel(reg, pctl->mux[pin / 16]); |
+ } |
+ spin_unlock_irqrestore(&pctl->lock, flags); |
+} |
+ |
+static void bcm6318_set_pad(struct bcm6318_pinctrl *pctl, unsigned pin, u8 val) |
+{ |
+ unsigned long flags; |
+ u32 reg; |
+ |
+ spin_lock_irqsave(&pctl->lock, flags); |
+ reg = __raw_readl(pctl->pad[pin / 8]); |
+ reg &= ~(0xfUL << ((pin % 8) * 4)); |
+ reg |= val << ((pin % 8) * 4); |
+ __raw_writel(reg, pctl->pad[pin / 8]); |
+ spin_unlock_irqrestore(&pctl->lock, flags); |
+} |
+ |
+static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev, |
+ unsigned selector, unsigned group) |
+{ |
+ struct bcm6318_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
+ const struct bcm6318_pingroup *grp = &bcm6318_groups[group]; |
+ const struct bcm6318_function *f = &bcm6318_funcs[selector]; |
+ |
+ bcm6318_rmw_mux(pctl, grp->pins[0], f->mode_val, f->mux_val); |
+ |
+ return 0; |
+} |
+ |
+static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev, |
+ struct pinctrl_gpio_range *range, |
+ unsigned offset) |
+{ |
+ struct bcm6318_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
+ |
+ /* disable all functions using this pin */ |
+ if (offset < 13) { |
+ /* GPIOs 0-12 use mux 0 as GPIO function */ |
+ bcm6318_rmw_mux(pctl, offset, 0, 0); |
+ } else if (offset < 42) { |
+ /* GPIOs 13-41 use mux 3 as GPIO function */ |
+ bcm6318_rmw_mux(pctl, offset, 0, 3); |
+ |
+ /* FIXME: revert to old value for non gpio? */ |
+ bcm6318_set_pad(pctl, offset, 0); |
+ } else { |
+ /* no idea, really */ |
+ } |
+ |
+ return 0; |
+} |
+ |
+static struct pinctrl_ops bcm6318_pctl_ops = { |
+ .get_groups_count = bcm6318_pinctrl_get_group_count, |
+ .get_group_name = bcm6318_pinctrl_get_group_name, |
+ .get_group_pins = bcm6318_pinctrl_get_group_pins, |
+#ifdef CONFIG_OF |
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, |
+ .dt_free_map = pinctrl_utils_free_map, |
+#endif |
+}; |
+ |
+static struct pinmux_ops bcm6318_pmx_ops = { |
+ .get_functions_count = bcm6318_pinctrl_get_func_count, |
+ .get_function_name = bcm6318_pinctrl_get_func_name, |
+ .get_function_groups = bcm6318_pinctrl_get_groups, |
+ .set_mux = bcm6318_pinctrl_set_mux, |
+ .gpio_request_enable = bcm6318_gpio_request_enable, |
+ .strict = true, |
+}; |
+ |
+static int bcm6318_pinctrl_probe(struct platform_device *pdev) |
+{ |
+ struct bcm6318_pinctrl *pctl; |
+ struct resource *res; |
+ void __iomem *mode, *mux, *pad; |
+ unsigned i; |
+ |
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode"); |
+ mode = devm_ioremap_resource(&pdev->dev, res); |
+ if (IS_ERR(mode)) |
+ return PTR_ERR(mode); |
+ |
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mux"); |
+ mux = devm_ioremap_resource(&pdev->dev, res); |
+ if (IS_ERR(mux)) |
+ return PTR_ERR(mux); |
+ |
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pad"); |
+ pad = devm_ioremap_resource(&pdev->dev, res); |
+ if (IS_ERR(pad)) |
+ return PTR_ERR(pad); |
+ |
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); |
+ if (!pctl) |
+ return -ENOMEM; |
+ |
+ spin_lock_init(&pctl->lock); |
+ |
+ pctl->mode = mode; |
+ |
+ for (i = 0; i < 3; i++) |
+ pctl->mux[i] = mux + (i * 4); |
+ |
+ for (i = 0; i < 6; i++) |
+ pctl->pad[i] = pad + (i * 4); |
+ |
+ pctl->desc.name = dev_name(&pdev->dev); |
+ pctl->desc.owner = THIS_MODULE; |
+ pctl->desc.pctlops = &bcm6318_pctl_ops; |
+ pctl->desc.pmxops = &bcm6318_pmx_ops; |
+ |
+ pctl->desc.npins = ARRAY_SIZE(bcm6318_pins); |
+ pctl->desc.pins = bcm6318_pins; |
+ |
+ platform_set_drvdata(pdev, pctl); |
+ |
+ pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl, |
+ pctl->gpio, BCM6318_NGPIO); |
+ if (IS_ERR(pctl->pctldev)) |
+ return PTR_ERR(pctl->pctldev); |
+ |
+ return 0; |
+} |
+ |
+static const struct of_device_id bcm6318_pinctrl_match[] = { |
+ { .compatible = "brcm,bcm6318-pinctrl", }, |
+ { }, |
+}; |
+ |
+static struct platform_driver bcm6318_pinctrl_driver = { |
+ .probe = bcm6318_pinctrl_probe, |
+ .driver = { |
+ .name = "bcm6318-pinctrl", |
+ .of_match_table = bcm6318_pinctrl_match, |
+ }, |
+}; |
+ |
+builtin_platform_driver(bcm6318_pinctrl_driver); |