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/* bcm2835.h

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C and C++ support for Broadcom BCM 2835 as used in Raspberry Pi

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Author: Mike McCauley

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$Id: bcm2835.h,v 1.26 2020/01/11 05:07:13 mikem Exp mikem $

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*/

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/*! \mainpage C library for Broadcom BCM 2835 as used in Raspberry Pi

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This is a C library for Raspberry Pi (RPi). It provides access to

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GPIO and other IO functions on the Broadcom BCM 2835 chip, as used in the RaspberryPi,

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allowing access to the GPIO pins on the

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26 pin IDE plug on the RPi board so you can control and interface with various external devices.

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It provides functions for reading digital inputs and setting digital outputs, using SPI and I2C,

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and for accessing the system timers.

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Pin event detection is supported by polling (interrupts are not supported).

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Works on all versions up to and including RPI 4.

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Works with all versions of Debian up to and including Debian Buster 10.

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It is C++ compatible, and installs as a header file and non-shared library on

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any Linux-based distro (but clearly is no use except on Raspberry Pi or another board with

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BCM 2835).

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The version of the package that this documentation refers to can be downloaded

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from http://www.airspayce.com/mikem/bcm2835/bcm2835-1.71.tar.gz

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You can find the latest version at http://www.airspayce.com/mikem/bcm2835

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Several example programs are provided.

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Based on data in http://elinux.org/RPi_Low-level_peripherals and

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http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf

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and http://www.scribd.com/doc/101830961/GPIO-Pads-Control2

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You can also find online help and discussion at http://groups.google.com/group/bcm2835

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Please use that group for all questions and discussions on this topic.

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Do not contact the author directly, unless it is to discuss commercial licensing.

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Before asking a question or reporting a bug, please read

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- http://en.wikipedia.org/wiki/Wikipedia:Reference_desk/How_to_ask_a_software_question

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- http://www.catb.org/esr/faqs/smart-questions.html

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- http://www.chiark.greenend.org.uk/~shgtatham/bugs.html

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Tested on debian6-19-04-2012, 2012-07-15-wheezy-raspbian, 2013-07-26-wheezy-raspbian

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and Occidentalisv01, 2016-02-09 Raspbian Jessie.

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CAUTION: it has been observed that when detect enables such as bcm2835_gpio_len()

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are used and the pin is pulled LOW

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it can cause temporary hangs on 2012-07-15-wheezy-raspbian, 2013-07-26-wheezy-raspbian

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and Occidentalisv01.

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Reason for this is not yet determined, but we suspect that an interrupt handler is

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hitting a hard loop on those OSs.

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If you must use bcm2835_gpio_len() and friends, make sure you disable the pins with

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bcm2835_gpio_clr_len() and friends after use.

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In order to compile this library, you may need to install:

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- libc6-dev

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- libgcc-s-dev

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- libstdc++-staticdev

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\par Running as root

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Prior to the release of Raspbian Jessie in Feb 2016, access to any

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peripheral device via /dev/mem on the RPi required the process to

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run as root. Raspbian Jessie permits non-root users to access the

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GPIO peripheral (only) via /dev/gpiomem, and this library supports

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that limited mode of operation.

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If the library runs with effective UID of 0 (ie root), then

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bcm2835_init() will attempt to open /dev/mem, and, if successful, it

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will permit use of all peripherals and library functions.

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If the library runs with any other effective UID (ie not root), then

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bcm2835_init() will attempt to open /dev/gpiomem, and, if

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successful, will only permit GPIO operations. In particular,

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bcm2835_spi_begin() and bcm2835_i2c_begin() will return false and all

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other non-gpio operations may fail silently or crash.

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If your program needs acccess to /dev/mem but not as root,

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and if you have the libcap-dev package installed on the target,

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you can compile this library to use

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libcap2 so that it tests whether the exceutable has the cap_sys_rawio capability, and therefore

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permission to access /dev/mem.

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To enable this ability, uncomment the #define BCM2835_HAVE_LIBCAP in bcm2835.h or

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-DBCM2835_HAVE_LIBCAP on your compiler command line.

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After your program has been compiled:

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\code

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sudo setcap cap_sys_rawio+ep *myprogname*

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\endcode

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You also need to do these steps on the host once, to support libcap and not-root read/write access

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to /dev/mem:

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1. Install libcap support

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\code

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sudo apt-get install libcap2 libcap-dev

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2. Add current user to kmem group

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\code

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sudo adduser $USER kmem

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\endcode

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3. Allow write access to /dev/mem by members of kmem group

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\code

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echo 'SUBSYSTEM=="mem", KERNEL=="mem", GROUP="kmem", MODE="0660"' | sudo tee /etc/udev/rules.d/98-mem.rules

\endcode

\code

sudo reboot

\endcode

\par Installation

This library consists of a single non-shared library and header file, which will be

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installed in the usual places by make install

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\code

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# download the latest version of the library, say bcm2835-1.xx.tar.gz, then:

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tar zxvf bcm2835-1.xx.tar.gz

cd bcm2835-1.xx

./configure

make

sudo make check

sudo make install

\endcode

\par Physical Addresses

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The functions bcm2835_peri_read(), bcm2835_peri_write() and bcm2835_peri_set_bits()

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are low level peripheral register access functions. They are designed to use

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physical addresses as described in section 1.2.3 ARM physical addresses

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of the BCM2835 ARM Peripherals manual.

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Physical addresses range from 0x20000000 to 0x20FFFFFF for peripherals. The bus

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addresses for peripherals are set up to map onto the peripheral bus address range starting at

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0x7E000000. Thus a peripheral advertised in the manual at bus address 0x7Ennnnnn is available at

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physical address 0x20nnnnnn.

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On RPI 2, the peripheral addresses are different and the bcm2835 library gets them

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from reading /proc/device-tree/soc/ranges. This is only availble with recent versions of the kernel on RPI 2.

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After initialisation, the base address of the various peripheral

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registers are available with the following

externals:

bcm2835_gpio

bcm2835_pwm

bcm2835_clk

bcm2835_pads

bcm2835_spio0

bcm2835_st

bcm2835_bsc0

bcm2835_bsc1

bcm2835_aux

bcm2835_spi1

\par Raspberry Pi 2 (RPI2)

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For this library to work correctly on RPI2, you MUST have the device tree support enabled in the kernel.

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You should also ensure you are using the latest version of Linux. The library has been tested on RPI2

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with 2015-02-16-raspbian-wheezy and ArchLinuxARM-rpi-2 as of 2015-03-29.

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When device tree suport is enabled, the file /proc/device-tree/soc/ranges will appear in the file system,

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and the bcm2835 module relies on its presence to correctly run on RPI2 (it is optional for RPI1).

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Without device tree support enabled and the presence of this file, it will not work on RPI2.

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To enable device tree support:

\code

sudo raspi-config

under Advanced Options - enable Device Tree

Reboot.

\endcode

\par Pin Numbering

The GPIO pin numbering as used by RPi is different to and inconsistent with the underlying

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BCM 2835 chip pin numbering. http://elinux.org/RPi_BCM2835_GPIOs

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RPi has a 26 pin IDE header that provides access to some of the GPIO pins on the BCM 2835,

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as well as power and ground pins. Not all GPIO pins on the BCM 2835 are available on the

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IDE header.

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RPi Version 2 also has a P5 connector with 4 GPIO pins, 5V, 3.3V and Gnd.

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The functions in this library are designed to be passed the BCM 2835 GPIO pin number and _not_

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the RPi pin number. There are symbolic definitions for each of the available pins

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that you should use for convenience. See \ref RPiGPIOPin.

\par SPI Pins

The bcm2835_spi_* functions allow you to control the BCM 2835 SPI0 interface,

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allowing you to send and received data by SPI (Serial Peripheral Interface).

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For more information about SPI, see http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

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When bcm2835_spi_begin() is called it changes the bahaviour of the SPI interface pins from their

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default GPIO behaviour in order to support SPI. While SPI is in use, you will not be able

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to control the state of the SPI pins through the usual bcm2835_spi_gpio_write().

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When bcm2835_spi_end() is called, the SPI pins will all revert to inputs, and can then be

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configured and controled with the usual bcm2835_gpio_* calls.

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The Raspberry Pi GPIO pins used for SPI are:

- P1-19 (MOSI)

- P1-21 (MISO)

- P1-23 (CLK)

- P1-24 (CE0)

- P1-26 (CE1)

Although it is possible to select high speeds for the SPI interface, up to 125MHz (see bcm2835_spi_setClockDivider())

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you should not expect to actually achieve those sorts of speeds with the RPi wiring. Our tests on RPi 2 show that the

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SPI CLK line when unloaded has a resonant frequency of about 40MHz, and when loaded, the MOSI and MISO lines

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ring at an even lower frequency. Measurements show that SPI waveforms are very poor and unusable at 62 and 125MHz.

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Dont expect any speed faster than 31MHz to work reliably.

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The bcm2835_aux_spi_* functions allow you to control the BCM 2835 SPI1 interface,

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allowing you to send and received data by SPI (Serial Peripheral Interface).

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The Raspberry Pi GPIO pins used for AUX SPI (SPI1) are:

- P1-38 (MOSI)

- P1-35 (MISO)

- P1-40 (CLK)

- P1-36 (CE2)

\par I2C Pins

The bcm2835_i2c_* functions allow you to control the BCM 2835 BSC interface,

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allowing you to send and received data by I2C ("eye-squared cee"; generically referred to as "two-wire interface") .

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For more information about I?C, see http://en.wikipedia.org/wiki/I%C2%B2C

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The Raspberry Pi V2 GPIO pins used for I2C are:

- P1-03 (SDA)

- P1-05 (SLC)

\par PWM

The BCM2835 supports hardware PWM on a limited subset of GPIO pins. This bcm2835 library provides

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functions for configuring and controlling PWM output on these pins.

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The BCM2835 contains 2 independent PWM channels (0 and 1), each of which be connnected to a limited subset of

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GPIO pins. The following GPIO pins may be connected to the following PWM channels (from section 9.5):

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\code

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GPIO PIN RPi pin PWM Channel ALT FUN

12 0 0

13 1 0

18 1-12 0 5

19 1 5

40 0 0

41 1 0

45 1 0

52 0 1

53 1 1

\endcode

In order for a GPIO pin to emit output from its PWM channel, it must be set to the Alt Function given above.

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Note carefully that current versions of the Raspberry Pi only expose one of these pins (GPIO 18 = RPi Pin 1-12)

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on the IO headers, and therefore this is the only IO pin on the RPi that can be used for PWM.

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Further it must be set to ALT FUN 5 to get PWM output.

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Both PWM channels are driven by the same PWM clock, whose clock dvider can be varied using

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bcm2835_pwm_set_clock(). Each channel can be separately enabled with bcm2835_pwm_set_mode().

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The average output of the PWM channel is determined by the ratio of DATA/RANGE for that channel.

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Use bcm2835_pwm_set_range() to set the range and bcm2835_pwm_set_data() to set the data in that ratio

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Each PWM channel can run in either Balanced or Mark-Space mode. In Balanced mode, the hardware

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sends a combination of clock pulses that results in an overall DATA pulses per RANGE pulses.

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In Mark-Space mode, the hardware sets the output HIGH for DATA clock pulses wide, followed by

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LOW for RANGE-DATA clock pulses.

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The PWM clock can be set to control the PWM pulse widths. The PWM clock is derived from

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a 19.2MHz clock. You can set any divider, but some common ones are provided by the BCM2835_PWM_CLOCK_DIVIDER_*

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values of \ref bcm2835PWMClockDivider.

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For example, say you wanted to drive a DC motor with PWM at about 1kHz,

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and control the speed in 1/1024 increments from

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0/1024 (stopped) through to 1024/1024 (full on). In that case you might set the

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clock divider to be 16, and the RANGE to 1024. The pulse repetition frequency will be

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1.2MHz/1024 = 1171.875Hz.

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\par Interactions with other systems

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In order for bcm2835 library SPI to work, you may need to disable the SPI kernel module using:

\code

sudo raspi-config

under Advanced Options - enable Device Tree

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under Advanced Options - disable SPI

Reboot.

\endcode

Since bcm2835 accesses the lowest level hardware interfaces (in eh intererests of speed and flexibility)

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there can be intercations with other low level software trying to do similar things.

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It seems that with "latest" 8.0 Jessie 4.9.24-v7+ kernel PWM just won't

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work unless you disable audio. There's a line

\code

dtparam=audio=on

\endcode

in the /boot/config.txt.

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Comment it out like this:

\code

#dtparam=audio=on

\endcode

\par Real Time performance constraints

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The bcm2835 is a library for user programs (i.e. they run in 'userland').

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Such programs are not part of the kernel and are usually

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subject to paging and swapping by the kernel while it does other things besides running your program.

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This means that you should not expect to get real-time performance or

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real-time timing constraints from such programs. In particular, there is no guarantee that the

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bcm2835_delay() and bcm2835_delayMicroseconds() will return after exactly the time requested.

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In fact, depending on other activity on the host, IO etc, you might get significantly longer delay times

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than the one you asked for. So please dont expect to get exactly the time delay you request.

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Arjan reports that you can prevent swapping on Linux with the following code fragment:

\code

#define <sched.h>

#define <sys/mman.h>

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struct sched_param sp;

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memset(&sp, 0, sizeof(sp));

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sp.sched_priority = sched_get_priority_max(SCHED_FIFO);

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sched_setscheduler(0, SCHED_FIFO, &sp);

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mlockall(MCL_CURRENT | MCL_FUTURE);

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\endcode

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\par Crashing on some versions of Raspbian

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Some people have reported that various versions of Rasbian will crash or hang

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if certain GPIO pins are toggled: https://github.com/raspberrypi/linux/issues/2550

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when using bcm2835.

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A workaround is to add this line to your /boot/config.txt:

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\code

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dtoverlay=gpio-no-irq

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\endcode

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\par Bindings to other languages

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mikem has made Perl bindings available at CPAN:

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http://search.cpan.org/~mikem/Device-BCM2835-1.9/lib/Device/BCM2835.pm

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Matthew Baker has kindly made Python bindings available at:

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https: github.com/mubeta06/py-libbcm2835

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Gary Marks has created a Serial Peripheral Interface (SPI) command-line utility

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for Raspberry Pi, based on the bcm2835 library. The

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utility, spincl, is licensed under Open Source GNU GPLv3 by iP Solutions (http://ipsolutionscorp.com), as a

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free download with source included: http://ipsolutionscorp.com/raspberry-pi-spi-utility/

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Bindings for Ada are available courtesy Tama McGlinn at https://github.com/TamaMcGlinn/ada_raspio

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\par Open Source Licensing GPL V3

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This is the appropriate option if you want to share the source code of your

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application with everyone you distribute it to, and you also want to give them

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the right to share who uses it. If you wish to use this software under Open

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Source Licensing, you must contribute all your source code to the open source

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community in accordance with the GPL Version 3 when your application is

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distributed. See https://www.gnu.org/licenses/gpl-3.0.html and COPYING

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\par Commercial Licensing

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This is the appropriate option if you are creating proprietary applications

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and you are not prepared to distribute and share the source code of your

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application. To purchase a commercial license, contact info@airspayce.com

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\par Acknowledgements

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Some of this code has been inspired by Dom and Gert.

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The I2C code has been inspired by Alan Barr.

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\par Revision History

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\version 1.0 Initial release

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\version 1.1 Minor bug fixes

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\version 1.2 Added support for SPI

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\version 1.3 Added bcm2835_spi_transfern()

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\version 1.4 Fixed a problem that prevented SPI CE1 being used. Reported by David Robinson.

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\version 1.5 Added bcm2835_close() to deinit the library. Suggested by C?sar Ortiz

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\version 1.6 Document testing on 2012-07-15-wheezy-raspbian and Occidentalisv01

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Functions bcm2835_gpio_ren(), bcm2835_gpio_fen(), bcm2835_gpio_hen()

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bcm2835_gpio_len(), bcm2835_gpio_aren() and bcm2835_gpio_afen() now

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changes only the pin specified. Other pins that were already previously

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enabled stay enabled.

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Added bcm2835_gpio_clr_ren(), bcm2835_gpio_clr_fen(), bcm2835_gpio_clr_hen()

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bcm2835_gpio_clr_len(), bcm2835_gpio_clr_aren(), bcm2835_gpio_clr_afen()

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to clear the enable for individual pins, suggested by Andreas Sundstrom.

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\version 1.7 Added bcm2835_spi_transfernb to support different buffers for read and write.

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\version 1.8 Improvements to read barrier, as suggested by maddin.

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\version 1.9 Improvements contributed by mikew:

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I noticed that it was mallocing memory for the mmaps on /dev/mem.

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It's not necessary to do that, you can just mmap the file directly,

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so I've removed the mallocs (and frees).

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I've also modified delayMicroseconds() to use nanosleep() for long waits,

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and a busy wait on a high resolution timer for the rest. This is because

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I've found that calling nanosleep() takes at least 100-200 us.

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You need to link using '-lrt' using this version.

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I've added some unsigned casts to the debug prints to silence compiler

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warnings I was getting, fixed some typos, and changed the value of

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BCM2835_PAD_HYSTERESIS_ENABLED to 0x08 as per Gert van Loo's doc at

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http://www.scribd.com/doc/101830961/GPIO-Pads-Control2

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Also added a define for the passwrd value that Gert says is needed to

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change pad control settings.

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\version 1.10 Changed the names of the delay functions to bcm2835_delay()

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and bcm2835_delayMicroseconds() to prevent collisions with wiringPi.

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Macros to map delay()-> bcm2835_delay() and

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Macros to map delayMicroseconds()-> bcm2835_delayMicroseconds(), which

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can be disabled by defining BCM2835_NO_DELAY_COMPATIBILITY

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\version 1.11 Fixed incorrect link to download file

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\version 1.12 New GPIO pin definitions for RPi version 2 (which has a different GPIO mapping)

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\version 1.13 New GPIO pin definitions for RPi version 2 plug P5

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Hardware base pointers are now available (after initialisation) externally as bcm2835_gpio

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bcm2835_pwm bcm2835_clk bcm2835_pads bcm2835_spi0.

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\version 1.14 Now compiles even if CLOCK_MONOTONIC_RAW is not available, uses CLOCK_MONOTONIC instead.

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Fixed errors in documentation of SPI divider frequencies based on 250MHz clock.

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Reported by Ben Simpson.

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\version 1.15 Added bcm2835_close() to end of examples as suggested by Mark Wolfe.

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\version 1.16 Added bcm2835_gpio_set_multi, bcm2835_gpio_clr_multi and bcm2835_gpio_write_multi

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to allow a mask of pins to be set all at once. Requested by Sebastian Loncar.

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\version 1.17 Added bcm2835_gpio_write_mask. Requested by Sebastian Loncar.

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\version 1.18 Added bcm2835_i2c_* functions. Changes to bcm2835_delayMicroseconds:

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now uses the RPi system timer counter, instead of clock_gettime, for improved accuracy.

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No need to link with -lrt now. Contributed by Arjan van Vught.

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\version 1.19 Removed inlines added by previous patch since they don't seem to work everywhere.

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Reported by olly.

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\version 1.20 Patch from Mark Dootson to close /dev/mem after access to the peripherals has been granted.

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\version 1.21 delayMicroseconds is now not susceptible to 32 bit timer overruns.

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Patch courtesy Jeremy Mortis.

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\version 1.22 Fixed incorrect definition of BCM2835_GPFEN0 which broke the ability to set

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falling edge events. Reported by Mark Dootson.

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\version 1.23 Added bcm2835_i2c_set_baudrate and bcm2835_i2c_read_register_rs.

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Improvements to bcm2835_i2c_read and bcm2835_i2c_write functions

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to fix ocasional reads not completing. Patched by Mark Dootson.

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\version 1.24 Mark Dootson p[atched a problem with his previously submitted code

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under high load from other processes.

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\version 1.25 Updated author and distribution location details to airspayce.com

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\version 1.26 Added missing unmapmem for pads in bcm2835_close to prevent a memory leak.

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Reported by Hartmut Henkel.

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\version 1.27 bcm2835_gpio_set_pad() no longer needs BCM2835_PAD_PASSWRD: it is

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now automatically included.

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Added support for PWM mode with bcm2835_pwm_* functions.

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\version 1.28 Fixed a problem where bcm2835_spi_writenb() would have problems with transfers of more than

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64 bytes dues to read buffer filling. Patched by Peter Würtz.

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\version 1.29 Further fix to SPI from Peter Würtz.

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\version 1.30 10 microsecond delays from bcm2835_spi_transfer and bcm2835_spi_transfern for

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significant performance improvements, Patch by Alan Watson.

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\version 1.31 Fix a GCC warning about dummy variable, patched by Alan Watson. Thanks.

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\version 1.32 Added option I2C_V1 definition to compile for version 1 RPi.

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By default I2C code is generated for the V2 RPi which has SDA1 and SCL1 connected.

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Contributed by Malcolm Wiles based on work by Arvi Govindaraj.

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\version 1.33 Added command line utilities i2c and gpio to examples. Contributed by Shahrooz Shahparnia.

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\version 1.34 Added bcm2835_i2c_write_read_rs() which writes an arbitrary number of bytes,

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sends a repeat start, and reads from the device. Contributed by Eduardo Steinhorst.

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  \version 1.35 Fix build errors when compiled under Qt. Also performance improvements with SPI transfers. Contributed b Udo Klaas.

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\version 1.36 Make automake's test runner detect that we're skipping tests when not root, the second

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one makes us skip the test when using fakeroot (as used when building

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Debian packages). Contributed by Guido Günther.

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\version 1.37 Moved confiure.in to configure.ac as receommnded by autoreconf. 

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Improvements to bcm2835_st_read to account for possible timer overflow, contributed by 'Ed'. 

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Added definitions for Raspberry Pi B+ J8 header GPIO pins. 

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\version 1.38 Added bcm2835_regbase for the benefit of C# wrappers, patch by Frank Hommers 

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\version 1.39 Beta version of RPi2 compatibility. Not tested here on RPi2 hardware.

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Testers please confirm correct operation on RPi2. 

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Unnecessary 'volatile' qualifiers removed from all variables and signatures. 

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Removed unsupportable PWM dividers, based on a report from Christophe Cecillon. 

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Minor improvements to spi.c example. 

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\version 1.40 Correct operation on RPi2 has been confirmed. 

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Fixed a number of compiler errors and warnings that occur when bcm2835.h is included

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in code compiled with -Wall -Woverflow -Wstrict-overflow -Wshadow -Wextra -pedantic.

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Reported by tlhackque. 

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Fixed a problem where calling bcm2835_delayMicroseconds loops forever when debug is set. Reported by tlhackque. 

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Reinstated use of volatile in 2 functions where there was a danger of lost reads or writes. Reported by tlhackque. 

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\version 1.41 Added BCM2835_VERSION macro and new function bcm2835_version(); Requested by tlhackque. 

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Improvements to peripheral memory barriers as suggested by tlhackque. 

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Reinstated some necessary volatile declarations as requested by tlhackque. 

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\version 1.42 Further improvements to memory barriers with the patient assistance and patches of tlhackque. 

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\version 1.43 Fixed problems with compiling barriers on RPI 2 with Arch Linux and gcc 4.9.2.

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Reported and patched by Lars Christensen. 

517

Testing on RPI 2, with ArchLinuxARM-rpi-2-latest and 2015-02-16-raspbian-wheezy. 

518

519

\version 1.44 Added documention about the need for device tree to be enabled on RPI2. 

520

Improvements to detection of availability of DMB instruction based on value of __ARM_ARCH macro. 

521

522

\version 1.45 Fixed an error in the pad group offsets that would prevent bcm2835_gpio_set_pad()

523

and bcm2835_gpio_pad() working correctly with non-0 pad groups. Reported by Guido.

524

525

\version 1.46 2015-09-18

526

Added symbolic definitions for remaining pins on 40 pin GPIO header on RPi 2. 

527

528

\version 1.47 2015-11-18

529

Fixed possibly incorrect reads in bcm2835_i2c_read_register_rs, patch from Eckhardt Ulrich. 

530

531

\version 1.48 2015-12-08

532

Added patch from Eckhardt Ulrich that fixed problems that could cause hanging with bcm2835_i2c_read_register_rs

533

and others.

534

535

\version 1.49 2016-01-05

536

Added patch from Jonathan Perkin with new functions bcm2835_gpio_eds_multi() and bcm2835_gpio_set_eds_multi().

537

538

\version 1.50 2016-02-28

539

Added support for running as non-root, permitting access to GPIO only. Functions

540

bcm2835_spi_begin() and bcm2835_i2c_begin() will now return 0 if not running as root

541

(which prevents access to the SPI and I2C peripherals, amongst others).

542

Testing on Raspbian Jessie.

543

544

\version 1.51 2016-11-03

545

Added documentation about SPI clock divider and resulting SPI speeds on RPi3.

546

Fixed a problem where seg fault could occur in bcm2835_delayMicroseconds() if not running as root. Patch from Pok.

547

548

\version 1.52 2017-02-03

549

Added link to commercial license purchasing.

550

551

\version 1.53 2018-01-14

552

Added support for AUX SPI (SPI1)

553

Contributed by Arjan van Vught (http://www.raspberrypi-dmx.org/)

554

555

\version 1.54 2018-01-17

556

Fixed compile errors in new AUX spi code under some circumstances.

557

558

\version 1.55 2018-01-20

559

Fixed version numbers.

560

Fixed some warnings.

561

562

\version 1.56 2018-06-10

563

Supports bcm2835_spi_setBitOrder(BCM2835_SPI_BIT_ORDER_LSBFIRST), after which SPI bytes are reversed on read or write.

564

Based on a suggestion by Damiano Benedetti.

565

566

\version 1.57 2018-08-28

567

Added SPI function bcm2835_spi_set_speed_hz(uint32_t speed_hz);

568

Contributed by Arjan van Vught (http://www.raspberrypi-dmx.org/)

569

570

\version 1.58 2018-11-29

571

Added examples/spiram, which shows how to use the included little library (spiram.c and spiram.h)

572

to read and write SPI RAM chips such as 23K256-I/P

573

574

\version 1.59 2019-05-22

575

Fixed a bug in bcm2835_i2c_read reported by Charles Hayward where a noisy I2C line cold cause a seg fault by

576

reading too many characters.

577

578

\version 1.60 2019-07-23

579

  Applied patch from Mark Dootson for RPi 4 compatibility. Thanks Mark. Not tested here on RPi4, but others report it works.

580

Tested as still working correctly on earlier RPi models. Tested with Debian Buster on earlier models

581

582

\version 1.61 2020-01-11

583

Fixed errors in the documentation for bcm2835_spi_write.

584

Fixes issue seen on Raspberry Pi 4 boards where 64-bit off_t is used by

585

default via -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64. The offset was

586

being incorrectly converted, this way is clearer and fixes the problem. Contributed by Jonathan Perkin.

587

588

\version 1.62 2020-01-12

589

Fixed a problem that could cause compile failures with size_t and off_t

590

591

\version 1.63 2020-03-07

592

Added bcm2835_aux_spi_transfer, contributed by Michivi

593

Adopted GPL V3 licensing

594

595

\version 1.64 2020-04-11

596

Fixed error in definitions of BCM2835_AUX_SPI_STAT_TX_LVL and BCM2835_AUX_SPI_STAT_RX_LVL. Patch from

597

Eric Marzec. Thanks.

598

599

\version 1.65, 1.66 2020-04-16

600

Added support for use of capability cap_sys_rawio to determine if access to /dev/mem is available for non-root

601

users. Contributed by Doug McFadyen.

602

603

\version 1.67, 1.66 2020-06-11

604

Fixed an error in bcm2835_i2c_read() where the status byte was not correctly updated with BCM2835_BSC_S_DONE

605

Reported by Zihan. Thanks.

606

607

\version 1.69, 2021-03-30

608

Added link to Ada bindings by Tama McGlinn.

609

Fixed problem with undefined off_t on some compilers.

610

611

\version 1.70,

612

Patch to ensure compilation with gcc -std=c99, as reported by John Blaiklock.

613

Fix some inconsistencies in version numbers

614

615

version 1.71

616

Added SMI bus support, courtesy of Benoit Bouchez, including new functions:

617

bcm2835_smi_begin(), bcm2835_smi_end(),

618

bcm2835_smi_set_timing(), bcm2835_smi_write(), bcm2835_smi_read().

619

620

\author Mike McCauley (mikem@airspayce.com) DO NOT CONTACT THE AUTHOR DIRECTLY: USE THE LISTS

*/

/* Defines for BCM2835 */

#ifndef BCM2835_H

#define BCM2835_H

#include <stdint.h>

629

630

/* Some compilers need this, as reported by Sam James */

631

#include <sys/types.h>

632

/* Needed to compile with gcc -std=c99, as reported by John Blaiklock.*/

633

#include <fcntl.h>

634

635

#define BCM2835_VERSION 10071 /* Version 1.71 */

636

637

// Define this if you want to use libcap2 to determine if you have the cap_sys_rawio capability

638

// and therefore the capability of opening /dev/mem, even if you are not root.

639

// See the comments above in the documentation for 'Running As Root'

640

//#define BCM2835_HAVE_LIBCAP

641

642

/* RPi 2 is ARM v7, and has DMB instruction for memory barriers.

643

Older RPis are ARM v6 and don't, so a coprocessor instruction must be used instead.

644

However, not all versions of gcc in all distros support the dmb assembler instruction even on compatible processors.

645

This test is so any ARMv7 or higher processors with suitable GCC will use DMB.

646

*/

647

#if __ARM_ARCH >= 7

648

#define BCM2835_HAVE_DMB

649

#endif

650

651

/*! \defgroup constants Constants for passing to and from library functions

652

The values here are designed to be passed to various functions in the bcm2835 library.

@{

*/

/*! This means pin HIGH, true, 3.3volts on a pin. */

657

#define HIGH 0x1

658

/*! This means pin LOW, false, 0volts on a pin. */

659

#define LOW 0x0

660

661

/*! Return the minimum of 2 numbers */

662

#ifndef MIN

663

#define MIN(a, b) (a < b ? a : b)

664

#endif

665

666

/*! Speed of the core clock core_clk */

667

#define BCM2835_CORE_CLK_HZ 250000000 /*!< 250 MHz */

668

669

/*! On all recent OSs, the base of the peripherals is read from a /proc file */

670

#define BMC2835_RPI2_DT_FILENAME "/proc/device-tree/soc/ranges"

671

672

/*! Physical addresses for various peripheral register sets

673

Base Physical Address of the BCM 2835 peripheral registers

674

Note this is different for the RPi2 BCM2836, where this is derived from /proc/device-tree/soc/ranges

675

If /proc/device-tree/soc/ranges exists on a RPi 1 OS, it would be expected to contain the

676

following numbers:

677

*/

678

/*! Peripherals block base address on RPi 1 */

679

#define BCM2835_PERI_BASE 0x20000000

680

/*! Size of the peripherals block on RPi 1 */

681

#define BCM2835_PERI_SIZE 0x01000000

682

/*! Alternate base address for RPI 2 / 3 */

683

#define BCM2835_RPI2_PERI_BASE 0x3F000000

684

/*! Alternate base address for RPI 4 */

685

#define BCM2835_RPI4_PERI_BASE 0xFE000000

686

/*! Alternate size for RPI 4 */

687

#define BCM2835_RPI4_PERI_SIZE 0x01800000

688

689

/*! Offsets for the bases of various peripherals within the peripherals block

690

/ Base Address of the System Timer registers

691

*/

692

#define BCM2835_ST_BASE 0x3000

693

/*! Base Address of the Pads registers */

694

#define BCM2835_GPIO_PADS 0x100000

695

/*! Base Address of the Clock/timer registers */

696

#define BCM2835_CLOCK_BASE 0x101000

697

/*! Base Address of the GPIO registers */

698

#define BCM2835_GPIO_BASE 0x200000

699

/*! Base Address of the SPI0 registers */

700

#define BCM2835_SPI0_BASE 0x204000

701

/*! Base Address of the BSC0 registers */

702

#define BCM2835_BSC0_BASE 0x205000

703

/*! Base Address of the PWM registers */

704

#define BCM2835_GPIO_PWM 0x20C000

705

/*! Base Address of the AUX registers */

706

#define BCM2835_AUX_BASE 0x215000

707

/*! Base Address of the AUX_SPI1 registers */

708

#define BCM2835_SPI1_BASE 0x215080

709

/*! Base Address of the AUX_SPI2 registers */

710

#define BCM2835_SPI2_BASE 0x2150C0

711

/*! Base Address of the BSC1 registers */

712

#define BCM2835_BSC1_BASE 0x804000

713

714

/* BEB */

715

/*! Base address of the SMI registers */

716

#define BCM2835_SMI_BASE 0x600000

717

718

#include <stdlib.h>

719

720

/*! Physical address and size of the peripherals block

721

May be overridden on RPi2

722

*/

723

extern off_t bcm2835_peripherals_base;

724

/*! Size of the peripherals block to be mapped */

725

extern size_t bcm2835_peripherals_size;

726

727

/*! Virtual memory address of the mapped peripherals block */

728

extern uint32_t *bcm2835_peripherals;

729

730

/*! Base of the ST (System Timer) registers.

731

Available after bcm2835_init has been called (as root)

732

*/

733

extern volatile uint32_t *bcm2835_st;

734

735

/*! Base of the GPIO registers.

736

Available after bcm2835_init has been called

737

*/

738

extern volatile uint32_t *bcm2835_gpio;

739

740

/*! Base of the PWM registers.

741

Available after bcm2835_init has been called (as root)

742

*/

743

extern volatile uint32_t *bcm2835_pwm;

744

745

/*! Base of the CLK registers.

746

Available after bcm2835_init has been called (as root)

747

*/

748

extern volatile uint32_t *bcm2835_clk;

749

750

/*! Base of the PADS registers.

751

Available after bcm2835_init has been called (as root)

752

*/

753

extern volatile uint32_t *bcm2835_pads;

754

755

/*! Base of the SPI0 registers.

756

Available after bcm2835_init has been called (as root)

757

*/

758

extern volatile uint32_t *bcm2835_spi0;

759

760

/*! Base of the BSC0 registers.

761

Available after bcm2835_init has been called (as root)

762

*/

763

extern volatile uint32_t *bcm2835_bsc0;

764

765

/*! Base of the BSC1 registers.

766

Available after bcm2835_init has been called (as root)

767

*/

768

extern volatile uint32_t *bcm2835_bsc1;

769

770

/*! Base of the AUX registers.

771

Available after bcm2835_init has been called (as root)

772

*/

773

extern volatile uint32_t *bcm2835_aux;

774

775

/*! Base of the SPI1 registers.

776

Available after bcm2835_init has been called (as root)

777

*/

778

extern volatile uint32_t *bcm2835_spi1;

779

780

/* BEB */

781

/*! Base of SMI registers.

782

Available after bcm2835_init has been called (as root)

783

*/

784

extern volatile uint32_t *bcm2835_smi;

785

786

/*! \brief bcm2835RegisterBase

787

Register bases for bcm2835_regbase()

*/

typedef enum

{

BCM2835_REGBASE_ST = 1, /*!< Base of the ST (System Timer) registers. */

792

BCM2835_REGBASE_GPIO = 2, /*!< Base of the GPIO registers. */

793

BCM2835_REGBASE_PWM = 3, /*!< Base of the PWM registers. */

794

BCM2835_REGBASE_CLK = 4, /*!< Base of the CLK registers. */

795

BCM2835_REGBASE_PADS = 5, /*!< Base of the PADS registers. */

796

BCM2835_REGBASE_SPI0 = 6, /*!< Base of the SPI0 registers. */

797

BCM2835_REGBASE_BSC0 = 7, /*!< Base of the BSC0 registers. */

798

BCM2835_REGBASE_BSC1 = 8, /*!< Base of the BSC1 registers. */

799

BCM2835_REGBASE_AUX = 9, /*!< Base of the AUX registers. */

800

BCM2835_REGBASE_SPI1 = 10,/*!< Base of the SPI1 registers. */

801

/* BEB */

802

BCM2835_REGBASE_SMI = 11 /*!< Base of the SMI registers. */

803

804

} bcm2835RegisterBase;

805

806

/*! Size of memory page on RPi */

807

#define BCM2835_PAGE_SIZE (4*1024)

808

/*! Size of memory block on RPi */

809

#define BCM2835_BLOCK_SIZE (4*1024)

810

811

812

/* Defines for GPIO

813

The BCM2835 has 54 GPIO pins.

814

BCM2835 data sheet, Page 90 onwards.

815

*/

816

/*! GPIO register offsets from BCM2835_GPIO_BASE.

817

Offsets into the GPIO Peripheral block in bytes per 6.1 Register View

818

*/

819

#define BCM2835_GPFSEL0 0x0000 /*!< GPIO Function Select 0 */

820

#define BCM2835_GPFSEL1 0x0004 /*!< GPIO Function Select 1 */

821

#define BCM2835_GPFSEL2 0x0008 /*!< GPIO Function Select 2 */

822

#define BCM2835_GPFSEL3 0x000c /*!< GPIO Function Select 3 */

823

#define BCM2835_GPFSEL4 0x0010 /*!< GPIO Function Select 4 */

824

#define BCM2835_GPFSEL5 0x0014 /*!< GPIO Function Select 5 */

825

#define BCM2835_GPSET0 0x001c /*!< GPIO Pin Output Set 0 */

826

#define BCM2835_GPSET1 0x0020 /*!< GPIO Pin Output Set 1 */

827

#define BCM2835_GPCLR0 0x0028 /*!< GPIO Pin Output Clear 0 */

828

#define BCM2835_GPCLR1 0x002c /*!< GPIO Pin Output Clear 1 */

829

#define BCM2835_GPLEV0 0x0034 /*!< GPIO Pin Level 0 */

830

#define BCM2835_GPLEV1 0x0038 /*!< GPIO Pin Level 1 */

831

#define BCM2835_GPEDS0 0x0040 /*!< GPIO Pin Event Detect Status 0 */

832

#define BCM2835_GPEDS1 0x0044 /*!< GPIO Pin Event Detect Status 1 */

833

#define BCM2835_GPREN0 0x004c /*!< GPIO Pin Rising Edge Detect Enable 0 */

834

#define BCM2835_GPREN1 0x0050 /*!< GPIO Pin Rising Edge Detect Enable 1 */

835

#define BCM2835_GPFEN0 0x0058 /*!< GPIO Pin Falling Edge Detect Enable 0 */

836

#define BCM2835_GPFEN1 0x005c /*!< GPIO Pin Falling Edge Detect Enable 1 */

837

#define BCM2835_GPHEN0 0x0064 /*!< GPIO Pin High Detect Enable 0 */

838

#define BCM2835_GPHEN1 0x0068 /*!< GPIO Pin High Detect Enable 1 */

839

#define BCM2835_GPLEN0 0x0070 /*!< GPIO Pin Low Detect Enable 0 */

840

#define BCM2835_GPLEN1 0x0074 /*!< GPIO Pin Low Detect Enable 1 */

841

#define BCM2835_GPAREN0 0x007c /*!< GPIO Pin Async. Rising Edge Detect 0 */

842

#define BCM2835_GPAREN1 0x0080 /*!< GPIO Pin Async. Rising Edge Detect 1 */

843

#define BCM2835_GPAFEN0 0x0088 /*!< GPIO Pin Async. Falling Edge Detect 0 */

844

#define BCM2835_GPAFEN1 0x008c /*!< GPIO Pin Async. Falling Edge Detect 1 */

845

#define BCM2835_GPPUD 0x0094 /*!< GPIO Pin Pull-up/down Enable */

846

#define BCM2835_GPPUDCLK0 0x0098 /*!< GPIO Pin Pull-up/down Enable Clock 0 */

847

#define BCM2835_GPPUDCLK1 0x009c /*!< GPIO Pin Pull-up/down Enable Clock 1 */

848

849

/* 2711 has a different method for pin pull-up/down/enable */

850

#define BCM2835_GPPUPPDN0 0x00e4 /* Pin pull-up/down for pins 15:0 */

851

#define BCM2835_GPPUPPDN1 0x00e8 /* Pin pull-up/down for pins 31:16 */

852

#define BCM2835_GPPUPPDN2 0x00ec /* Pin pull-up/down for pins 47:32 */

853

#define BCM2835_GPPUPPDN3 0x00f0 /* Pin pull-up/down for pins 57:48 */

854

855

/*! \brief bcm2835PortFunction

856

Port function select modes for bcm2835_gpio_fsel()

*/

typedef enum

{

BCM2835_GPIO_FSEL_INPT = 0x00, /*!< Input 0b000 */

861

BCM2835_GPIO_FSEL_OUTP = 0x01, /*!< Output 0b001 */

862

BCM2835_GPIO_FSEL_ALT0 = 0x04, /*!< Alternate function 0 0b100 */

863

BCM2835_GPIO_FSEL_ALT1 = 0x05, /*!< Alternate function 1 0b101 */

864

BCM2835_GPIO_FSEL_ALT2 = 0x06, /*!< Alternate function 2 0b110, */

865

BCM2835_GPIO_FSEL_ALT3 = 0x07, /*!< Alternate function 3 0b111 */

866

BCM2835_GPIO_FSEL_ALT4 = 0x03, /*!< Alternate function 4 0b011 */

867

BCM2835_GPIO_FSEL_ALT5 = 0x02, /*!< Alternate function 5 0b010 */

868

BCM2835_GPIO_FSEL_MASK = 0x07 /*!< Function select bits mask 0b111 */

869

} bcm2835FunctionSelect;

870

871

/*! \brief bcm2835PUDControl

872

Pullup/Pulldown defines for bcm2835_gpio_pud()

*/

typedef enum

{

BCM2835_GPIO_PUD_OFF = 0x00, /*!< Off ? disable pull-up/down 0b00 */

877

BCM2835_GPIO_PUD_DOWN = 0x01, /*!< Enable Pull Down control 0b01 */

878

BCM2835_GPIO_PUD_UP = 0x02 /*!< Enable Pull Up control 0b10 */

879

} bcm2835PUDControl;

880

881

/* need a value for pud functions that can't work unless RPI 4 */

882

#define BCM2835_GPIO_PUD_ERROR 0x08

883

884

/*! Pad control register offsets from BCM2835_GPIO_PADS */

885

#define BCM2835_PADS_GPIO_0_27 0x002c /*!< Pad control register for pads 0 to 27 */

886

#define BCM2835_PADS_GPIO_28_45 0x0030 /*!< Pad control register for pads 28 to 45 */

887

#define BCM2835_PADS_GPIO_46_53 0x0034 /*!< Pad control register for pads 46 to 53 */

888

889

/*! Pad Control masks */

890

#define BCM2835_PAD_PASSWRD (0x5A << 24) /*!< Password to enable setting pad mask */

891

#define BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10 /*!< Slew rate unlimited */

892

#define BCM2835_PAD_HYSTERESIS_ENABLED 0x08 /*!< Hysteresis enabled */

893

#define BCM2835_PAD_DRIVE_2mA 0x00 /*!< 2mA drive current */

894

#define BCM2835_PAD_DRIVE_4mA 0x01 /*!< 4mA drive current */

895

#define BCM2835_PAD_DRIVE_6mA 0x02 /*!< 6mA drive current */

896

#define BCM2835_PAD_DRIVE_8mA 0x03 /*!< 8mA drive current */

897

#define BCM2835_PAD_DRIVE_10mA 0x04 /*!< 10mA drive current */

898

#define BCM2835_PAD_DRIVE_12mA 0x05 /*!< 12mA drive current */

899

#define BCM2835_PAD_DRIVE_14mA 0x06 /*!< 14mA drive current */

900

#define BCM2835_PAD_DRIVE_16mA 0x07 /*!< 16mA drive current */

901

902

/*! \brief bcm2835PadGroup

903

Pad group specification for bcm2835_gpio_pad()

*/

typedef enum

{

BCM2835_PAD_GROUP_GPIO_0_27 = 0, /*!< Pad group for GPIO pads 0 to 27 */

908

BCM2835_PAD_GROUP_GPIO_28_45 = 1, /*!< Pad group for GPIO pads 28 to 45 */

909

BCM2835_PAD_GROUP_GPIO_46_53 = 2 /*!< Pad group for GPIO pads 46 to 53 */

910

} bcm2835PadGroup;

911

912

/*! \brief GPIO Pin Numbers

913

914

Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers.

915

These can be passed as a pin number to any function requiring a pin.

916

Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins

917

and some can adopt an alternate function.

918

RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*.

919

RPi B+ has yet differnet pinouts and these are defined in RPI_BPLUS_*.

920

At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively

921

When SPI0 is in use (ie after bcm2835_spi_begin()), SPI0 pins are dedicated to SPI

922

and cant be controlled independently.

923

If you are using the RPi Compute Module, just use the GPIO number: there is no need to use one of these

symbolic names

*/

typedef enum

{

RPI_GPIO_P1_03 = 0, /*!< Version 1, Pin P1-03 */

929

RPI_GPIO_P1_05 = 1, /*!< Version 1, Pin P1-05 */

930

RPI_GPIO_P1_07 = 4, /*!< Version 1, Pin P1-07 */

931

RPI_GPIO_P1_08 = 14, /*!< Version 1, Pin P1-08, defaults to alt function 0 UART0_TXD */

932

RPI_GPIO_P1_10 = 15, /*!< Version 1, Pin P1-10, defaults to alt function 0 UART0_RXD */

933

RPI_GPIO_P1_11 = 17, /*!< Version 1, Pin P1-11 */

934

RPI_GPIO_P1_12 = 18, /*!< Version 1, Pin P1-12, can be PWM channel 0 in ALT FUN 5 */

935

RPI_GPIO_P1_13 = 21, /*!< Version 1, Pin P1-13 */

936

RPI_GPIO_P1_15 = 22, /*!< Version 1, Pin P1-15 */

937

RPI_GPIO_P1_16 = 23, /*!< Version 1, Pin P1-16 */

938

RPI_GPIO_P1_18 = 24, /*!< Version 1, Pin P1-18 */

939

RPI_GPIO_P1_19 = 10, /*!< Version 1, Pin P1-19, MOSI when SPI0 in use */

940

RPI_GPIO_P1_21 = 9, /*!< Version 1, Pin P1-21, MISO when SPI0 in use */

941

RPI_GPIO_P1_22 = 25, /*!< Version 1, Pin P1-22 */

942

RPI_GPIO_P1_23 = 11, /*!< Version 1, Pin P1-23, CLK when SPI0 in use */

943

RPI_GPIO_P1_24 = 8, /*!< Version 1, Pin P1-24, CE0 when SPI0 in use */

944

RPI_GPIO_P1_26 = 7, /*!< Version 1, Pin P1-26, CE1 when SPI0 in use */

945

946

/* RPi Version 2 */

947

RPI_V2_GPIO_P1_03 = 2, /*!< Version 2, Pin P1-03 */

948

RPI_V2_GPIO_P1_05 = 3, /*!< Version 2, Pin P1-05 */

949

RPI_V2_GPIO_P1_07 = 4, /*!< Version 2, Pin P1-07 */

950

RPI_V2_GPIO_P1_08 = 14, /*!< Version 2, Pin P1-08, defaults to alt function 0 UART0_TXD */

951

RPI_V2_GPIO_P1_10 = 15, /*!< Version 2, Pin P1-10, defaults to alt function 0 UART0_RXD */

952

RPI_V2_GPIO_P1_11 = 17, /*!< Version 2, Pin P1-11 */

953

RPI_V2_GPIO_P1_12 = 18, /*!< Version 2, Pin P1-12, can be PWM channel 0 in ALT FUN 5 */

954

RPI_V2_GPIO_P1_13 = 27, /*!< Version 2, Pin P1-13 */

955

RPI_V2_GPIO_P1_15 = 22, /*!< Version 2, Pin P1-15 */

956

RPI_V2_GPIO_P1_16 = 23, /*!< Version 2, Pin P1-16 */

957

RPI_V2_GPIO_P1_18 = 24, /*!< Version 2, Pin P1-18 */

958

RPI_V2_GPIO_P1_19 = 10, /*!< Version 2, Pin P1-19, MOSI when SPI0 in use */

959

RPI_V2_GPIO_P1_21 = 9, /*!< Version 2, Pin P1-21, MISO when SPI0 in use */

960

RPI_V2_GPIO_P1_22 = 25, /*!< Version 2, Pin P1-22 */

961

RPI_V2_GPIO_P1_23 = 11, /*!< Version 2, Pin P1-23, CLK when SPI0 in use */

962

RPI_V2_GPIO_P1_24 = 8, /*!< Version 2, Pin P1-24, CE0 when SPI0 in use */

963

RPI_V2_GPIO_P1_26 = 7, /*!< Version 2, Pin P1-26, CE1 when SPI0 in use */

964

RPI_V2_GPIO_P1_29 = 5, /*!< Version 2, Pin P1-29 */

965

RPI_V2_GPIO_P1_31 = 6, /*!< Version 2, Pin P1-31 */

966

RPI_V2_GPIO_P1_32 = 12, /*!< Version 2, Pin P1-32 */

967

RPI_V2_GPIO_P1_33 = 13, /*!< Version 2, Pin P1-33 */

968

RPI_V2_GPIO_P1_35 = 19, /*!< Version 2, Pin P1-35, can be PWM channel 1 in ALT FUN 5 */

969

RPI_V2_GPIO_P1_36 = 16, /*!< Version 2, Pin P1-36 */

970

RPI_V2_GPIO_P1_37 = 26, /*!< Version 2, Pin P1-37 */

971

RPI_V2_GPIO_P1_38 = 20, /*!< Version 2, Pin P1-38 */

972

RPI_V2_GPIO_P1_40 = 21, /*!< Version 2, Pin P1-40 */

973

974

/* RPi Version 2, new plug P5 */

975

RPI_V2_GPIO_P5_03 = 28, /*!< Version 2, Pin P5-03 */

976

RPI_V2_GPIO_P5_04 = 29, /*!< Version 2, Pin P5-04 */

977

RPI_V2_GPIO_P5_05 = 30, /*!< Version 2, Pin P5-05 */

978

RPI_V2_GPIO_P5_06 = 31, /*!< Version 2, Pin P5-06 */

979

980

/* RPi B+ J8 header, also RPi 2 40 pin GPIO header */

981

RPI_BPLUS_GPIO_J8_03 = 2, /*!< B+, Pin J8-03 */

982

RPI_BPLUS_GPIO_J8_05 = 3, /*!< B+, Pin J8-05 */

983

RPI_BPLUS_GPIO_J8_07 = 4, /*!< B+, Pin J8-07 */

984

RPI_BPLUS_GPIO_J8_08 = 14, /*!< B+, Pin J8-08, defaults to alt function 0 UART0_TXD */

985

RPI_BPLUS_GPIO_J8_10 = 15, /*!< B+, Pin J8-10, defaults to alt function 0 UART0_RXD */

986

RPI_BPLUS_GPIO_J8_11 = 17, /*!< B+, Pin J8-11 */

987

RPI_BPLUS_GPIO_J8_12 = 18, /*!< B+, Pin J8-12, can be PWM channel 0 in ALT FUN 5 */

988

RPI_BPLUS_GPIO_J8_13 = 27, /*!< B+, Pin J8-13 */

989

RPI_BPLUS_GPIO_J8_15 = 22, /*!< B+, Pin J8-15 */

990

RPI_BPLUS_GPIO_J8_16 = 23, /*!< B+, Pin J8-16 */

991

RPI_BPLUS_GPIO_J8_18 = 24, /*!< B+, Pin J8-18 */

992

RPI_BPLUS_GPIO_J8_19 = 10, /*!< B+, Pin J8-19, MOSI when SPI0 in use */

993

RPI_BPLUS_GPIO_J8_21 = 9, /*!< B+, Pin J8-21, MISO when SPI0 in use */

994

RPI_BPLUS_GPIO_J8_22 = 25, /*!< B+, Pin J8-22 */

995

RPI_BPLUS_GPIO_J8_23 = 11, /*!< B+, Pin J8-23, CLK when SPI0 in use */

996

RPI_BPLUS_GPIO_J8_24 = 8, /*!< B+, Pin J8-24, CE0 when SPI0 in use */

997

RPI_BPLUS_GPIO_J8_26 = 7, /*!< B+, Pin J8-26, CE1 when SPI0 in use */

998

RPI_BPLUS_GPIO_J8_29 = 5, /*!< B+, Pin J8-29, */

999

RPI_BPLUS_GPIO_J8_31 = 6, /*!< B+, Pin J8-31, */

1000

RPI_BPLUS_GPIO_J8_32 = 12, /*!< B+, Pin J8-32, */

1001

RPI_BPLUS_GPIO_J8_33 = 13, /*!< B+, Pin J8-33, */

1002

RPI_BPLUS_GPIO_J8_35 = 19, /*!< B+, Pin J8-35, can be PWM channel 1 in ALT FUN 5 */

1003

RPI_BPLUS_GPIO_J8_36 = 16, /*!< B+, Pin J8-36, */

1004

RPI_BPLUS_GPIO_J8_37 = 26, /*!< B+, Pin J8-37, */

1005

RPI_BPLUS_GPIO_J8_38 = 20, /*!< B+, Pin J8-38, */

1006

RPI_BPLUS_GPIO_J8_40 = 21 /*!< B+, Pin J8-40, */

} RPiGPIOPin;

/* Defines for AUX

GPIO register offsets from BCM2835_AUX_BASE.

1011

*/

1012

#define BCM2835_AUX_IRQ 0x0000 /*!< xxx */

1013

#define BCM2835_AUX_ENABLE 0x0004 /*!< */

1014

1015

#define BCM2835_AUX_ENABLE_UART1 0x01 /*!< */

1016

#define BCM2835_AUX_ENABLE_SPI0 0x02 /*!< SPI0 (SPI1 in the device) */

1017

#define BCM2835_AUX_ENABLE_SPI1 0x04 /*!< SPI1 (SPI2 in the device) */

1018

1019

1020

#define BCM2835_AUX_SPI_CNTL0 0x0000 /*!< */

1021

#define BCM2835_AUX_SPI_CNTL1 0x0004 /*!< */

1022

#define BCM2835_AUX_SPI_STAT 0x0008 /*!< */

1023

#define BCM2835_AUX_SPI_PEEK 0x000C /*!< Read but do not take from FF */

1024

#define BCM2835_AUX_SPI_IO 0x0020 /*!< Write = TX, read=RX */

1025

#define BCM2835_AUX_SPI_TXHOLD 0x0030 /*!< Write = TX keep CS, read=RX */

1026

1027

#define BCM2835_AUX_SPI_CLOCK_MIN 30500 /*!< 30,5kHz */

1028

#define BCM2835_AUX_SPI_CLOCK_MAX 125000000 /*!< 125Mhz */

1029

1030

#define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000 /*!< */

1031

#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF /*!< */

1032

#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 20 /*!< */

1033

1034

#define BCM2835_AUX_SPI_CNTL0_CS0_N 0x000C0000 /*!< CS 0 low */

1035

#define BCM2835_AUX_SPI_CNTL0_CS1_N 0x000A0000 /*!< CS 1 low */

1036

#define BCM2835_AUX_SPI_CNTL0_CS2_N 0x00060000 /*!< CS 2 low */

1037

1038

#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000 /*!< */

1039

#define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x00008000 /*!< */

1040

#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000 /*!< */

1041

#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x00003000 /*!< */

1042

#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x00000800 /*!< */

1043

#define BCM2835_AUX_SPI_CNTL0_CPHA_IN 0x00000400 /*!< */

1044

#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200 /*!< */

1045

#define BCM2835_AUX_SPI_CNTL0_CPHA_OUT 0x00000100 /*!< */

1046

#define BCM2835_AUX_SPI_CNTL0_CPOL 0x00000080 /*!< */

1047

#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x00000040 /*!< */

1048

#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F /*!< */

1049

1050

#define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x00000700 /*!< */

1051

#define BCM2835_AUX_SPI_CNTL1_IDLE 0x00000080 /*!< */

1052

#define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x00000040 /*!< */

1053

#define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x00000002 /*!< */

1054

#define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x00000001 /*!< */

1055

1056

#define BCM2835_AUX_SPI_STAT_TX_LVL 0xF0000000 /*!< */

1057

#define BCM2835_AUX_SPI_STAT_RX_LVL 0x00F00000 /*!< */

1058

#define BCM2835_AUX_SPI_STAT_TX_FULL 0x00000400 /*!< */

1059

#define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x00000200 /*!< */

1060

#define BCM2835_AUX_SPI_STAT_RX_FULL 0x00000100 /*!< */

1061

#define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x00000080 /*!< */

1062

#define BCM2835_AUX_SPI_STAT_BUSY 0x00000040 /*!< */

1063

#define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F /*!< */

1064

1065

/* Defines for SPI

1066

GPIO register offsets from BCM2835_SPI0_BASE.

1067

Offsets into the SPI Peripheral block in bytes per 10.5 SPI Register Map

1068

*/

1069

#define BCM2835_SPI0_CS 0x0000 /*!< SPI Master Control and Status */

1070

#define BCM2835_SPI0_FIFO 0x0004 /*!< SPI Master TX and RX FIFOs */

1071

#define BCM2835_SPI0_CLK 0x0008 /*!< SPI Master Clock Divider */

1072

#define BCM2835_SPI0_DLEN 0x000c /*!< SPI Master Data Length */

1073

#define BCM2835_SPI0_LTOH 0x0010 /*!< SPI LOSSI mode TOH */

1074

#define BCM2835_SPI0_DC 0x0014 /*!< SPI DMA DREQ Controls */

1075

1076

/* Register masks for SPI0_CS */

1077

#define BCM2835_SPI0_CS_LEN_LONG 0x02000000 /*!< Enable Long data word in Lossi mode if DMA_LEN is set */

1078

#define BCM2835_SPI0_CS_DMA_LEN 0x01000000 /*!< Enable DMA mode in Lossi mode */

1079

#define BCM2835_SPI0_CS_CSPOL2 0x00800000 /*!< Chip Select 2 Polarity */

1080

#define BCM2835_SPI0_CS_CSPOL1 0x00400000 /*!< Chip Select 1 Polarity */

1081

#define BCM2835_SPI0_CS_CSPOL0 0x00200000 /*!< Chip Select 0 Polarity */

1082

#define BCM2835_SPI0_CS_RXF 0x00100000 /*!< RXF - RX FIFO Full */

1083

#define BCM2835_SPI0_CS_RXR 0x00080000 /*!< RXR RX FIFO needs Reading (full) */

1084

#define BCM2835_SPI0_CS_TXD 0x00040000 /*!< TXD TX FIFO can accept Data */

1085

#define BCM2835_SPI0_CS_RXD 0x00020000 /*!< RXD RX FIFO contains Data */

1086

#define BCM2835_SPI0_CS_DONE 0x00010000 /*!< Done transfer Done */

1087

#define BCM2835_SPI0_CS_TE_EN 0x00008000 /*!< Unused */

1088

#define BCM2835_SPI0_CS_LMONO 0x00004000 /*!< Unused */

1089

#define BCM2835_SPI0_CS_LEN 0x00002000 /*!< LEN LoSSI enable */

1090

#define BCM2835_SPI0_CS_REN 0x00001000 /*!< REN Read Enable */

1091

#define BCM2835_SPI0_CS_ADCS 0x00000800 /*!< ADCS Automatically Deassert Chip Select */

1092

#define BCM2835_SPI0_CS_INTR 0x00000400 /*!< INTR Interrupt on RXR */

1093

#define BCM2835_SPI0_CS_INTD 0x00000200 /*!< INTD Interrupt on Done */

1094

#define BCM2835_SPI0_CS_DMAEN 0x00000100 /*!< DMAEN DMA Enable */

1095

#define BCM2835_SPI0_CS_TA 0x00000080 /*!< Transfer Active */

1096

#define BCM2835_SPI0_CS_CSPOL 0x00000040 /*!< Chip Select Polarity */

1097

#define BCM2835_SPI0_CS_CLEAR 0x00000030 /*!< Clear FIFO Clear RX and TX */

1098

#define BCM2835_SPI0_CS_CLEAR_RX 0x00000020 /*!< Clear FIFO Clear RX */

1099

#define BCM2835_SPI0_CS_CLEAR_TX 0x00000010 /*!< Clear FIFO Clear TX */

1100

#define BCM2835_SPI0_CS_CPOL 0x00000008 /*!< Clock Polarity */

1101

#define BCM2835_SPI0_CS_CPHA 0x00000004 /*!< Clock Phase */

1102

#define BCM2835_SPI0_CS_CS 0x00000003 /*!< Chip Select */

1103

1104

/*! \brief bcm2835SPIBitOrder SPI Bit order

1105

Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder()

*/

typedef enum

{

BCM2835_SPI_BIT_ORDER_LSBFIRST = 0, /*!< LSB First */

1110

BCM2835_SPI_BIT_ORDER_MSBFIRST = 1 /*!< MSB First */

1111

}bcm2835SPIBitOrder;

1112

1113

/*! \brief SPI Data mode

1114

Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()

*/

typedef enum

{

BCM2835_SPI_MODE0 = 0, /*!< CPOL = 0, CPHA = 0 */

1119

BCM2835_SPI_MODE1 = 1, /*!< CPOL = 0, CPHA = 1 */

1120

BCM2835_SPI_MODE2 = 2, /*!< CPOL = 1, CPHA = 0 */

1121

BCM2835_SPI_MODE3 = 3 /*!< CPOL = 1, CPHA = 1 */

1122

}bcm2835SPIMode;

1123

1124

/*! \brief bcm2835SPIChipSelect

1125

Specify the SPI chip select pin(s)

*/

typedef enum

{

BCM2835_SPI_CS0 = 0, /*!< Chip Select 0 */

1130

BCM2835_SPI_CS1 = 1, /*!< Chip Select 1 */

1131

BCM2835_SPI_CS2 = 2, /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */

1132

BCM2835_SPI_CS_NONE = 3 /*!< No CS, control it yourself */

1133

} bcm2835SPIChipSelect;

1134

1135

/*! \brief bcm2835SPIClockDivider

1136

Specifies the divider used to generate the SPI clock from the system clock.

1137

Figures below give the divider, clock period and clock frequency.

1138

Clock divided is based on nominal core clock rate of 250MHz on RPi1 and RPi2, and 400MHz on RPi3.

1139

It is reported that (contrary to the documentation) any even divider may used.

1140

The frequencies shown for each divider have been confirmed by measurement on RPi1 and RPi2.

1141

The system clock frequency on RPi3 is different, so the frequency you get from a given divider will be different.

1142

See comments in 'SPI Pins' for information about reliable SPI speeds.

1143

Note: it is possible to change the core clock rate of the RPi 3 back to 250MHz, by putting

\code

core_freq=250

\endcode

in the config.txt

*/

typedef enum

{

BCM2835_SPI_CLOCK_DIVIDER_65536 = 0, /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */

1152

BCM2835_SPI_CLOCK_DIVIDER_32768 = 32768, /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */

1153

BCM2835_SPI_CLOCK_DIVIDER_16384 = 16384, /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */

1154

BCM2835_SPI_CLOCK_DIVIDER_8192 = 8192, /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */

1155

BCM2835_SPI_CLOCK_DIVIDER_4096 = 4096, /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */

1156

BCM2835_SPI_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */

1157

BCM2835_SPI_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */

1158

BCM2835_SPI_CLOCK_DIVIDER_512 = 512, /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */

1159

BCM2835_SPI_CLOCK_DIVIDER_256 = 256, /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */

1160

BCM2835_SPI_CLOCK_DIVIDER_128 = 128, /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */

1161

BCM2835_SPI_CLOCK_DIVIDER_64 = 64, /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */

1162

BCM2835_SPI_CLOCK_DIVIDER_32 = 32, /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */

1163

BCM2835_SPI_CLOCK_DIVIDER_16 = 16, /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */

1164

BCM2835_SPI_CLOCK_DIVIDER_8 = 8, /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */

1165

    BCM2835_SPI_CLOCK_DIVIDER_4     = 4,       /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */

1166

    BCM2835_SPI_CLOCK_DIVIDER_2     = 2,       /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/

1167

BCM2835_SPI_CLOCK_DIVIDER_1 = 1 /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */

1168

} bcm2835SPIClockDivider;

1169

1170

/* Defines for I2C

1171

GPIO register offsets from BCM2835_BSC*_BASE.

1172

Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map

1173

*/

1174

#define BCM2835_BSC_C 0x0000 /*!< BSC Master Control */

1175

#define BCM2835_BSC_S 0x0004 /*!< BSC Master Status */

1176

#define BCM2835_BSC_DLEN 0x0008 /*!< BSC Master Data Length */

1177

#define BCM2835_BSC_A 0x000c /*!< BSC Master Slave Address */

1178

#define BCM2835_BSC_FIFO 0x0010 /*!< BSC Master Data FIFO */

1179

#define BCM2835_BSC_DIV 0x0014 /*!< BSC Master Clock Divider */

1180

#define BCM2835_BSC_DEL 0x0018 /*!< BSC Master Data Delay */

1181

#define BCM2835_BSC_CLKT 0x001c /*!< BSC Master Clock Stretch Timeout */

1182

1183

/* Register masks for BSC_C */

1184

#define BCM2835_BSC_C_I2CEN 0x00008000 /*!< I2C Enable, 0 = disabled, 1 = enabled */

1185

#define BCM2835_BSC_C_INTR 0x00000400 /*!< Interrupt on RX */

1186

#define BCM2835_BSC_C_INTT 0x00000200 /*!< Interrupt on TX */

1187

#define BCM2835_BSC_C_INTD 0x00000100 /*!< Interrupt on DONE */

1188

#define BCM2835_BSC_C_ST 0x00000080 /*!< Start transfer, 1 = Start a new transfer */

1189

#define BCM2835_BSC_C_CLEAR_1 0x00000020 /*!< Clear FIFO Clear */

1190

#define BCM2835_BSC_C_CLEAR_2 0x00000010 /*!< Clear FIFO Clear */

1191

#define BCM2835_BSC_C_READ 0x00000001 /*!< Read transfer */

1192

1193

/* Register masks for BSC_S */

1194

#define BCM2835_BSC_S_CLKT 0x00000200 /*!< Clock stretch timeout */

1195

#define BCM2835_BSC_S_ERR 0x00000100 /*!< ACK error */

1196

#define BCM2835_BSC_S_RXF 0x00000080 /*!< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */

1197

#define BCM2835_BSC_S_TXE 0x00000040 /*!< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */

1198

#define BCM2835_BSC_S_RXD 0x00000020 /*!< RXD FIFO contains data */

1199

#define BCM2835_BSC_S_TXD 0x00000010 /*!< TXD FIFO can accept data */

1200

#define BCM2835_BSC_S_RXR 0x00000008 /*!< RXR FIFO needs reading (full) */

1201

#define BCM2835_BSC_S_TXW 0x00000004 /*!< TXW FIFO needs writing (full) */

1202

#define BCM2835_BSC_S_DONE 0x00000002 /*!< Transfer DONE */

1203

#define BCM2835_BSC_S_TA 0x00000001 /*!< Transfer Active */

1204

1205

#define BCM2835_BSC_FIFO_SIZE 16 /*!< BSC FIFO size */

1206

1207

/*! \brief bcm2835I2CClockDivider

1208

Specifies the divider used to generate the I2C clock from the system clock.

1209

Clock divided is based on nominal base clock rate of 250MHz

*/

typedef enum

{

BCM2835_I2C_CLOCK_DIVIDER_2500 = 2500, /*!< 2500 = 10us = 100 kHz */

1214

BCM2835_I2C_CLOCK_DIVIDER_626 = 626, /*!< 622 = 2.504us = 399.3610 kHz */

1215

BCM2835_I2C_CLOCK_DIVIDER_150 = 150, /*!< 150 = 60ns = 1.666 MHz (default at reset) */

1216

BCM2835_I2C_CLOCK_DIVIDER_148 = 148 /*!< 148 = 59ns = 1.689 MHz */

1217

} bcm2835I2CClockDivider;

1218

1219

/*! \brief bcm2835I2CReasonCodes

1220

Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.

*/

typedef enum

{

BCM2835_I2C_REASON_OK = 0x00, /*!< Success */

1225

BCM2835_I2C_REASON_ERROR_NACK = 0x01, /*!< Received a NACK */

1226

BCM2835_I2C_REASON_ERROR_CLKT = 0x02, /*!< Received Clock Stretch Timeout */

1227

BCM2835_I2C_REASON_ERROR_DATA = 0x04 /*!< Not all data is sent / received */

1228

} bcm2835I2CReasonCodes;

1229

1230

/* Registers offets from BCM2835_SMI_BASE */

1231

#define BCM2835_SMI_CS 0 /*! < Control and status register > */

1232

#define BCM2835_SMI_LENGTH 1 /*! < Transfer length register > */

1233

#define BCM2835_SMI_ADRS 2 /*! < Transfer address register > */

1234

#define BCM2835_SMI_DATA 3 /*! < Transfer data register > */

1235

#define BCM2835_SMI_READ0 4 /*! < Read settings 0 register > */

1236

#define BCM2835_SMI_WRITE0 5 /*! < Write settings 0 register > */

1237

#define BCM2835_SMI_READ1 6 /*! < Read settings 1 register > */

1238

#define BCM2835_SMI_WRITE1 7 /*! < Write settings 1 register > */

1239

#define BCM2835_SMI_READ2 8 /*! < Read settings 2 register > */

1240

#define BCM2835_SMI_WRITE2 9 /*! < Write settings 2 register > */

1241

#define BCM2835_SMI_READ3 10 /*! < Read settings 3 register > */

1242

#define BCM2835_SMI_WRITE3 11 /*! < Write settings 3 register > */

1243

#define BCM2835_SMI_DMAC 12 /*! < DMA control register > */

1244

#define BCM2835_SMI_DIRCS 13 /*! < Direct control register > */

1245

#define BCM2835_SMI_DIRADDR 14 /*! < Direct access address register > */

1246

#define BCM2835_SMI_DIRDATA 15 /*! < Direct access data register > */

1247

1248

/* Register masks for SMI_READ and SMI_WRITE */

1249

#define BCM2835_SMI_RW_WIDTH_MSK 0xC0000000 /*! < Data width mask > */

1250

#define BCM2835_SMI_RW_WID8 0x00000000 /*! < Data width 8 bits > */

1251

#define BCM2835_SMI_RW_WID16 0x40000000 /*! < Data width 16 bits > */

1252

#define BCM2835_SMI_RW_WID18 0x80000000 /*! < Data width 18 bits > */

1253

#define BCM2835_SMI_RW_WID9 0xC0000000 /*! < Data width 9 bits > */

1254

#define BCM2835_SMI_RW_SETUP_MSK 0x3F000000 /*! < Setup cycles (6 bits) > */

1255

#define BCM2835_SMI_RW_SETUP_LS 24 /*! < Shift for setup cycles > */

1256

#define BCM2835_SMI_RW_MODE68 0x00800000 /*! < Run cycle motorola mode > */

1257

#define BCM2835_SMI_RW_MODE80 0x00000000 /*! < Run cycle intel mode > */

1258

#define BCM2835_SMI_READ_FSETUP 0x00400000 /*! < Read : Setup only for first cycle > */

1259

#define BCM2835_SMI_WRITE_SWAP 0x00400000 /*! < Write : swap pixel data > */

1260

#define BCM2835_SMI_RW_HOLD_MSK 0x003F0000 /*! < Hold cycles (6 bits) > */

1261

#define BCM2835_SMI_RW_HOLD_LS 16 /*! < Shift for hold cycles > */

1262

#define BCM2835_SMI_RW_PACEALL 0x00008000 /*! < Apply pacing always > */

1263

#define BCM2835_SMI_RW_PACE_MSK 0x00007F00 /*! < Pace cycles (7 bits) > */

1264

#define BCM2835_SMI_RW_PACE_LS 8 /*! < Shift for pace cycles > */

1265

#define BCM2835_SMI_RW_DREQ 0x00000080 /*! < Use DMA req on read/write > */

1266

#define BCM2835_SMI_RW_STROBE_MSK 0x0000007F /*! < Strobe cycles (7 bits) > */

1267

#define BCM2835_SMI_RW_STROBE_LS 0 /*! < Shift for strobe cycles > */

1268

1269

/* Registers masks for Direct Access control register */

1270

#define BCM2835_SMI_DIRCS_ENABLE 0x00000001 /*! < Set to enable SMI. 0 = Read from ext. devices > */

1271

#define BCM2835_SMI_DIRCS_START 0x00000002 /*! < Initiate SMI transfer > */

1272

#define BCM2835_SMI_DIRCS_DONE 0x00000004 /*! < Set if transfer has finished / Write to clear flag > */

1273

#define BCM2835_SMI_DIRCS_WRITE 0x00000008 /*! < 1 = Write to ext. devices > */

1274

1275

/* Registers masks for Direct Access address register */

1276

#define BCM2835_SMI_DIRADRS_DEV_MSK 0x00000300 /*! < Timing configuration slot > */

1277

#define BCM2835_SMI_DIRADRS_DEV_LS 8 /*! < Shift for configuration slot > */

1278

#define BCM2835_SMI_DIRADRS_DEV0 0x00000000 /*! < Use timing config slot 0 > */

1279

#define BCM2835_SMI_DIRADRS_DEV1 0x00000100 /*! < Use timing config slot 1 > */

1280

#define BCM2835_SMI_DIRADRS_DEV2 0x00000200 /*! < Use timing config slot 2 > */

1281

#define BCM2835_SMI_DIRADRS_DEV3 0x00000300 /*! < Use timing config slot 3 > */

1282

#define BCM2835_SMI_DIRADRS_MSK 0x0000003F /*! < Adress bits SA5..SA0 > */

1283

#define BCM2835_SMI_DIRADRS_LS 0 /*! < Shift for address bits > */

1284

1285

/* SMI clock control registers : defined as offset from bcm2835_clk */

1286

#define SMICLK_CNTL (44) /* = 0xB0 */

1287

#define SMICLK_DIV (45) /* = 0xB4 */

/* Defines for ST

GPIO register offsets from BCM2835_ST_BASE.

1292

Offsets into the ST Peripheral block in bytes per 12.1 System Timer Registers

1293

The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter.

1294

BCM2835_ST_CLO is the System Timer Counter Lower bits register.

1295

The system timer free-running counter lower register is a read-only register that returns the current value

1296

of the lower 32-bits of the free running counter.

1297

BCM2835_ST_CHI is the System Timer Counter Upper bits register.

1298

The system timer free-running counter upper register is a read-only register that returns the current value

1299

of the upper 32-bits of the free running counter.

1300

*/

1301

#define BCM2835_ST_CS 0x0000 /*!< System Timer Control/Status */

1302

#define BCM2835_ST_CLO 0x0004 /*!< System Timer Counter Lower 32 bits */

1303

#define BCM2835_ST_CHI 0x0008 /*!< System Timer Counter Upper 32 bits */

/*! @} */

/* Defines for PWM, word offsets (ie 4 byte multiples) */

1309

#define BCM2835_PWM_CONTROL 0

1310

#define BCM2835_PWM_STATUS 1

1311

#define BCM2835_PWM_DMAC 2

1312

#define BCM2835_PWM0_RANGE 4

1313

#define BCM2835_PWM0_DATA 5

1314

#define BCM2835_PWM_FIF1 6

1315

#define BCM2835_PWM1_RANGE 8

1316

#define BCM2835_PWM1_DATA 9

1317

1318

/* Defines for PWM Clock, word offsets (ie 4 byte multiples) */

1319

#define BCM2835_PWMCLK_CNTL 40

1320

#define BCM2835_PWMCLK_DIV 41

1321

#define BCM2835_PWM_PASSWRD (0x5A << 24) /*!< Password to enable setting PWM clock */

1322

1323

#define BCM2835_PWM1_MS_MODE 0x8000 /*!< Run in Mark/Space mode */

1324

#define BCM2835_PWM1_USEFIFO 0x2000 /*!< Data from FIFO */

1325

#define BCM2835_PWM1_REVPOLAR 0x1000 /*!< Reverse polarity */

1326

#define BCM2835_PWM1_OFFSTATE 0x0800 /*!< Ouput Off state */

1327

#define BCM2835_PWM1_REPEATFF 0x0400 /*!< Repeat last value if FIFO empty */

1328

#define BCM2835_PWM1_SERIAL 0x0200 /*!< Run in serial mode */

1329

#define BCM2835_PWM1_ENABLE 0x0100 /*!< Channel Enable */

1330

1331

#define BCM2835_PWM0_MS_MODE 0x0080 /*!< Run in Mark/Space mode */

1332

#define BCM2835_PWM_CLEAR_FIFO 0x0040 /*!< Clear FIFO */

1333

#define BCM2835_PWM0_USEFIFO 0x0020 /*!< Data from FIFO */

1334

#define BCM2835_PWM0_REVPOLAR 0x0010 /*!< Reverse polarity */

1335

#define BCM2835_PWM0_OFFSTATE 0x0008 /*!< Ouput Off state */

1336

#define BCM2835_PWM0_REPEATFF 0x0004 /*!< Repeat last value if FIFO empty */

1337

#define BCM2835_PWM0_SERIAL 0x0002 /*!< Run in serial mode */

1338

#define BCM2835_PWM0_ENABLE 0x0001 /*!< Channel Enable */

1339

1340

/*! \brief bcm2835PWMClockDivider

1341

Specifies the divider used to generate the PWM clock from the system clock.

1342

Figures below give the divider, clock period and clock frequency.

1343

Clock divided is based on nominal PWM base clock rate of 19.2MHz

1344

The frequencies shown for each divider have been confirmed by measurement

*/

typedef enum

{

BCM2835_PWM_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 9.375kHz */

1349

BCM2835_PWM_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 18.75kHz */

1350

BCM2835_PWM_CLOCK_DIVIDER_512 = 512, /*!< 512 = 37.5kHz */

1351

BCM2835_PWM_CLOCK_DIVIDER_256 = 256, /*!< 256 = 75kHz */

1352

BCM2835_PWM_CLOCK_DIVIDER_128 = 128, /*!< 128 = 150kHz */

1353

BCM2835_PWM_CLOCK_DIVIDER_64 = 64, /*!< 64 = 300kHz */

1354

BCM2835_PWM_CLOCK_DIVIDER_32 = 32, /*!< 32 = 600.0kHz */

1355

BCM2835_PWM_CLOCK_DIVIDER_16 = 16, /*!< 16 = 1.2MHz */

1356

BCM2835_PWM_CLOCK_DIVIDER_8 = 8, /*!< 8 = 2.4MHz */

1357

BCM2835_PWM_CLOCK_DIVIDER_4 = 4, /*!< 4 = 4.8MHz */

1358

BCM2835_PWM_CLOCK_DIVIDER_2 = 2, /*!< 2 = 9.6MHz, fastest you can get */

1359

BCM2835_PWM_CLOCK_DIVIDER_1 = 1 /*!< 1 = 4.6875kHz, same as divider 4096 */

1360

} bcm2835PWMClockDivider;

1361

1362

/* Historical name compatibility */

1363

#ifndef BCM2835_NO_DELAY_COMPATIBILITY

1364

#define delay(x) bcm2835_delay(x)

1365

#define delayMicroseconds(x) bcm2835_delayMicroseconds(x)

#endif

#ifdef __cplusplus

extern "C" {

#endif

/*! \defgroup init Library initialisation and management

1373

These functions allow you to intialise and control the bcm2835 library

@{

*/

/*! Initialise the library by opening /dev/mem (if you are root)

1378

or /dev/gpiomem (if you are not)

1379

and getting pointers to the

1380

internal memory for BCM 2835 device registers. You must call this (successfully)

1381

before calling any other

1382

functions in this library (except bcm2835_set_debug).

1383

If bcm2835_init() fails by returning 0,

1384

calling any other function may result in crashes or other failures.

1385

If bcm2835_init() succeeds but you are not running as root, then only gpio operations

1386

are permitted, and calling any other functions may result in crashes or other failures. .

1387

Prints messages to stderr in case of errors.

1388

\return 1 if successful else 0

1389

*/

1390

extern int bcm2835_init(void);

1391

1392

/*! Close the library, deallocating any allocated memory and closing /dev/mem

1393

\return 1 if successful else 0

1394

*/

1395

extern int bcm2835_close(void);

1396

1397

/*! Sets the debug level of the library.

1398

A value of 1 prevents mapping to /dev/mem, and makes the library print out

1399

what it would do, rather than accessing the GPIO registers.

1400

A value of 0, the default, causes normal operation.

1401

Call this before calling bcm2835_init();

1402

\param[in] debug The new debug level. 1 means debug

1403

*/

1404

extern void bcm2835_set_debug(uint8_t debug);

1405

1406

/*! Returns the version number of the library, same as BCM2835_VERSION

1407

\return the current library version number

1408

*/

1409

extern unsigned int bcm2835_version(void);

/*! @} */

/*! \defgroup lowlevel Low level register access

1414

These functions provide low level register access, and should not generally

need to be used

@{

*/

/*! Gets the base of a register

1421

\param[in] regbase You can use one of the common values BCM2835_REGBASE_*

1422

in \ref bcm2835RegisterBase

1423

\return the register base

1424

\sa Physical Addresses

1425

*/

1426

extern uint32_t* bcm2835_regbase(uint8_t regbase);

1427

1428

/*! Reads 32 bit value from a peripheral address WITH a memory barrier before and after each read.

1429

This is safe, but slow. The MB before protects this read from any in-flight reads that didn't

1430

use a MB. The MB after protects subsequent reads from another peripheral.

1431

1432

\param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.

1433

\return the value read from the 32 bit register

1434

\sa Physical Addresses

1435

*/

1436

extern uint32_t bcm2835_peri_read(volatile uint32_t* paddr);

1437

1438

/*! Reads 32 bit value from a peripheral address WITHOUT the read barriers

1439

You should only use this when:

1440

o your code has previously called bcm2835_peri_read() for a register

1441

within the same peripheral, and no read or write to another peripheral has occurred since.

1442

o your code has called bcm2835_memory_barrier() since the last access to ANOTHER peripheral.

1443

1444

\param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.

1445

\return the value read from the 32 bit register

1446

\sa Physical Addresses

1447

*/

1448

extern uint32_t bcm2835_peri_read_nb(volatile uint32_t* paddr);

1449

1450

1451

/*! Writes 32 bit value from a peripheral address WITH a memory barrier before and after each write

1452

This is safe, but slow. The MB before ensures that any in-flight write to another peripheral

1453

completes before this write is issued. The MB after ensures that subsequent reads and writes

1454

to another peripheral will see the effect of this write.

1455

1456

This is a tricky optimization; if you aren't sure, use the barrier version.

1457

1458

\param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.

1459

\param[in] value The 32 bit value to write

1460

\sa Physical Addresses

1461

*/

1462

extern void bcm2835_peri_write(volatile uint32_t* paddr, uint32_t value);

1463

1464

/*! Writes 32 bit value from a peripheral address without the write barrier

1465

You should only use this when:

1466

o your code has previously called bcm2835_peri_write() for a register

1467

within the same peripheral, and no other peripheral access has occurred since.

1468

o your code has called bcm2835_memory_barrier() since the last access to ANOTHER peripheral.

1469

1470

This is a tricky optimization; if you aren't sure, use the barrier version.

1471

1472

\param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.

1473

\param[in] value The 32 bit value to write

1474

\sa Physical Addresses

1475

*/

1476

extern void bcm2835_peri_write_nb(volatile uint32_t* paddr, uint32_t value);

1477

1478

/*! Alters a number of bits in a 32 peripheral regsiter.

1479

It reads the current valu and then alters the bits defines as 1 in mask,

1480

according to the bit value in value.

1481

All other bits that are 0 in the mask are unaffected.

1482

Use this to alter a subset of the bits in a register.

1483

Memory barriers are used. Note that this is not atomic; an interrupt

1484

routine can cause unexpected results.

1485

\param[in] paddr Physical address to read from. See BCM2835_GPIO_BASE etc.

1486

\param[in] value The 32 bit value to write, masked in by mask.

1487

\param[in] mask Bitmask that defines the bits that will be altered in the register.

1488

\sa Physical Addresses

1489

*/

1490

extern void bcm2835_peri_set_bits(volatile uint32_t* paddr, uint32_t value, uint32_t mask);

1491

/*! @} end of lowlevel */

1492

1493

/*! \defgroup gpio GPIO register access

1494

These functions allow you to control the GPIO interface. You can set the

1495

function of each GPIO pin, read the input state and set the output state.

@{

*/

/*! Sets the Function Select register for the given pin, which configures

1500

the pin as Input, Output or one of the 6 alternate functions.

1501

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1502

\param[in] mode Mode to set the pin to, one of BCM2835_GPIO_FSEL_* from \ref bcm2835FunctionSelect

1503

*/

1504

extern void bcm2835_gpio_fsel(uint8_t pin, uint8_t mode);

1505

1506

/*! Sets the specified pin output to

1507

HIGH.

1508

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1509

\sa bcm2835_gpio_write()

1510

*/

1511

extern void bcm2835_gpio_set(uint8_t pin);

1512

1513

/*! Sets the specified pin output to

1514

LOW.

1515

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1516

\sa bcm2835_gpio_write()

1517

*/

1518

extern void bcm2835_gpio_clr(uint8_t pin);

1519

1520

/*! Sets any of the first 32 GPIO output pins specified in the mask to

1521

HIGH.

1522

\param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)

1523

\sa bcm2835_gpio_write_multi()

1524

*/

1525

extern void bcm2835_gpio_set_multi(uint32_t mask);

1526

1527

/*! Sets any of the first 32 GPIO output pins specified in the mask to

1528

LOW.

1529

\param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)

1530

\sa bcm2835_gpio_write_multi()

1531

*/

1532

extern void bcm2835_gpio_clr_multi(uint32_t mask);

1533

1534

/*! Reads the current level on the specified

1535

pin and returns either HIGH or LOW. Works whether or not the pin

1536

is an input or an output.

1537

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1538

\return the current level either HIGH or LOW

1539

*/

1540

extern uint8_t bcm2835_gpio_lev(uint8_t pin);

1541

1542

/*! Event Detect Status.

1543

Tests whether the specified pin has detected a level or edge

1544

as requested by bcm2835_gpio_ren(), bcm2835_gpio_fen(), bcm2835_gpio_hen(),

1545

bcm2835_gpio_len(), bcm2835_gpio_aren(), bcm2835_gpio_afen().

1546

Clear the flag for a given pin by calling bcm2835_gpio_set_eds(pin);

1547

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1548

\return HIGH if the event detect status for the given pin is true.

1549

*/

1550

extern uint8_t bcm2835_gpio_eds(uint8_t pin);

1551

1552

/*! Same as bcm2835_gpio_eds() but checks if any of the pins specified in

1553

the mask have detected a level or edge.

1554

\param[in] mask Mask of pins to check. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)

1555

\return Mask of pins HIGH if the event detect status for the given pin is true.

1556

*/

1557

extern uint32_t bcm2835_gpio_eds_multi(uint32_t mask);

1558

1559

/*! Sets the Event Detect Status register for a given pin to 1,

1560

which has the effect of clearing the flag. Use this afer seeing

1561

an Event Detect Status on the pin.

1562

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1563

*/

1564

extern void bcm2835_gpio_set_eds(uint8_t pin);

1565

1566

/*! Same as bcm2835_gpio_set_eds() but clears the flag for any pin which

1567

is set in the mask.

1568

\param[in] mask Mask of pins to clear. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)

1569

*/

1570

extern void bcm2835_gpio_set_eds_multi(uint32_t mask);

1571

1572

/*! Enable Rising Edge Detect Enable for the specified pin.

1573

When a rising edge is detected, sets the appropriate pin in Event Detect Status.

1574

The GPRENn registers use

1575

synchronous edge detection. This means the input signal is sampled using the

1576

system clock and then it is looking for a ?011? pattern on the sampled signal. This

1577

has the effect of suppressing glitches.

1578

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1579

*/

1580

extern void bcm2835_gpio_ren(uint8_t pin);

1581

1582

/*! Disable Rising Edge Detect Enable for the specified pin.

1583

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1584

*/

1585

extern void bcm2835_gpio_clr_ren(uint8_t pin);

1586

1587

/*! Enable Falling Edge Detect Enable for the specified pin.

1588

When a falling edge is detected, sets the appropriate pin in Event Detect Status.

1589

The GPRENn registers use

1590

synchronous edge detection. This means the input signal is sampled using the

1591

system clock and then it is looking for a ?100? pattern on the sampled signal. This

1592

has the effect of suppressing glitches.

1593

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1594

*/

1595

extern void bcm2835_gpio_fen(uint8_t pin);

1596

1597

/*! Disable Falling Edge Detect Enable for the specified pin.

1598

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1599

*/

1600

extern void bcm2835_gpio_clr_fen(uint8_t pin);

1601

1602

/*! Enable High Detect Enable for the specified pin.

1603

When a HIGH level is detected on the pin, sets the appropriate pin in Event Detect Status.

1604

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1605

*/

1606

extern void bcm2835_gpio_hen(uint8_t pin);

1607

1608

/*! Disable High Detect Enable for the specified pin.

1609

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1610

*/

1611

extern void bcm2835_gpio_clr_hen(uint8_t pin);

1612

1613

/*! Enable Low Detect Enable for the specified pin.

1614

When a LOW level is detected on the pin, sets the appropriate pin in Event Detect Status.

1615

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1616

*/

1617

extern void bcm2835_gpio_len(uint8_t pin);

1618

1619

/*! Disable Low Detect Enable for the specified pin.

1620

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1621

*/

1622

extern void bcm2835_gpio_clr_len(uint8_t pin);

1623

1624

/*! Enable Asynchronous Rising Edge Detect Enable for the specified pin.

1625

When a rising edge is detected, sets the appropriate pin in Event Detect Status.

1626

Asynchronous means the incoming signal is not sampled by the system clock. As such

1627

rising edges of very short duration can be detected.

1628

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1629

*/

1630

extern void bcm2835_gpio_aren(uint8_t pin);

1631

1632

/*! Disable Asynchronous Rising Edge Detect Enable for the specified pin.

1633

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1634

*/

1635

extern void bcm2835_gpio_clr_aren(uint8_t pin);

1636

1637

/*! Enable Asynchronous Falling Edge Detect Enable for the specified pin.

1638

When a falling edge is detected, sets the appropriate pin in Event Detect Status.

1639

Asynchronous means the incoming signal is not sampled by the system clock. As such

1640

falling edges of very short duration can be detected.

1641

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1642

*/

1643

extern void bcm2835_gpio_afen(uint8_t pin);

1644

1645

/*! Disable Asynchronous Falling Edge Detect Enable for the specified pin.

1646

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1647

*/

1648

extern void bcm2835_gpio_clr_afen(uint8_t pin);

1649

1650

/*! Sets the Pull-up/down register for the given pin. This is

1651

used with bcm2835_gpio_pudclk() to set the Pull-up/down resistor for the given pin.

1652

However, it is usually more convenient to use bcm2835_gpio_set_pud().

1653

\param[in] pud The desired Pull-up/down mode. One of BCM2835_GPIO_PUD_* from bcm2835PUDControl

1654

On the RPI 4, although this function and bcm2835_gpio_pudclk() are supported for backward

1655

compatibility, new code should always use bcm2835_gpio_set_pud().

1656

\sa bcm2835_gpio_set_pud()

1657

*/

1658

extern void bcm2835_gpio_pud(uint8_t pud);

1659

1660

/*! Clocks the Pull-up/down value set earlier by bcm2835_gpio_pud() into the pin.

1661

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1662

\param[in] on HIGH to clock the value from bcm2835_gpio_pud() into the pin.

1663

LOW to remove the clock.

1664

1665

On the RPI 4, although this function and bcm2835_gpio_pud() are supported for backward

1666

compatibility, new code should always use bcm2835_gpio_set_pud().

1667

1668

\sa bcm2835_gpio_set_pud()

1669

*/

1670

extern void bcm2835_gpio_pudclk(uint8_t pin, uint8_t on);

1671

1672

/*! Reads and returns the Pad Control for the given GPIO group.

1673

Caution: requires root access.

1674

\param[in] group The GPIO pad group number, one of BCM2835_PAD_GROUP_GPIO_*

1675

\return Mask of bits from BCM2835_PAD_* from \ref bcm2835PadGroup

1676

*/

1677

extern uint32_t bcm2835_gpio_pad(uint8_t group);

1678

1679

/*! Sets the Pad Control for the given GPIO group.

1680

Caution: requires root access.

1681

\param[in] group The GPIO pad group number, one of BCM2835_PAD_GROUP_GPIO_*

1682

\param[in] control Mask of bits from BCM2835_PAD_* from \ref bcm2835PadGroup. Note

1683

that it is not necessary to include BCM2835_PAD_PASSWRD in the mask as this

1684

is automatically included.

1685

*/

1686

extern void bcm2835_gpio_set_pad(uint8_t group, uint32_t control);

1687

1688

/*! Delays for the specified number of milliseconds.

1689

Uses nanosleep(), and therefore does not use CPU until the time is up.

1690

However, you are at the mercy of nanosleep(). From the manual for nanosleep():

1691

If the interval specified in req is not an exact multiple of the granularity

1692

underlying clock (see time(7)), then the interval will be

1693

rounded up to the next multiple. Furthermore, after the sleep completes,

1694

there may still be a delay before the CPU becomes free to once

1695

again execute the calling thread.

1696

\param[in] millis Delay in milliseconds

1697

*/

1698

extern void bcm2835_delay (unsigned int millis);

1699

1700

/*! Delays for the specified number of microseconds.

1701

Uses a combination of nanosleep() and a busy wait loop on the BCM2835 system timers,

1702

However, you are at the mercy of nanosleep(). From the manual for nanosleep():

1703

If the interval specified in req is not an exact multiple of the granularity

1704

underlying clock (see time(7)), then the interval will be

1705

rounded up to the next multiple. Furthermore, after the sleep completes,

1706

there may still be a delay before the CPU becomes free to once

1707

again execute the calling thread.

1708

For times less than about 450 microseconds, uses a busy wait on the System Timer.

1709

It is reported that a delay of 0 microseconds on RaspberryPi will in fact

1710

result in a delay of about 80 microseconds. Your mileage may vary.

1711

\param[in] micros Delay in microseconds

1712

*/

1713

extern void bcm2835_delayMicroseconds (uint64_t micros);

1714

1715

/*! Sets the output state of the specified pin

1716

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1717

\param[in] on HIGH sets the output to HIGH and LOW to LOW.

1718

*/

1719

extern void bcm2835_gpio_write(uint8_t pin, uint8_t on);

1720

1721

/*! Sets any of the first 32 GPIO output pins specified in the mask to the state given by on

1722

\param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)

1723

\param[in] on HIGH sets the output to HIGH and LOW to LOW.

1724

*/

1725

extern void bcm2835_gpio_write_multi(uint32_t mask, uint8_t on);

1726

1727

/*! Sets the first 32 GPIO output pins specified in the mask to the value given by value

1728

\param[in] value values required for each bit masked in by mask, eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)

1729

\param[in] mask Mask of pins to affect. Use eg: (1 << RPI_GPIO_P1_03) | (1 << RPI_GPIO_P1_05)

1730

*/

1731

extern void bcm2835_gpio_write_mask(uint32_t value, uint32_t mask);

1732

1733

/*! Sets the Pull-up/down mode for the specified pin. This is more convenient than

1734

clocking the mode in with bcm2835_gpio_pud() and bcm2835_gpio_pudclk().

1735

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1736

\param[in] pud The desired Pull-up/down mode. One of BCM2835_GPIO_PUD_* from bcm2835PUDControl

1737

*/

1738

extern void bcm2835_gpio_set_pud(uint8_t pin, uint8_t pud);

1739

1740

/*! On the BCM2711 based RPI 4, gets the current Pull-up/down mode for the specified pin.

1741

Returns one of BCM2835_GPIO_PUD_* from bcm2835PUDControl.

1742

On earlier RPI versions not based on the BCM2711, returns BCM2835_GPIO_PUD_ERROR

1743

\param[in] pin GPIO number, or one of RPI_GPIO_P1_* from \ref RPiGPIOPin.

1744

*/

1745

1746

extern uint8_t bcm2835_gpio_get_pud(uint8_t pin);

/*! @} */

/*! \defgroup spi SPI access

1751

These functions let you use SPI0 (Serial Peripheral Interface) to

1752

interface with an external SPI device.

@{

*/

/*! Start SPI operations.

1757

Forces RPi SPI0 pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)

1758

to alternate function ALT0, which enables those pins for SPI interface.

1759

You should call bcm2835_spi_end() when all SPI funcitons are complete to return the pins to

1760

their default functions.

1761

\sa bcm2835_spi_end()

1762

\return 1 if successful, 0 otherwise (perhaps because you are not running as root)

1763

*/

1764

extern int bcm2835_spi_begin(void);

1765

1766

/*! End SPI operations.

1767

SPI0 pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)

1768

are returned to their default INPUT behaviour.

1769

*/

1770

extern void bcm2835_spi_end(void);

1771

1772

/*! Sets the SPI bit order

1773

Set the bit order to be used for transmit and receive. The bcm2835 SPI0 only supports BCM2835_SPI_BIT_ORDER_MSB,

1774

so if you select BCM2835_SPI_BIT_ORDER_LSB, the bytes will be reversed in software.

1775

The library defaults to BCM2835_SPI_BIT_ORDER_MSB.

1776

\param[in] order The desired bit order, one of BCM2835_SPI_BIT_ORDER_*,

1777

see \ref bcm2835SPIBitOrder

1778

*/

1779

extern void bcm2835_spi_setBitOrder(uint8_t order);

1780

1781

/*! Sets the SPI clock divider and therefore the

1782

SPI clock speed.

1783

\param[in] divider The desired SPI clock divider, one of BCM2835_SPI_CLOCK_DIVIDER_*,

1784

see \ref bcm2835SPIClockDivider

1785

*/

1786

extern void bcm2835_spi_setClockDivider(uint16_t divider);

1787

1788

/*! Sets the SPI clock divider by converting the speed parameter to

1789

the equivalent SPI clock divider. ( see \sa bcm2835_spi_setClockDivider)

1790

\param[in] speed_hz The desired SPI clock speed in Hz

1791

*/

1792

extern void bcm2835_spi_set_speed_hz(uint32_t speed_hz);

1793

1794

/*! Sets the SPI data mode

1795

Sets the clock polariy and phase

1796

\param[in] mode The desired data mode, one of BCM2835_SPI_MODE*,

1797

see \ref bcm2835SPIMode

1798

*/

1799

extern void bcm2835_spi_setDataMode(uint8_t mode);

1800

1801

/*! Sets the chip select pin(s)

1802

When an bcm2835_spi_transfer() is made, the selected pin(s) will be asserted during the

1803

transfer.

1804

\param[in] cs Specifies the CS pins(s) that are used to activate the desired slave.

1805

One of BCM2835_SPI_CS*, see \ref bcm2835SPIChipSelect

1806

*/

1807

extern void bcm2835_spi_chipSelect(uint8_t cs);

1808

1809

/*! Sets the chip select pin polarity for a given pin

1810

When an bcm2835_spi_transfer() occurs, the currently selected chip select pin(s)

1811

will be asserted to the

1812

value given by active. When transfers are not happening, the chip select pin(s)

1813

return to the complement (inactive) value.

1814

\param[in] cs The chip select pin to affect

1815

\param[in] active Whether the chip select pin is to be active HIGH

1816

*/

1817

extern void bcm2835_spi_setChipSelectPolarity(uint8_t cs, uint8_t active);

1818

1819

/*! Transfers one byte to and from the currently selected SPI slave.

1820

Asserts the currently selected CS pins (as previously set by bcm2835_spi_chipSelect)

1821

during the transfer.

1822

Clocks the 8 bit value out on MOSI, and simultaneously clocks in data from MISO.

1823

Returns the read data byte from the slave.

1824

Uses polled transfer as per section 10.6.1 of the BCM 2835 ARM Peripherls manual

1825

\param[in] value The 8 bit data byte to write to MOSI

1826

\return The 8 bit byte simultaneously read from MISO

1827

\sa bcm2835_spi_transfern()

1828

*/

1829

extern uint8_t bcm2835_spi_transfer(uint8_t value);

1830

1831

/*! Transfers any number of bytes to and from the currently selected SPI slave.

1832

Asserts the currently selected CS pins (as previously set by bcm2835_spi_chipSelect)

1833

during the transfer.

1834

Clocks the len 8 bit bytes out on MOSI, and simultaneously clocks in data from MISO.

1835

The data read read from the slave is placed into rbuf. rbuf must be at least len bytes long

1836

Uses polled transfer as per section 10.6.1 of the BCM 2835 ARM Peripherls manual

1837

\param[in] tbuf Buffer of bytes to send.

1838

\param[out] rbuf Received bytes will by put in this buffer

1839

\param[in] len Number of bytes in the tbuf buffer, and the number of bytes to send/received

1840

\sa bcm2835_spi_transfer()

1841

*/

1842

extern void bcm2835_spi_transfernb(char* tbuf, char* rbuf, uint32_t len);

1843

1844

/*! Transfers any number of bytes to and from the currently selected SPI slave

1845

using bcm2835_spi_transfernb.

1846

The returned data from the slave replaces the transmitted data in the buffer.

1847

\param[in,out] buf Buffer of bytes to send. Received bytes will replace the contents

1848

\param[in] len Number of bytes int eh buffer, and the number of bytes to send/received

1849

\sa bcm2835_spi_transfer()

1850

*/

1851

extern void bcm2835_spi_transfern(char* buf, uint32_t len);

1852

1853

/*! Transfers any number of bytes to the currently selected SPI slave.

1854

Asserts the currently selected CS pins (as previously set by bcm2835_spi_chipSelect)

1855

during the transfer.

1856

\param[in] buf Buffer of bytes to send.

1857

\param[in] len Number of bytes in the buf buffer, and the number of bytes to send

1858

*/

1859

extern void bcm2835_spi_writenb(const char* buf, uint32_t len);

1860

1861

/*! Transfers half-word to the currently selected SPI slave.

1862

Asserts the currently selected CS pins (as previously set by bcm2835_spi_chipSelect)

1863

during the transfer.

1864

Clocks the 8 bit value out on MOSI, and simultaneously clocks in data from MISO.

1865

Uses polled transfer as per section 10.6.1 of the BCM 2835 ARM Peripherls manual

1866

\param[in] data The 8 bit data byte to write to MOSI

1867

\sa bcm2835_spi_writenb()

1868

*/

1869

extern void bcm2835_spi_write(uint16_t data);

1870

1871

/*! Start AUX SPI operations.

1872

Forces RPi AUX SPI pins P1-38 (MOSI), P1-38 (MISO), P1-40 (CLK) and P1-36 (CE2)

1873

to alternate function ALT4, which enables those pins for SPI interface.

1874

\return 1 if successful, 0 otherwise (perhaps because you are not running as root)

1875

*/

1876

extern int bcm2835_aux_spi_begin(void);

1877

1878

/*! End AUX SPI operations.

1879

SPI1 pins P1-38 (MOSI), P1-38 (MISO), P1-40 (CLK) and P1-36 (CE2)

1880

are returned to their default INPUT behaviour.

1881

*/

1882

extern void bcm2835_aux_spi_end(void);

1883

1884

/*! Sets the AUX SPI clock divider and therefore the AUX SPI clock speed.

1885

\param[in] divider The desired AUX SPI clock divider.

1886

*/

1887

extern void bcm2835_aux_spi_setClockDivider(uint16_t divider);

1888

1889

/*!

1890

* Calculates the input for \sa bcm2835_aux_spi_setClockDivider

1891

* @param speed_hz A value between \sa BCM2835_AUX_SPI_CLOCK_MIN and \sa BCM2835_AUX_SPI_CLOCK_MAX

1892

* @return Input for \sa bcm2835_aux_spi_setClockDivider

1893

*/

1894

extern uint16_t bcm2835_aux_spi_CalcClockDivider(uint32_t speed_hz);

1895

1896

/*! Transfers half-word to the AUX SPI slave.

1897

Asserts the currently selected CS pins during the transfer.

1898

\param[in] data The 8 bit data byte to write to MOSI

1899

\return The 16 bit byte simultaneously read from MISO

1900

\sa bcm2835_spi_transfern()

1901

*/

1902

extern void bcm2835_aux_spi_write(uint16_t data);

1903

1904

/*! Transfers any number of bytes to the AUX SPI slave.

1905

Asserts the CE2 pin during the transfer.

1906

\param[in] buf Buffer of bytes to send.

1907

\param[in] len Number of bytes in the tbuf buffer, and the number of bytes to send

1908

*/

1909

extern void bcm2835_aux_spi_writenb(const char *buf, uint32_t len);

1910

1911

/*! Transfers any number of bytes to and from the AUX SPI slave

1912

using bcm2835_aux_spi_transfernb.

1913

The returned data from the slave replaces the transmitted data in the buffer.

1914

\param[in,out] buf Buffer of bytes to send. Received bytes will replace the contents

1915

\param[in] len Number of bytes in the buffer, and the number of bytes to send/received

1916

\sa bcm2835_aux_spi_transfer()

1917

*/

1918

extern void bcm2835_aux_spi_transfern(char *buf, uint32_t len);

1919

1920

/*! Transfers any number of bytes to and from the AUX SPI slave.

1921

Asserts the CE2 pin during the transfer.

1922

Clocks the len 8 bit bytes out on MOSI, and simultaneously clocks in data from MISO.

1923

The data read read from the slave is placed into rbuf. rbuf must be at least len bytes long

1924

\param[in] tbuf Buffer of bytes to send.

1925

\param[out] rbuf Received bytes will by put in this buffer

1926

\param[in] len Number of bytes in the tbuf buffer, and the number of bytes to send/received

1927

*/

1928

extern void bcm2835_aux_spi_transfernb(const char *tbuf, char *rbuf, uint32_t len);

1929

1930

/*! Transfers one byte to and from the AUX SPI slave.

1931

Clocks the 8 bit value out on MOSI, and simultaneously clocks in data from MISO.

1932

Returns the read data byte from the slave.

1933

\param[in] value The 8 bit data byte to write to MOSI

1934

\return The 8 bit byte simultaneously read from MISO

1935

\sa bcm2835_aux_spi_transfern()

1936

*/

1937

extern uint8_t bcm2835_aux_spi_transfer(uint8_t value);

/*! @} */

/*! \defgroup i2c I2C access

1942

These functions let you use I2C (The Broadcom Serial Control bus with the Philips

1943

I2C bus/interface version 2.1 January 2000.) to interface with an external I2C device.

@{

*/

/*! Start I2C operations.

1948

Forces RPi I2C pins P1-03 (SDA) and P1-05 (SCL)

1949

to alternate function ALT0, which enables those pins for I2C interface.

1950

You should call bcm2835_i2c_end() when all I2C functions are complete to return the pins to

1951

their default functions

1952

\return 1 if successful, 0 otherwise (perhaps because you are not running as root)

1953

\sa bcm2835_i2c_end()

1954

*/

1955

extern int bcm2835_i2c_begin(void);

1956

1957

/*! End I2C operations.

1958

I2C pins P1-03 (SDA) and P1-05 (SCL)

1959

are returned to their default INPUT behaviour.

1960

*/

1961

extern void bcm2835_i2c_end(void);

1962

1963

/*! Sets the I2C slave address.

1964

\param[in] addr The I2C slave address.

1965

*/

1966

extern void bcm2835_i2c_setSlaveAddress(uint8_t addr);

1967

1968

/*! Sets the I2C clock divider and therefore the I2C clock speed.

1969

\param[in] divider The desired I2C clock divider, one of BCM2835_I2C_CLOCK_DIVIDER_*,

1970

see \ref bcm2835I2CClockDivider

1971

*/

1972

extern void bcm2835_i2c_setClockDivider(uint16_t divider);

1973

1974

/*! Sets the I2C clock divider by converting the baudrate parameter to

1975

the equivalent I2C clock divider. ( see \sa bcm2835_i2c_setClockDivider)

1976

For the I2C standard 100khz you would set baudrate to 100000

1977

The use of baudrate corresponds to its use in the I2C kernel device

1978

driver. (Of course, bcm2835 has nothing to do with the kernel driver)

1979

*/

1980

extern void bcm2835_i2c_set_baudrate(uint32_t baudrate);

1981

1982

/*! Transfers any number of bytes to the currently selected I2C slave.

1983

(as previously set by \sa bcm2835_i2c_setSlaveAddress)

1984

\param[in] buf Buffer of bytes to send.

1985

\param[in] len Number of bytes in the buf buffer, and the number of bytes to send.

1986

\return reason see \ref bcm2835I2CReasonCodes

1987

*/

1988

extern uint8_t bcm2835_i2c_write(const char * buf, uint32_t len);

1989

1990

/*! Transfers any number of bytes from the currently selected I2C slave.

1991

(as previously set by \sa bcm2835_i2c_setSlaveAddress)

1992

\param[in] buf Buffer of bytes to receive.

1993

\param[in] len Number of bytes in the buf buffer, and the number of bytes to received.

1994

\return reason see \ref bcm2835I2CReasonCodes

1995

*/

1996

extern uint8_t bcm2835_i2c_read(char* buf, uint32_t len);

1997

1998

/*! Allows reading from I2C slaves that require a repeated start (without any prior stop)

1999

to read after the required slave register has been set. For example, the popular

2000

MPL3115A2 pressure and temperature sensor. Note that your device must support or

2001

require this mode. If your device does not require this mode then the standard

2002

combined:

2003

\sa bcm2835_i2c_write

2004

\sa bcm2835_i2c_read

2005

are a better choice.

2006

Will read from the slave previously set by \sa bcm2835_i2c_setSlaveAddress

2007

\param[in] regaddr Buffer containing the slave register you wish to read from.

2008

\param[in] buf Buffer of bytes to receive.

2009

\param[in] len Number of bytes in the buf buffer, and the number of bytes to received.

2010

\return reason see \ref bcm2835I2CReasonCodes

2011

*/

2012

extern uint8_t bcm2835_i2c_read_register_rs(char* regaddr, char* buf, uint32_t len);

2013

2014

/*! Allows sending an arbitrary number of bytes to I2C slaves before issuing a repeated

2015

start (with no prior stop) and reading a response.

2016

Necessary for devices that require such behavior, such as the MLX90620.

2017

Will write to and read from the slave previously set by \sa bcm2835_i2c_setSlaveAddress

2018

\param[in] cmds Buffer containing the bytes to send before the repeated start condition.

2019

\param[in] cmds_len Number of bytes to send from cmds buffer

2020

\param[in] buf Buffer of bytes to receive.

2021

\param[in] buf_len Number of bytes to receive in the buf buffer.

2022

\return reason see \ref bcm2835I2CReasonCodes

2023

*/

2024

extern uint8_t bcm2835_i2c_write_read_rs(char* cmds, uint32_t cmds_len, char* buf, uint32_t buf_len);

/*! @} */

/*! \defgroup smi SMI bus support

2029

Allows access to SMI bus

2030

@{

2031

*/

2032

/*! Start SMI operations.

2033

Forces RPi SMI pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)

2034

to alternate function ALT1, which enables those pins for SMI interface.

2035

You should call bcm2835_smi_end() when all SMI functions are complete to return the pins to

2036

their default functions.

2037

Only address bits SA0 to SA3 are available as RPi uses GPIO0 (SA5) and GPIO1 (SA4) for I2C

2038

HAT identification EEPROM access

2039

\sa bcm2835_smi_end()

2040

\return 1 if successful, 0 otherwise (perhaps because you are not running as root)

2041

*/

2042

extern int bcm2835_smi_begin (void);

2043

2044

/*! End SMI operations.

2045

SMI pins P1-19 (MOSI), P1-21 (MISO), P1-23 (CLK), P1-24 (CE0) and P1-26 (CE1)

2046

are returned to their default INPUT behaviour.

2047

*/

2048

extern void bcm2835_smi_end (void);

2049

2050

/*! Setup SMI bus cycle timing parameters

2051

There are four SMI channels for read operation and four channels for write operation

2052

Cycles are expressed as multiple of 8ns

2053

Note that Pace cycles are not used (no effect on hardware) but they are required for

2054

configuration. It is recommended to set this value to 1 (and not 0) to have the

2055

smallest cycle in case the hardware would recognize it

2056

\param[in] smichannel SMI configuration slot to setup (0 to 3)

2057

\param[in] readchannel Set to 1 to configure the read channel (0 = configure write channel)

2058

\param[in] setupcycles Time between address assertion on bus and OE/WR signal assertion

2059

\param[in] strobecycles Duration of OE/WR signal assertion

2060

\param[in] holdcycles Time after OE/WR deassertion before address is deasserted

2061

\param[in] pacecycles Time before next SMI bus cycle

2062

*/

2063

extern void bcm2835_smi_set_timing(uint32_t smichannel, uint32_t readchannel,

2064

uint32_t setupcycles, uint32_t strobecycles,

2065

uint32_t holdcycles, uint32_t pacecycles);

2066

2067

/*! Transfers one byte to SMI bus.

2068

Uses polled transfer as described in BCM 2835 ARM Peripherals manual

2069

\param[in] timingslot SMI configuration slot to use (0 to 3)

2070

\param[in] data The data byte to write

2071

\param[in] address The address to write to

2072

\sa bcm2835_smi_writenb()

2073

*/

2074

extern void bcm2835_smi_write (uint32_t smichannel, uint8_t data, uint32_t address);

2075

2076

/*! Reads one byte from SMI bus.

2077

Uses polled transfer as described in BCM 2835 ARM Peripherals manual

2078

\param[in] smichannel SMI configuration slot to use (0 to 3)

2079

\param[in] address The address to read from

2080

\return value read from SMI bus

2081

\sa bcm2835_smi_readnb()

2082

*/

2083

extern uint32_t bcm2835_smi_read (uint32_t smichannel, uint32_t address);

/*! @} */

/*! \defgroup st System Timer access

2089

Allows access to and delays using the System Timer Counter.

@{

*/

/*! Read the System Timer Counter register.

2094

\return the value read from the System Timer Counter Lower 32 bits register

2095

*/

2096

extern uint64_t bcm2835_st_read(void);

2097

2098

/*! Delays for the specified number of microseconds with offset.

2099

\param[in] offset_micros Offset in microseconds

2100

\param[in] micros Delay in microseconds

2101

*/

2102

extern void bcm2835_st_delay(uint64_t offset_micros, uint64_t micros);

/*! @} */

/*! \defgroup pwm Pulse Width Modulation

2107

Allows control of 2 independent PWM channels. A limited subset of GPIO pins

2108

can be connected to one of these 2 channels, allowing PWM control of GPIO pins.

2109

You have to set the desired pin into a particular Alt Fun to PWM output. See the PWM

2110

documentation on the Main Page.

@{

*/

/*! Sets the PWM clock divisor,

2115

to control the basic PWM pulse widths.

2116

\param[in] divisor Divides the basic 19.2MHz PWM clock. You can use one of the common

2117

values BCM2835_PWM_CLOCK_DIVIDER_* in \ref bcm2835PWMClockDivider

2118

*/

2119

extern void bcm2835_pwm_set_clock(uint32_t divisor);

2120

2121

/*! Sets the mode of the given PWM channel,

2122

allowing you to control the PWM mode and enable/disable that channel

2123

\param[in] channel The PWM channel. 0 or 1.

2124

\param[in] markspace Set true if you want Mark-Space mode. 0 for Balanced mode.

2125

\param[in] enabled Set true to enable this channel and produce PWM pulses.

2126

*/

2127

extern void bcm2835_pwm_set_mode(uint8_t channel, uint8_t markspace, uint8_t enabled);

2128

2129

/*! Sets the maximum range of the PWM output.

2130

The data value can vary between 0 and this range to control PWM output

2131

\param[in] channel The PWM channel. 0 or 1.

2132

\param[in] range The maximum value permitted for DATA.

2133

*/

2134

extern void bcm2835_pwm_set_range(uint8_t channel, uint32_t range);

2135

2136

/*! Sets the PWM pulse ratio to emit to DATA/RANGE,

2137

where RANGE is set by bcm2835_pwm_set_range().

2138

\param[in] channel The PWM channel. 0 or 1.

2139

\param[in] data Controls the PWM output ratio as a fraction of the range.

2140

Can vary from 0 to RANGE.

2141

*/

2142

extern void bcm2835_pwm_set_data(uint8_t channel, uint32_t data);

/*! @} */

#ifdef __cplusplus

}

#endif

#endif /* BCM2835_H */

2150

2151

/*! @example blink.c

2152

Blinks RPi GPIO pin 11 on and off

2153

*/

2154

2155

/*! @example input.c

2156

Reads the state of an RPi input pin

2157

*/

2158

2159

/*! @example event.c

2160

Shows how to use event detection on an input pin

*/

/*! @example spi.c

Shows how to use SPI interface to transfer a byte to and from an SPI device

2165

*/

2166

2167

/*! @example spin.c

2168

Shows how to use SPI interface to transfer a number of bytes to and from an SPI device

*/

/*! @example pwm.c

Shows how to use PWM to control GPIO pins

*/

/*! @example i2c.c

Command line utility for executing i2c commands with the

2177

Broadcom bcm2835. Contributed by Shahrooz Shahparnia.

*/

/*! example gpio.c

Command line utility for executing gpio commands with the

2182

Broadcom bcm2835. Contributed by Shahrooz Shahparnia.

2183

*/

2184

2185

/*! example spimem_test.c

2186

Shows how to use the included little library (spiram.c and spiram.h)

2187

to read and write SPI RAM chips such as 23K256-I/P

2188

*/

pikeyd165 – Blame information for rev 1