OpenWrt – Blame information for rev 1
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1 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
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3 | * the Free Software Foundation; version 2 of the License |
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4 | * |
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5 | * This program is distributed in the hope that it will be useful, |
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6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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8 | * GNU General Public License for more details. |
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9 | * |
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10 | * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org> |
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11 | * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name> |
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12 | * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com> |
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13 | */ |
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14 | |||
15 | #include <linux/module.h> |
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16 | |||
17 | #include <asm/mach-ralink/ralink_regs.h> |
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18 | |||
19 | #include "mtk_eth_soc.h" |
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20 | #include "mdio_rt2880.h" |
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21 | |||
22 | #define RT2880_RESET_FE BIT(18) |
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23 | |||
24 | static void rt2880_init_data(struct fe_soc_data *data, |
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25 | struct net_device *netdev) |
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26 | { |
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27 | struct fe_priv *priv = netdev_priv(netdev); |
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28 | |||
29 | priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG | |
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30 | FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK; |
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31 | netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX; |
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32 | /* this should work according to the datasheet but actually does not*/ |
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33 | /* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */ |
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34 | } |
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35 | |||
36 | void rt2880_fe_reset(void) |
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37 | { |
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38 | fe_reset(RT2880_RESET_FE); |
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39 | } |
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40 | |||
41 | static int rt2880_fwd_config(struct fe_priv *priv) |
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42 | { |
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43 | int ret; |
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44 | |||
45 | ret = fe_set_clock_cycle(priv); |
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46 | if (ret) |
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47 | return ret; |
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48 | |||
49 | fe_fwd_config(priv); |
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50 | fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG); |
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51 | fe_csum_config(priv); |
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52 | |||
53 | return ret; |
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54 | } |
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55 | |||
56 | struct fe_soc_data rt2880_data = { |
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57 | .init_data = rt2880_init_data, |
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58 | .reset_fe = rt2880_fe_reset, |
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59 | .fwd_config = rt2880_fwd_config, |
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60 | .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS, |
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61 | .checksum_bit = RX_DMA_L4VALID, |
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62 | .rx_int = FE_RX_DONE_INT, |
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63 | .tx_int = FE_TX_DONE_INT, |
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64 | .status_int = FE_CNT_GDM_AF, |
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65 | .mdio_read = rt2880_mdio_read, |
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66 | .mdio_write = rt2880_mdio_write, |
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67 | .mdio_adjust_link = rt2880_mdio_link_adjust, |
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68 | .port_init = rt2880_port_init, |
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69 | }; |
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70 | |||
71 | const struct of_device_id of_fe_match[] = { |
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72 | { .compatible = "ralink,rt2880-eth", .data = &rt2880_data }, |
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73 | {}, |
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74 | }; |
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75 | |||
76 | MODULE_DEVICE_TABLE(of, of_fe_match); |