OpenWrt – Blame information for rev 1
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by |
||
3 | * the Free Software Foundation; version 2 of the License |
||
4 | * |
||
5 | * This program is distributed in the hope that it will be useful, |
||
6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
||
7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||
8 | * GNU General Public License for more details. |
||
9 | * |
||
10 | * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org> |
||
11 | * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name> |
||
12 | * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com> |
||
13 | */ |
||
14 | |||
15 | #include <linux/module.h> |
||
16 | #include <linux/kernel.h> |
||
17 | #include <linux/types.h> |
||
18 | #include <linux/platform_device.h> |
||
19 | #include <linux/of_device.h> |
||
20 | #include <linux/of_irq.h> |
||
21 | |||
22 | #include <ralink_regs.h> |
||
23 | |||
24 | #include "mtk_eth_soc.h" |
||
25 | #include "gsw_mt7620.h" |
||
26 | |||
27 | void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg) |
||
28 | { |
||
29 | iowrite32(val, gsw->base + reg); |
||
30 | } |
||
31 | |||
32 | u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg) |
||
33 | { |
||
34 | return ioread32(gsw->base + reg); |
||
35 | } |
||
36 | |||
37 | static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv) |
||
38 | { |
||
39 | struct fe_priv *priv = (struct fe_priv *)_priv; |
||
40 | struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv; |
||
41 | u32 status; |
||
42 | int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3); |
||
43 | |||
44 | status = mtk_switch_r32(gsw, GSW_REG_ISR); |
||
45 | if (status & PORT_IRQ_ST_CHG) |
||
46 | for (i = 0; i <= max; i++) { |
||
47 | u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)); |
||
48 | int link = status & 0x1; |
||
49 | |||
50 | if (link != priv->link[i]) |
||
51 | mt7620_print_link_state(priv, i, link, |
||
52 | (status >> 2) & 3, |
||
53 | (status & 0x2)); |
||
54 | |||
55 | priv->link[i] = link; |
||
56 | } |
||
57 | mt7620_handle_carrier(priv); |
||
58 | mtk_switch_w32(gsw, status, GSW_REG_ISR); |
||
59 | |||
60 | return IRQ_HANDLED; |
||
61 | } |
||
62 | |||
63 | static int mt7620_mdio_mode(struct device_node *eth_node) |
||
64 | { |
||
65 | struct device_node *phy_node, *mdiobus_node; |
||
66 | const __be32 *id; |
||
67 | int ret = 0; |
||
68 | |||
69 | mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus"); |
||
70 | |||
71 | if (mdiobus_node) { |
||
72 | if (of_property_read_bool(mdiobus_node, "mediatek,mdio-mode")) |
||
73 | ret = 1; |
||
74 | |||
75 | for_each_child_of_node(mdiobus_node, phy_node) { |
||
76 | id = of_get_property(phy_node, "reg", NULL); |
||
77 | if (id && (be32_to_cpu(*id) == 0x1f)) |
||
78 | ret = 1; |
||
79 | } |
||
80 | |||
81 | of_node_put(mdiobus_node); |
||
82 | } |
||
83 | |||
84 | return ret; |
||
85 | } |
||
86 | |||
87 | static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode) |
||
88 | { |
||
89 | u32 i; |
||
90 | u32 val; |
||
91 | u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1; |
||
92 | |||
93 | rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1); |
||
94 | mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR); |
||
95 | |||
96 | /* Enable MIB stats */ |
||
97 | mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN); |
||
98 | |||
99 | if (mdio_mode) { |
||
100 | u32 val; |
||
101 | |||
102 | /* turn off ephy and set phy base addr to 12 */ |
||
103 | mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) | |
||
104 | (0x1f << 24) | (0xc << 16), |
||
105 | GSW_REG_GPC1); |
||
106 | |||
107 | /* set MT7530 central align */ |
||
108 | val = mt7530_mdio_r32(gsw, 0x7830); |
||
109 | val &= ~BIT(0); |
||
110 | val |= BIT(1); |
||
111 | mt7530_mdio_w32(gsw, 0x7830, val); |
||
112 | |||
113 | val = mt7530_mdio_r32(gsw, 0x7a40); |
||
114 | val &= ~BIT(30); |
||
115 | mt7530_mdio_w32(gsw, 0x7a40, val); |
||
116 | |||
117 | mt7530_mdio_w32(gsw, 0x7a78, 0x855); |
||
118 | } else { |
||
119 | /* global page 4 */ |
||
120 | _mt7620_mii_write(gsw, 1, 31, 0x4000); |
||
121 | |||
122 | _mt7620_mii_write(gsw, 1, 17, 0x7444); |
||
123 | if (is_BGA) |
||
124 | _mt7620_mii_write(gsw, 1, 19, 0x0114); |
||
125 | else |
||
126 | _mt7620_mii_write(gsw, 1, 19, 0x0117); |
||
127 | |||
128 | _mt7620_mii_write(gsw, 1, 22, 0x10cf); |
||
129 | _mt7620_mii_write(gsw, 1, 25, 0x6212); |
||
130 | _mt7620_mii_write(gsw, 1, 26, 0x0777); |
||
131 | _mt7620_mii_write(gsw, 1, 29, 0x4000); |
||
132 | _mt7620_mii_write(gsw, 1, 28, 0xc077); |
||
133 | _mt7620_mii_write(gsw, 1, 24, 0x0000); |
||
134 | |||
135 | /* global page 3 */ |
||
136 | _mt7620_mii_write(gsw, 1, 31, 0x3000); |
||
137 | _mt7620_mii_write(gsw, 1, 17, 0x4838); |
||
138 | |||
139 | /* global page 2 */ |
||
140 | _mt7620_mii_write(gsw, 1, 31, 0x2000); |
||
141 | if (is_BGA) { |
||
142 | _mt7620_mii_write(gsw, 1, 21, 0x0515); |
||
143 | _mt7620_mii_write(gsw, 1, 22, 0x0053); |
||
144 | _mt7620_mii_write(gsw, 1, 23, 0x00bf); |
||
145 | _mt7620_mii_write(gsw, 1, 24, 0x0aaf); |
||
146 | _mt7620_mii_write(gsw, 1, 25, 0x0fad); |
||
147 | _mt7620_mii_write(gsw, 1, 26, 0x0fc1); |
||
148 | } else { |
||
149 | _mt7620_mii_write(gsw, 1, 21, 0x0517); |
||
150 | _mt7620_mii_write(gsw, 1, 22, 0x0fd2); |
||
151 | _mt7620_mii_write(gsw, 1, 23, 0x00bf); |
||
152 | _mt7620_mii_write(gsw, 1, 24, 0x0aab); |
||
153 | _mt7620_mii_write(gsw, 1, 25, 0x00ae); |
||
154 | _mt7620_mii_write(gsw, 1, 26, 0x0fff); |
||
155 | } |
||
156 | /* global page 1 */ |
||
157 | _mt7620_mii_write(gsw, 1, 31, 0x1000); |
||
158 | _mt7620_mii_write(gsw, 1, 17, 0xe7f8); |
||
159 | |||
160 | /* turn on all PHYs */ |
||
161 | for (i = 0; i <= 4; i++) { |
||
162 | val = _mt7620_mii_read(gsw, i, 0); |
||
163 | val &= ~BIT(11); |
||
164 | _mt7620_mii_write(gsw, i, 0, val); |
||
165 | } |
||
166 | } |
||
167 | |||
168 | /* global page 0 */ |
||
169 | _mt7620_mii_write(gsw, 1, 31, 0x8000); |
||
170 | _mt7620_mii_write(gsw, 0, 30, 0xa000); |
||
171 | _mt7620_mii_write(gsw, 1, 30, 0xa000); |
||
172 | _mt7620_mii_write(gsw, 2, 30, 0xa000); |
||
173 | _mt7620_mii_write(gsw, 3, 30, 0xa000); |
||
174 | |||
175 | _mt7620_mii_write(gsw, 0, 4, 0x05e1); |
||
176 | _mt7620_mii_write(gsw, 1, 4, 0x05e1); |
||
177 | _mt7620_mii_write(gsw, 2, 4, 0x05e1); |
||
178 | _mt7620_mii_write(gsw, 3, 4, 0x05e1); |
||
179 | |||
180 | /* global page 2 */ |
||
181 | _mt7620_mii_write(gsw, 1, 31, 0xa000); |
||
182 | _mt7620_mii_write(gsw, 0, 16, 0x1111); |
||
183 | _mt7620_mii_write(gsw, 1, 16, 0x1010); |
||
184 | _mt7620_mii_write(gsw, 2, 16, 0x1515); |
||
185 | _mt7620_mii_write(gsw, 3, 16, 0x0f0f); |
||
186 | |||
187 | /* CPU Port6 Force Link 1G, FC ON */ |
||
188 | mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6)); |
||
189 | |||
190 | /* Set Port 6 as CPU Port */ |
||
191 | mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010); |
||
192 | |||
193 | /* setup port 4 */ |
||
194 | if (gsw->port4 == PORT4_EPHY) { |
||
195 | u32 val = rt_sysc_r32(SYSC_REG_CFG1); |
||
196 | |||
197 | val |= 3 << 14; |
||
198 | rt_sysc_w32(val, SYSC_REG_CFG1); |
||
199 | _mt7620_mii_write(gsw, 4, 30, 0xa000); |
||
200 | _mt7620_mii_write(gsw, 4, 4, 0x05e1); |
||
201 | _mt7620_mii_write(gsw, 4, 16, 0x1313); |
||
202 | pr_info("gsw: setting port4 to ephy mode\n"); |
||
203 | } else if (!mdio_mode) { |
||
204 | u32 val = rt_sysc_r32(SYSC_REG_CFG1); |
||
205 | |||
206 | val &= ~(3 << 14); |
||
207 | rt_sysc_w32(val, SYSC_REG_CFG1); |
||
208 | pr_info("gsw: setting port4 to gmac mode\n"); |
||
209 | } |
||
210 | } |
||
211 | |||
212 | static const struct of_device_id mediatek_gsw_match[] = { |
||
213 | { .compatible = "mediatek,mt7620-gsw" }, |
||
214 | {}, |
||
215 | }; |
||
216 | MODULE_DEVICE_TABLE(of, mediatek_gsw_match); |
||
217 | |||
218 | int mtk_gsw_init(struct fe_priv *priv) |
||
219 | { |
||
220 | struct device_node *np = priv->switch_np; |
||
221 | struct platform_device *pdev = of_find_device_by_node(np); |
||
222 | struct mt7620_gsw *gsw; |
||
223 | |||
224 | if (!pdev) |
||
225 | return -ENODEV; |
||
226 | |||
227 | if (!of_device_is_compatible(np, mediatek_gsw_match->compatible)) |
||
228 | return -EINVAL; |
||
229 | |||
230 | gsw = platform_get_drvdata(pdev); |
||
231 | priv->soc->swpriv = gsw; |
||
232 | |||
233 | mt7620_hw_init(gsw, mt7620_mdio_mode(priv->dev->of_node)); |
||
234 | |||
235 | if (gsw->irq) { |
||
236 | request_irq(gsw->irq, gsw_interrupt_mt7620, 0, |
||
237 | "gsw", priv); |
||
238 | mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR); |
||
239 | } |
||
240 | |||
241 | return 0; |
||
242 | } |
||
243 | |||
244 | static int mt7620_gsw_probe(struct platform_device *pdev) |
||
245 | { |
||
246 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||
247 | const char *port4 = NULL; |
||
248 | struct mt7620_gsw *gsw; |
||
249 | struct device_node *np = pdev->dev.of_node; |
||
250 | |||
251 | gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL); |
||
252 | if (!gsw) |
||
253 | return -ENOMEM; |
||
254 | |||
255 | gsw->base = devm_ioremap_resource(&pdev->dev, res); |
||
256 | if (IS_ERR(gsw->base)) |
||
257 | return PTR_ERR(gsw->base); |
||
258 | |||
259 | gsw->dev = &pdev->dev; |
||
260 | |||
261 | of_property_read_string(np, "mediatek,port4", &port4); |
||
262 | if (port4 && !strcmp(port4, "ephy")) |
||
263 | gsw->port4 = PORT4_EPHY; |
||
264 | else if (port4 && !strcmp(port4, "gmac")) |
||
265 | gsw->port4 = PORT4_EXT; |
||
266 | else |
||
267 | gsw->port4 = PORT4_EPHY; |
||
268 | |||
269 | gsw->irq = platform_get_irq(pdev, 0); |
||
270 | |||
271 | platform_set_drvdata(pdev, gsw); |
||
272 | |||
273 | return 0; |
||
274 | } |
||
275 | |||
276 | static int mt7620_gsw_remove(struct platform_device *pdev) |
||
277 | { |
||
278 | platform_set_drvdata(pdev, NULL); |
||
279 | |||
280 | return 0; |
||
281 | } |
||
282 | |||
283 | static struct platform_driver gsw_driver = { |
||
284 | .probe = mt7620_gsw_probe, |
||
285 | .remove = mt7620_gsw_remove, |
||
286 | .driver = { |
||
287 | .name = "mt7620-gsw", |
||
288 | .owner = THIS_MODULE, |
||
289 | .of_match_table = mediatek_gsw_match, |
||
290 | }, |
||
291 | }; |
||
292 | |||
293 | module_platform_driver(gsw_driver); |
||
294 | |||
295 | MODULE_LICENSE("GPL"); |
||
296 | MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); |
||
297 | MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC"); |
||
298 | MODULE_VERSION(MTK_FE_DRV_VERSION); |