OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 004eb24e939b5b31f828333f37fb5cb2a877d6f2 Mon Sep 17 00:00:00 2001 |
2 | From: Kristian Evensen <kristian.evensen@gmail.com> |
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3 | Date: Sun, 17 Jun 2018 14:41:47 +0200 |
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4 | Subject: [PATCH] arm: dts: Add Unielec U7623 DTS |
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5 | |||
6 | --- |
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7 | arch/arm/boot/dts/Makefile | 1 + |
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8 | .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts | 18 + |
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9 | .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi | 366 +++++++++++++++++++++ |
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10 | 3 files changed, 385 insertions(+) |
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11 | create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts |
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12 | create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi |
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13 | |||
14 | --- a/arch/arm/boot/dts/Makefile |
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15 | +++ b/arch/arm/boot/dts/Makefile |
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16 | @@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ |
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17 | mt6589-aquaris5.dtb \ |
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18 | mt6592-evb.dtb \ |
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19 | mt7623a-rfb-emmc.dtb \ |
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20 | + mt7623a-unielec-u7623-02-emmc-512M.dtb \ |
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21 | mt7623n-rfb-nand.dtb \ |
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22 | mt7623n-bananapi-bpi-r2.dtb \ |
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23 | mt8127-moose.dtb \ |
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24 | --- /dev/null |
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25 | +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts |
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26 | @@ -0,0 +1,18 @@ |
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27 | +/* |
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28 | + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com> |
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29 | + * |
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30 | + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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31 | + */ |
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32 | + |
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33 | +/dts-v1/; |
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34 | +#include "mt7623a-unielec-u7623-02-emmc.dtsi" |
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35 | + |
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36 | +/ { |
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37 | + model = "UniElec U7623-02 eMMC (512M RAM)"; |
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38 | + compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623"; |
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39 | + |
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40 | + memory@80000000 { |
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41 | + device_type = "memory"; |
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42 | + reg = <0 0x80000000 0 0x20000000>; |
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43 | + }; |
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44 | +}; |
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45 | --- /dev/null |
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46 | +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi |
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47 | @@ -0,0 +1,366 @@ |
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48 | +/* |
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49 | + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com> |
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50 | + * |
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51 | + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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52 | + */ |
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53 | + |
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54 | +#include <dt-bindings/input/input.h> |
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55 | +#include "mt7623.dtsi" |
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56 | +#include "mt6323.dtsi" |
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57 | + |
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58 | +/ { |
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59 | + compatible = "unielec,u7623-02-emmc", "mediatek,mt7623"; |
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60 | + |
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61 | + aliases { |
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62 | + serial2 = &uart2; |
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63 | + }; |
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64 | + |
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65 | + chosen { |
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66 | + bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs"; |
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67 | + stdout-path = "serial2:115200n8"; |
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68 | + }; |
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69 | + |
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70 | + cpus { |
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71 | + cpu@0 { |
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72 | + proc-supply = <&mt6323_vproc_reg>; |
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73 | + }; |
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74 | + |
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75 | + cpu@1 { |
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76 | + proc-supply = <&mt6323_vproc_reg>; |
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77 | + }; |
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78 | + |
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79 | + cpu@2 { |
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80 | + proc-supply = <&mt6323_vproc_reg>; |
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81 | + }; |
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82 | + |
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83 | + cpu@3 { |
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84 | + proc-supply = <&mt6323_vproc_reg>; |
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85 | + }; |
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86 | + }; |
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87 | + |
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88 | + reg_1p8v: regulator-1p8v { |
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89 | + compatible = "regulator-fixed"; |
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90 | + regulator-name = "fixed-1.8V"; |
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91 | + regulator-min-microvolt = <1800000>; |
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92 | + regulator-max-microvolt = <1800000>; |
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93 | + regulator-boot-on; |
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94 | + regulator-always-on; |
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95 | + }; |
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96 | + |
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97 | + reg_3p3v: regulator-3p3v { |
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98 | + compatible = "regulator-fixed"; |
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99 | + regulator-name = "fixed-3.3V"; |
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100 | + regulator-min-microvolt = <3300000>; |
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101 | + regulator-max-microvolt = <3300000>; |
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102 | + regulator-boot-on; |
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103 | + regulator-always-on; |
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104 | + }; |
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105 | + |
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106 | + reg_5v: regulator-5v { |
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107 | + compatible = "regulator-fixed"; |
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108 | + regulator-name = "fixed-5V"; |
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109 | + regulator-min-microvolt = <5000000>; |
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110 | + regulator-max-microvolt = <5000000>; |
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111 | + regulator-boot-on; |
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112 | + regulator-always-on; |
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113 | + }; |
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114 | + |
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115 | + gpio-keys { |
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116 | + compatible = "gpio-keys"; |
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117 | + pinctrl-names = "default"; |
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118 | + pinctrl-0 = <&key_pins_a>; |
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119 | + |
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120 | + factory { |
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121 | + label = "factory"; |
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122 | + linux,code = <KEY_RESTART>; |
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123 | + gpios = <&pio 256 GPIO_ACTIVE_LOW>; |
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124 | + }; |
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125 | + }; |
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126 | + |
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127 | + leds { |
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128 | + compatible = "gpio-leds"; |
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129 | + pinctrl-names = "default"; |
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130 | + pinctrl-0 = <&led_pins_unielec>; |
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131 | + |
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132 | + led3 { |
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133 | + label = "u7623-01:green:led3"; |
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134 | + gpios = <&pio 14 GPIO_ACTIVE_LOW>; |
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135 | + default-state = "off"; |
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136 | + }; |
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137 | + |
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138 | + led4 { |
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139 | + label = "u7623-01:green:led4"; |
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140 | + gpios = <&pio 15 GPIO_ACTIVE_LOW>; |
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141 | + default-state = "off"; |
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142 | + }; |
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143 | + }; |
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144 | + |
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145 | + mt7530: switch@0 { |
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146 | + compatible = "mediatek,mt7530"; |
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147 | + #address-cells = <1>; |
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148 | + #size-cells = <0>; |
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149 | + }; |
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150 | +}; |
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151 | + |
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152 | +&crypto { |
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153 | + status = "okay"; |
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154 | +}; |
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155 | + |
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156 | +ð { |
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157 | + status = "okay"; |
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158 | + |
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159 | + gmac0: mac@0 { |
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160 | + compatible = "mediatek,eth-mac"; |
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161 | + reg = <0>; |
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162 | + phy-mode = "trgmii"; |
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163 | + |
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164 | + fixed-link { |
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165 | + speed = <1000>; |
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166 | + full-duplex; |
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167 | + pause; |
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168 | + }; |
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169 | + }; |
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170 | + |
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171 | + mdio: mdio-bus { |
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172 | + #address-cells = <1>; |
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173 | + #size-cells = <0>; |
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174 | + phy5: ethernet-phy@5 { |
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175 | + reg = <5>; |
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176 | + phy-mode = "rgmii-rxid"; |
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177 | + }; |
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178 | + }; |
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179 | +}; |
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180 | + |
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181 | +&mt7530 { |
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182 | + compatible = "mediatek,mt7530"; |
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183 | + #address-cells = <1>; |
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184 | + #size-cells = <0>; |
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185 | + reg = <0>; |
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186 | + pinctrl-names = "default"; |
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187 | + mediatek,mcm; |
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188 | + resets = <ðsys 2>; |
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189 | + reset-names = "mcm"; |
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190 | + core-supply = <&mt6323_vpa_reg>; |
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191 | + io-supply = <&mt6323_vemc3v3_reg>; |
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192 | + |
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193 | + dsa,mii-bus = <&mdio>; |
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194 | + |
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195 | + ports { |
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196 | + #address-cells = <1>; |
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197 | + #size-cells = <0>; |
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198 | + reg = <0>; |
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199 | + |
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200 | + port@0 { |
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201 | + reg = <0>; |
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202 | + label = "lan0"; |
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203 | + cpu = <&cpu_port0>; |
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204 | + }; |
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205 | + |
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206 | + port@1 { |
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207 | + reg = <1>; |
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208 | + label = "lan1"; |
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209 | + cpu = <&cpu_port0>; |
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210 | + }; |
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211 | + |
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212 | + port@2 { |
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213 | + reg = <2>; |
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214 | + label = "lan2"; |
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215 | + cpu = <&cpu_port0>; |
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216 | + }; |
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217 | + |
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218 | + port@3 { |
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219 | + reg = <3>; |
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220 | + label = "lan3"; |
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221 | + cpu = <&cpu_port0>; |
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222 | + }; |
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223 | + |
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224 | + port@4 { |
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225 | + reg = <4>; |
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226 | + label = "wan"; |
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227 | + cpu = <&cpu_port0>; |
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228 | + }; |
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229 | + |
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230 | + cpu_port0: port@6 { |
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231 | + reg = <6>; |
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232 | + label = "cpu"; |
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233 | + ethernet = <&gmac0>; |
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234 | + phy-mode = "trgmii"; |
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235 | + |
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236 | + fixed-link { |
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237 | + speed = <1000>; |
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238 | + full-duplex; |
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239 | + }; |
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240 | + }; |
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241 | + }; |
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242 | +}; |
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243 | + |
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244 | +&mmc0 { |
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245 | + pinctrl-names = "default", "state_uhs"; |
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246 | + pinctrl-0 = <&mmc0_pins_default>; |
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247 | + pinctrl-1 = <&mmc0_pins_uhs>; |
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248 | + status = "okay"; |
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249 | + bus-width = <8>; |
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250 | + max-frequency = <50000000>; |
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251 | + cap-mmc-highspeed; |
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252 | + vmmc-supply = <®_3p3v>; |
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253 | + vqmmc-supply = <®_1p8v>; |
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254 | + non-removable; |
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255 | +}; |
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256 | + |
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257 | +&pio { |
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258 | + key_pins_a: keys-alt { |
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259 | + pins-keys { |
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260 | + pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>, |
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261 | + <MT7623_PIN_257_GPIO257_FUNC_GPIO257>; |
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262 | + input-enable; |
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263 | + }; |
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264 | + }; |
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265 | + |
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266 | + led_pins_unielec: leds-unielec { |
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267 | + pins-leds { |
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268 | + pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>, |
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269 | + <MT7623_PIN_15_GPIO15_FUNC_GPIO15>; |
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270 | + }; |
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271 | + }; |
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272 | + |
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273 | + mmc0_pins_default: mmc0default { |
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274 | + pins_cmd_dat { |
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275 | + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
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276 | + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
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277 | + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
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278 | + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
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279 | + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
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280 | + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
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281 | + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
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282 | + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
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283 | + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
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284 | + input-enable; |
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285 | + bias-pull-up; |
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286 | + }; |
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287 | + |
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288 | + pins_clk { |
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289 | + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
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290 | + bias-pull-down; |
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291 | + }; |
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292 | + |
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293 | + pins_rst { |
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294 | + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
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295 | + bias-pull-up; |
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296 | + }; |
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297 | + }; |
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298 | + |
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299 | + mmc0_pins_uhs: mmc0 { |
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300 | + pins_cmd_dat { |
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301 | + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>, |
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302 | + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>, |
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303 | + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>, |
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304 | + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>, |
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305 | + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>, |
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306 | + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>, |
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307 | + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>, |
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308 | + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, |
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309 | + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; |
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310 | + input-enable; |
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311 | + drive-strength = <MTK_DRIVE_2mA>; |
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312 | + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
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313 | + }; |
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314 | + |
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315 | + pins_clk { |
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316 | + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; |
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317 | + drive-strength = <MTK_DRIVE_2mA>; |
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318 | + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; |
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319 | + }; |
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320 | + |
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321 | + pins_rst { |
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322 | + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>; |
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323 | + bias-pull-up; |
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324 | + }; |
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325 | + }; |
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326 | + |
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327 | + pwm_pins_a: pwm@0 { |
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328 | + pins_pwm { |
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329 | + pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, |
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330 | + <MT7623_PIN_204_PWM1_FUNC_PWM1>, |
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331 | + <MT7623_PIN_205_PWM2_FUNC_PWM2>, |
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332 | + <MT7623_PIN_206_PWM3_FUNC_PWM3>, |
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333 | + <MT7623_PIN_207_PWM4_FUNC_PWM4>; |
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334 | + }; |
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335 | + }; |
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336 | + |
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337 | + uart2_pins_b: uart@2 { |
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338 | + pins_dat { |
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339 | + pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>, |
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340 | + <MT7623_PIN_201_UTXD2_FUNC_UTXD2>; |
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341 | + }; |
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342 | + }; |
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343 | + |
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344 | + pcie_default: pcie_pin_default { |
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345 | + pins_cmd_dat { |
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346 | + pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>, |
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347 | + <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>; |
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348 | + bias-disable; |
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349 | + }; |
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350 | + }; |
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351 | +}; |
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352 | + |
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353 | +&pwm { |
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354 | + pinctrl-names = "default"; |
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355 | + pinctrl-0 = <&pwm_pins_a>; |
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356 | + status = "okay"; |
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357 | +}; |
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358 | + |
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359 | +&pwrap { |
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360 | + mt6323 { |
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361 | + mt6323led: led { |
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362 | + compatible = "mediatek,mt6323-led"; |
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363 | + #address-cells = <1>; |
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364 | + #size-cells = <0>; |
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365 | + |
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366 | + led@0 { |
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367 | + reg = <0>; |
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368 | + label = "led0"; |
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369 | + default-state = "off"; |
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370 | + }; |
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371 | + }; |
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372 | + }; |
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373 | +}; |
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374 | + |
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375 | +&uart2 { |
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376 | + pinctrl-names = "default"; |
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377 | + pinctrl-0 = <&uart2_pins_b>; |
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378 | + status = "okay"; |
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379 | +}; |
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380 | + |
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381 | +&usb1 { |
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382 | + vusb33-supply = <®_3p3v>; |
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383 | + vbus-supply = <®_3p3v>; |
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384 | + status = "okay"; |
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385 | +}; |
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386 | + |
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387 | +&u3phy1 { |
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388 | + status = "okay"; |
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389 | +}; |
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390 | + |
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391 | +&u3phy2 { |
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392 | + status = "okay"; |
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393 | + mediatek,phy-switch = <&hifsys>; |
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394 | +}; |
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395 | + |
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396 | +&pcie { |
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397 | + pinctrl-names = "default"; |
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398 | + pinctrl-0 = <&pcie_default>; |
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399 | + status = "okay"; |
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400 | + |
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401 | + pcie@1,0 { |
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402 | + status = "okay"; |
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403 | + }; |
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404 | + |
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405 | + pcie@2,0 { |
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406 | + status = "okay"; |
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407 | + }; |
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408 | +}; |
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409 | + |
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410 | +&pcie1_phy { |
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411 | + status = "okay"; |
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412 | +}; |
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413 | + |