OpenWrt – Blame information for rev 1
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1 | office | 1 | From 78e92290c8c9511d0d540dfd0450e64169f08c20 Mon Sep 17 00:00:00 2001 |
2 | From: Sean Wang <sean.wang@mediatek.com> |
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3 | Date: Mon, 5 Feb 2018 22:44:44 +0800 |
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4 | Subject: [PATCH 213/224] arm64: dts: mt7622: add PMIC MT6380 related nodes |
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5 | |||
6 | Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380 |
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7 | regulator nodes in an alone file to allow similar boards using MT6380 |
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8 | able to resue the configuration. |
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9 | |||
10 | Signed-off-by: Sean Wang <sean.wang@mediatek.com> |
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11 | Cc: Mark Brown <broonie@kernel.org> |
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12 | Cc: Matthias Brugger <matthias.bgg@gmail.com> |
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13 | Cc: Philippe Ombredanne <pombredanne@nexb.com> |
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14 | Acked-by: Philippe Ombredanne <pombredanne@nexb.com> |
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15 | --- |
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16 | arch/arm64/boot/dts/mediatek/mt6380.dtsi | 86 ++++++++++++++++++++++++++++ |
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17 | arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++ |
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18 | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++ |
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19 | 3 files changed, 106 insertions(+) |
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20 | create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi |
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21 | |||
22 | --- /dev/null |
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23 | +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi |
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24 | @@ -0,0 +1,86 @@ |
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25 | +// SPDX-License-Identifier: GPL-2.0 |
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26 | +/* |
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27 | + * dts file for MediaTek MT6380 regulator |
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28 | + * |
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29 | + * Copyright (c) 2018 MediaTek Inc. |
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30 | + * Author: Chenglin Xu <chenglin.xu@mediatek.com> |
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31 | + * Sean Wang <sean.wang@mediatek.com> |
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32 | + */ |
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33 | + |
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34 | +&pwrap { |
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35 | + regulators { |
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36 | + compatible = "mediatek,mt6380-regulator"; |
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37 | + |
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38 | + mt6380_vcpu_reg: buck-vcore1 { |
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39 | + regulator-name = "vcore1"; |
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40 | + regulator-min-microvolt = < 600000>; |
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41 | + regulator-max-microvolt = <1393750>; |
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42 | + regulator-ramp-delay = <6250>; |
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43 | + regulator-always-on; |
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44 | + regulator-boot-on; |
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45 | + }; |
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46 | + |
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47 | + mt6380_vcore_reg: buck-vcore { |
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48 | + regulator-name = "vcore"; |
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49 | + regulator-min-microvolt = <600000>; |
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50 | + regulator-max-microvolt = <1393750>; |
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51 | + regulator-ramp-delay = <6250>; |
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52 | + regulator-always-on; |
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53 | + regulator-boot-on; |
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54 | + }; |
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55 | + |
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56 | + mt6380_vrf_reg: buck-vrf { |
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57 | + regulator-name = "vrf"; |
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58 | + regulator-min-microvolt = <1200000>; |
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59 | + regulator-max-microvolt = <1575000>; |
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60 | + regulator-ramp-delay = <0>; |
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61 | + regulator-always-on; |
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62 | + regulator-boot-on; |
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63 | + }; |
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64 | + |
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65 | + mt6380_vm_reg: ldo-vm { |
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66 | + regulator-name = "vm"; |
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67 | + regulator-min-microvolt = <1050000>; |
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68 | + regulator-max-microvolt = <1400000>; |
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69 | + regulator-ramp-delay = <0>; |
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70 | + regulator-always-on; |
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71 | + regulator-boot-on; |
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72 | + }; |
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73 | + |
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74 | + mt6380_va_reg: ldo-va { |
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75 | + regulator-name = "va"; |
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76 | + regulator-min-microvolt = <2200000>; |
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77 | + regulator-max-microvolt = <3300000>; |
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78 | + regulator-ramp-delay = <0>; |
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79 | + regulator-always-on; |
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80 | + regulator-boot-on; |
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81 | + }; |
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82 | + |
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83 | + mt6380_vphy_reg: ldo-vphy { |
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84 | + regulator-name = "vphy"; |
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85 | + regulator-min-microvolt = <1800000>; |
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86 | + regulator-max-microvolt = <1800000>; |
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87 | + regulator-ramp-delay = <0>; |
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88 | + regulator-always-on; |
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89 | + regulator-boot-on; |
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90 | + }; |
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91 | + |
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92 | + mt6380_vddr_reg: ldo-vddr { |
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93 | + regulator-name = "vddr"; |
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94 | + regulator-min-microvolt = <1240000>; |
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95 | + regulator-max-microvolt = <1840000>; |
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96 | + regulator-ramp-delay = <0>; |
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97 | + regulator-always-on; |
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98 | + regulator-boot-on; |
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99 | + }; |
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100 | + |
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101 | + mt6380_vt_reg: ldo-vt { |
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102 | + regulator-name = "vt"; |
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103 | + regulator-min-microvolt = <2200000>; |
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104 | + regulator-max-microvolt = <3300000>; |
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105 | + regulator-ramp-delay = <0>; |
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106 | + regulator-always-on; |
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107 | + regulator-boot-on; |
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108 | + }; |
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109 | + }; |
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110 | +}; |
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111 | --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |
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112 | +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |
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113 | @@ -10,6 +10,7 @@ |
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114 | #include <dt-bindings/input/input.h> |
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115 | |||
116 | #include "mt7622.dtsi" |
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117 | +#include "mt6380.dtsi" |
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118 | |||
119 | / { |
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120 | model = "MediaTek MT7622 RFB1 board"; |
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121 | @@ -222,6 +223,13 @@ |
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122 | }; |
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123 | }; |
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124 | |||
125 | +&pwrap { |
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126 | + pinctrl-names = "default"; |
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127 | + pinctrl-0 = <&pmic_bus_pins>; |
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128 | + |
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129 | + status = "okay"; |
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130 | +}; |
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131 | + |
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132 | &uart0 { |
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133 | status = "okay"; |
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134 | }; |
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135 | --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
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136 | +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
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137 | @@ -102,6 +102,18 @@ |
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138 | #reset-cells = <1>; |
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139 | }; |
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140 | |||
141 | + pwrap: pwrap@10001000 { |
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142 | + compatible = "mediatek,mt7622-pwrap"; |
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143 | + reg = <0 0x10001000 0 0x250>; |
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144 | + reg-names = "pwrap"; |
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145 | + clocks = <&infracfg CLK_INFRA_PMIC_PD>,<&pwrap_clk>; |
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146 | + clock-names = "spi","wrap"; |
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147 | + resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; |
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148 | + reset-names = "pwrap"; |
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149 | + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
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150 | + status = "disabled"; |
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151 | + }; |
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152 | + |
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153 | pericfg: pericfg@10002000 { |
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154 | compatible = "mediatek,mt7622-pericfg", |
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155 | "syscon"; |