OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <blogic@openwrt.org> |
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3 | Date: Thu, 7 Aug 2014 18:26:42 +0200 |
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4 | Subject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master |
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5 | |||
6 | This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. |
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7 | |||
8 | Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> |
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9 | Signed-off-by: John Crispin <blogic@openwrt.org> |
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10 | --- |
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11 | drivers/i2c/busses/Kconfig | 10 + |
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12 | drivers/i2c/busses/Makefile | 1 + |
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13 | drivers/i2c/busses/i2c-lantiq.c | 747 +++++++++++++++++++++++++++++++++++++++ |
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14 | drivers/i2c/busses/i2c-lantiq.h | 234 ++++++++++++ |
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15 | 4 files changed, 992 insertions(+) |
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16 | create mode 100644 drivers/i2c/busses/i2c-lantiq.c |
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17 | create mode 100644 drivers/i2c/busses/i2c-lantiq.h |
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18 | |||
19 | --- a/drivers/i2c/busses/Kconfig |
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20 | +++ b/drivers/i2c/busses/Kconfig |
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21 | @@ -696,6 +696,16 @@ config I2C_MESON |
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22 | If you say yes to this option, support will be included for the |
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23 | I2C interface on the Amlogic Meson family of SoCs. |
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24 | |||
25 | +config I2C_LANTIQ |
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26 | + tristate "Lantiq I2C interface" |
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27 | + depends on LANTIQ && SOC_FALCON |
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28 | + help |
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29 | + If you say yes to this option, support will be included for the |
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30 | + Lantiq I2C core. |
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31 | + |
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32 | + This driver can also be built as a module. If so, the module |
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33 | + will be called i2c-lantiq. |
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34 | + |
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35 | config I2C_MPC |
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36 | tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" |
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37 | depends on PPC |
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38 | --- a/drivers/i2c/busses/Makefile |
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39 | +++ b/drivers/i2c/busses/Makefile |
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40 | @@ -68,6 +68,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l |
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41 | obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o |
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42 | obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o |
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43 | obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o |
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44 | +obj-$(CONFIG_I2C_LANTIQ) += i2c-lantiq.o |
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45 | obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o |
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46 | obj-$(CONFIG_I2C_MESON) += i2c-meson.o |
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47 | obj-$(CONFIG_I2C_MPC) += i2c-mpc.o |
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48 | --- /dev/null |
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49 | +++ b/drivers/i2c/busses/i2c-lantiq.c |
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50 | @@ -0,0 +1,747 @@ |
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51 | + |
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52 | +/* |
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53 | + * Lantiq I2C bus adapter |
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54 | + * |
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55 | + * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 |
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56 | + * |
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57 | + * This program is free software; you can redistribute it and/or modify |
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58 | + * it under the terms of the GNU General Public License as published by |
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59 | + * the Free Software Foundation; either version 2 of the License, or |
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60 | + * (at your option) any later version. |
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61 | + * |
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62 | + * This program is distributed in the hope that it will be useful, |
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63 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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64 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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65 | + * GNU General Public License for more details. |
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66 | + * |
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67 | + * You should have received a copy of the GNU General Public License |
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68 | + * along with this program; if not, write to the Free Software |
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69 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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70 | + * |
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71 | + * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com> |
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72 | + */ |
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73 | + |
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74 | +#include <linux/kernel.h> |
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75 | +#include <linux/module.h> |
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76 | +#include <linux/delay.h> |
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77 | +#include <linux/slab.h> /* for kzalloc, kfree */ |
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78 | +#include <linux/i2c.h> |
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79 | +#include <linux/errno.h> |
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80 | +#include <linux/completion.h> |
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81 | +#include <linux/interrupt.h> |
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82 | +#include <linux/platform_device.h> |
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83 | +#include <linux/io.h> |
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84 | +#include <linux/of_irq.h> |
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85 | + |
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86 | +#include <lantiq_soc.h> |
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87 | +#include "i2c-lantiq.h" |
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88 | + |
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89 | +/* |
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90 | + * CURRENT ISSUES: |
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91 | + * - no high speed support |
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92 | + * - ten bit mode is not tested (no slave devices) |
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93 | + */ |
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94 | + |
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95 | +/* access macros */ |
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96 | +#define i2c_r32(reg) \ |
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97 | + __raw_readl(&(priv->membase)->reg) |
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98 | +#define i2c_w32(val, reg) \ |
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99 | + __raw_writel(val, &(priv->membase)->reg) |
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100 | +#define i2c_w32_mask(clear, set, reg) \ |
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101 | + i2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg) |
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102 | + |
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103 | +#define DRV_NAME "i2c-lantiq" |
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104 | +#define DRV_VERSION "1.00" |
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105 | + |
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106 | +#define LTQ_I2C_BUSY_TIMEOUT 20 /* ms */ |
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107 | + |
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108 | +#ifdef DEBUG |
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109 | +#define LTQ_I2C_XFER_TIMEOUT (25*HZ) |
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110 | +#else |
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111 | +#define LTQ_I2C_XFER_TIMEOUT HZ |
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112 | +#endif |
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113 | + |
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114 | +#define LTQ_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ |
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115 | + I2C_IMSC_I2C_ERR_INT_EN) |
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116 | + |
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117 | +#define LTQ_I2C_ARB_LOST (1 << 0) |
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118 | +#define LTQ_I2C_NACK (1 << 1) |
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119 | +#define LTQ_I2C_RX_UFL (1 << 2) |
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120 | +#define LTQ_I2C_RX_OFL (1 << 3) |
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121 | +#define LTQ_I2C_TX_UFL (1 << 4) |
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122 | +#define LTQ_I2C_TX_OFL (1 << 5) |
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123 | + |
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124 | +struct ltq_i2c { |
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125 | + struct mutex mutex; |
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126 | + |
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127 | + |
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128 | + /* active clock settings */ |
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129 | + unsigned int input_clock; /* clock input for i2c hardware block */ |
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130 | + unsigned int i2c_clock; /* approximated bus clock in kHz */ |
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131 | + |
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132 | + struct clk *clk_gate; |
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133 | + struct clk *clk_input; |
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134 | + |
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135 | + |
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136 | + /* resources (memory and interrupts) */ |
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137 | + int irq_lb; /* last burst irq */ |
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138 | + |
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139 | + struct lantiq_reg_i2c __iomem *membase; /* base of mapped registers */ |
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140 | + |
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141 | + struct i2c_adapter adap; |
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142 | + struct device *dev; |
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143 | + |
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144 | + struct completion cmd_complete; |
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145 | + |
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146 | + |
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147 | + /* message transfer data */ |
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148 | + struct i2c_msg *current_msg; /* current message */ |
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149 | + int msgs_num; /* number of messages to handle */ |
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150 | + u8 *msg_buf; /* current buffer */ |
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151 | + u32 msg_buf_len; /* remaining length of current buffer */ |
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152 | + int msg_err; /* error status of the current transfer */ |
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153 | + |
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154 | + |
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155 | + /* master status codes */ |
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156 | + enum { |
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157 | + STATUS_IDLE, |
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158 | + STATUS_ADDR, /* address phase */ |
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159 | + STATUS_WRITE, |
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160 | + STATUS_READ, |
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161 | + STATUS_READ_END, |
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162 | + STATUS_STOP |
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163 | + } status; |
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164 | +}; |
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165 | + |
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166 | +static irqreturn_t ltq_i2c_isr(int irq, void *dev_id); |
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167 | + |
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168 | +static inline void enable_burst_irq(struct ltq_i2c *priv) |
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169 | +{ |
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170 | + i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); |
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171 | +} |
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172 | +static inline void disable_burst_irq(struct ltq_i2c *priv) |
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173 | +{ |
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174 | + i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); |
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175 | +} |
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176 | + |
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177 | +static void prepare_msg_send_addr(struct ltq_i2c *priv) |
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178 | +{ |
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179 | + struct i2c_msg *msg = priv->current_msg; |
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180 | + int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ |
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181 | + u16 addr = msg->addr; |
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182 | + |
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183 | + /* new i2c_msg */ |
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184 | + priv->msg_buf = msg->buf; |
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185 | + priv->msg_buf_len = msg->len; |
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186 | + if (rd) |
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187 | + priv->status = STATUS_READ; |
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188 | + else |
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189 | + priv->status = STATUS_WRITE; |
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190 | + |
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191 | + /* send slave address */ |
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192 | + if (msg->flags & I2C_M_TEN) { |
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193 | + i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); |
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194 | + i2c_w32(addr & 0xff, txd); |
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195 | + } else { |
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196 | + i2c_w32((addr & 0x7f) << 1 | rd, txd); |
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197 | + } |
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198 | +} |
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199 | + |
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200 | +static void ltq_i2c_set_tx_len(struct ltq_i2c *priv) |
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201 | +{ |
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202 | + struct i2c_msg *msg = priv->current_msg; |
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203 | + int len = (msg->flags & I2C_M_TEN) ? 2 : 1; |
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204 | + |
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205 | + pr_debug("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? 'R' : 'T'); |
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206 | + |
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207 | + priv->status = STATUS_ADDR; |
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208 | + |
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209 | + if (!(msg->flags & I2C_M_RD)) |
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210 | + len += msg->len; |
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211 | + else |
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212 | + /* set maximum received packet size (before rx int!) */ |
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213 | + i2c_w32(msg->len, mrps_ctrl); |
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214 | + i2c_w32(len, tps_ctrl); |
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215 | + enable_burst_irq(priv); |
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216 | +} |
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217 | + |
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218 | +static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap) |
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219 | +{ |
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220 | + struct ltq_i2c *priv = i2c_get_adapdata(adap); |
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221 | + unsigned int input_clock = clk_get_rate(priv->clk_input); |
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222 | + u32 dec, inc = 1; |
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223 | + |
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224 | + /* clock changed? */ |
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225 | + if (priv->input_clock == input_clock) |
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226 | + return 0; |
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227 | + |
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228 | + /* |
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229 | + * this formula is only an approximation, found by the recommended |
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230 | + * values in the "I2C Architecture Specification 1.7.1" |
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231 | + */ |
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232 | + dec = input_clock / (priv->i2c_clock * 2); |
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233 | + if (dec <= 6) |
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234 | + return -ENXIO; |
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235 | + |
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236 | + i2c_w32(0, fdiv_high_cfg); |
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237 | + i2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) | |
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238 | + (dec << I2C_FDIV_CFG_DEC_OFFSET), |
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239 | + fdiv_cfg); |
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240 | + |
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241 | + dev_info(priv->dev, "setup clocks (in %d kHz, bus %d kHz, dec=%d)\n", |
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242 | + input_clock, priv->i2c_clock, dec); |
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243 | + |
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244 | + priv->input_clock = input_clock; |
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245 | + return 0; |
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246 | +} |
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247 | + |
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248 | +static int ltq_i2c_hw_init(struct i2c_adapter *adap) |
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249 | +{ |
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250 | + int ret = 0; |
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251 | + struct ltq_i2c *priv = i2c_get_adapdata(adap); |
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252 | + |
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253 | + /* disable bus */ |
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254 | + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); |
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255 | + |
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256 | +#ifndef DEBUG |
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257 | + /* set normal operation clock divider */ |
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258 | + i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); |
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259 | +#else |
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260 | + /* for debugging a higher divider value! */ |
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261 | + i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); |
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262 | +#endif |
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263 | + |
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264 | + /* setup clock */ |
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265 | + ret = ltq_i2c_hw_set_clock(adap); |
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266 | + if (ret != 0) { |
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267 | + dev_warn(priv->dev, "invalid clock settings\n"); |
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268 | + return ret; |
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269 | + } |
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270 | + |
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271 | + /* configure fifo */ |
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272 | + i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ |
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273 | + I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ |
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274 | + I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ |
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275 | + I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ |
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276 | + I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ |
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277 | + I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ |
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278 | + fifo_cfg); |
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279 | + |
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280 | + /* configure address */ |
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281 | + i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in |
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282 | + the fifo */ |
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283 | + I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ |
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284 | + I2C_ADDR_CFG_MnS_EN | /* we are master device */ |
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285 | + 0, /* our slave address (not used!) */ |
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286 | + addr_cfg); |
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287 | + |
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288 | + /* enable bus */ |
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289 | + i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); |
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290 | + |
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291 | + return 0; |
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292 | +} |
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293 | + |
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294 | +static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv) |
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295 | +{ |
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296 | + unsigned long timeout; |
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297 | + |
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298 | + timeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT); |
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299 | + |
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300 | + do { |
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301 | + u32 stat = i2c_r32(bus_stat); |
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302 | + |
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303 | + if ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE) |
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304 | + return 0; |
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305 | + |
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306 | + cond_resched(); |
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307 | + } while (!time_after_eq(jiffies, timeout)); |
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308 | + |
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309 | + dev_err(priv->dev, "timeout waiting for bus ready\n"); |
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310 | + return -ETIMEDOUT; |
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311 | +} |
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312 | + |
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313 | +static void ltq_i2c_tx(struct ltq_i2c *priv, int last) |
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314 | +{ |
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315 | + if (priv->msg_buf_len && priv->msg_buf) { |
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316 | + i2c_w32(*priv->msg_buf, txd); |
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317 | + |
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318 | + if (--priv->msg_buf_len) |
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319 | + priv->msg_buf++; |
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320 | + else |
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321 | + priv->msg_buf = NULL; |
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322 | + } else { |
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323 | + last = 1; |
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324 | + } |
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325 | + |
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326 | + if (last) |
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327 | + disable_burst_irq(priv); |
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328 | +} |
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329 | + |
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330 | +static void ltq_i2c_rx(struct ltq_i2c *priv, int last) |
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331 | +{ |
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332 | + u32 fifo_stat, timeout; |
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333 | + if (priv->msg_buf_len && priv->msg_buf) { |
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334 | + timeout = 5000000; |
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335 | + do { |
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336 | + fifo_stat = i2c_r32(ffs_stat); |
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337 | + } while (!fifo_stat && --timeout); |
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338 | + if (!timeout) { |
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339 | + last = 1; |
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340 | + pr_debug("\nrx timeout\n"); |
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341 | + goto err; |
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342 | + } |
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343 | + while (fifo_stat) { |
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344 | + *priv->msg_buf = i2c_r32(rxd); |
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345 | + if (--priv->msg_buf_len) { |
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346 | + priv->msg_buf++; |
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347 | + } else { |
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348 | + priv->msg_buf = NULL; |
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349 | + last = 1; |
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350 | + break; |
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351 | + } |
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352 | + /* |
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353 | + * do not read more than burst size, otherwise no "last |
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354 | + * burst" is generated and the transaction is blocked! |
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355 | + */ |
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356 | + fifo_stat = 0; |
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357 | + } |
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358 | + } else { |
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359 | + last = 1; |
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360 | + } |
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361 | +err: |
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362 | + if (last) { |
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363 | + disable_burst_irq(priv); |
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364 | + |
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365 | + if (priv->status == STATUS_READ_END) { |
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366 | + /* |
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367 | + * do the STATUS_STOP and complete() here, as sometimes |
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368 | + * the tx_end is already seen before this is finished |
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369 | + */ |
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370 | + priv->status = STATUS_STOP; |
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371 | + complete(&priv->cmd_complete); |
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372 | + } else { |
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373 | + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); |
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374 | + priv->status = STATUS_READ_END; |
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375 | + } |
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376 | + } |
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377 | +} |
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378 | + |
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379 | +static void ltq_i2c_xfer_init(struct ltq_i2c *priv) |
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380 | +{ |
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381 | + /* enable interrupts */ |
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382 | + i2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc); |
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383 | + |
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384 | + /* trigger transfer of first msg */ |
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385 | + ltq_i2c_set_tx_len(priv); |
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386 | +} |
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387 | + |
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388 | +static void dump_msgs(struct i2c_msg msgs[], int num, int rx) |
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389 | +{ |
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390 | +#if defined(DEBUG) |
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391 | + int i, j; |
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392 | + pr_debug("Messages %d %s\n", num, rx ? "out" : "in"); |
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393 | + for (i = 0; i < num; i++) { |
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394 | + pr_debug("%2d %cX Msg(%d) addr=0x%X: ", i, |
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395 | + (msgs[i].flags & I2C_M_RD) ? 'R' : 'T', |
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396 | + msgs[i].len, msgs[i].addr); |
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397 | + if (!(msgs[i].flags & I2C_M_RD) || rx) { |
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398 | + for (j = 0; j < msgs[i].len; j++) |
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399 | + pr_debug("%02X ", msgs[i].buf[j]); |
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400 | + } |
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401 | + pr_debug("\n"); |
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402 | + } |
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403 | +#endif |
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404 | +} |
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405 | + |
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406 | +static void ltq_i2c_release_bus(struct ltq_i2c *priv) |
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407 | +{ |
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408 | + if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) |
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409 | + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); |
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410 | +} |
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411 | + |
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412 | +static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], |
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413 | + int num) |
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414 | +{ |
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415 | + struct ltq_i2c *priv = i2c_get_adapdata(adap); |
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416 | + int ret; |
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417 | + |
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418 | + dev_dbg(priv->dev, "xfer %u messages\n", num); |
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419 | + dump_msgs(msgs, num, 0); |
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420 | + |
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421 | + mutex_lock(&priv->mutex); |
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422 | + |
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423 | + init_completion(&priv->cmd_complete); |
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424 | + priv->current_msg = msgs; |
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425 | + priv->msgs_num = num; |
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426 | + priv->msg_err = 0; |
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427 | + priv->status = STATUS_IDLE; |
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428 | + |
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429 | + /* wait for the bus to become ready */ |
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430 | + ret = ltq_i2c_wait_bus_not_busy(priv); |
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431 | + if (ret) |
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432 | + goto done; |
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433 | + |
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434 | + while (priv->msgs_num) { |
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435 | + /* start the transfers */ |
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436 | + ltq_i2c_xfer_init(priv); |
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437 | + |
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438 | + /* wait for transfers to complete */ |
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439 | + ret = wait_for_completion_interruptible_timeout( |
||
440 | + &priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT); |
||
441 | + if (ret == 0) { |
||
442 | + dev_err(priv->dev, "controller timed out\n"); |
||
443 | + ltq_i2c_hw_init(adap); |
||
444 | + ret = -ETIMEDOUT; |
||
445 | + goto done; |
||
446 | + } else if (ret < 0) |
||
447 | + goto done; |
||
448 | + |
||
449 | + if (priv->msg_err) { |
||
450 | + if (priv->msg_err & LTQ_I2C_NACK) |
||
451 | + ret = -ENXIO; |
||
452 | + else |
||
453 | + ret = -EREMOTEIO; |
||
454 | + goto done; |
||
455 | + } |
||
456 | + if (--priv->msgs_num) |
||
457 | + priv->current_msg++; |
||
458 | + } |
||
459 | + /* no error? */ |
||
460 | + ret = num; |
||
461 | + |
||
462 | +done: |
||
463 | + ltq_i2c_release_bus(priv); |
||
464 | + |
||
465 | + mutex_unlock(&priv->mutex); |
||
466 | + |
||
467 | + if (ret >= 0) |
||
468 | + dump_msgs(msgs, num, 1); |
||
469 | + |
||
470 | + pr_debug("XFER ret %d\n", ret); |
||
471 | + return ret; |
||
472 | +} |
||
473 | + |
||
474 | +static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id) |
||
475 | +{ |
||
476 | + struct ltq_i2c *priv = dev_id; |
||
477 | + struct i2c_msg *msg = priv->current_msg; |
||
478 | + int last = (irq == priv->irq_lb); |
||
479 | + |
||
480 | + if (last) |
||
481 | + pr_debug("LB "); |
||
482 | + else |
||
483 | + pr_debug("B "); |
||
484 | + |
||
485 | + if (msg->flags & I2C_M_RD) { |
||
486 | + switch (priv->status) { |
||
487 | + case STATUS_ADDR: |
||
488 | + pr_debug("X"); |
||
489 | + prepare_msg_send_addr(priv); |
||
490 | + disable_burst_irq(priv); |
||
491 | + break; |
||
492 | + case STATUS_READ: |
||
493 | + case STATUS_READ_END: |
||
494 | + pr_debug("R"); |
||
495 | + ltq_i2c_rx(priv, last); |
||
496 | + break; |
||
497 | + default: |
||
498 | + disable_burst_irq(priv); |
||
499 | + pr_warn("Status R %d\n", priv->status); |
||
500 | + break; |
||
501 | + } |
||
502 | + } else { |
||
503 | + switch (priv->status) { |
||
504 | + case STATUS_ADDR: |
||
505 | + pr_debug("x"); |
||
506 | + prepare_msg_send_addr(priv); |
||
507 | + break; |
||
508 | + case STATUS_WRITE: |
||
509 | + pr_debug("w"); |
||
510 | + ltq_i2c_tx(priv, last); |
||
511 | + break; |
||
512 | + default: |
||
513 | + disable_burst_irq(priv); |
||
514 | + pr_warn("Status W %d\n", priv->status); |
||
515 | + break; |
||
516 | + } |
||
517 | + } |
||
518 | + |
||
519 | + i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); |
||
520 | + return IRQ_HANDLED; |
||
521 | +} |
||
522 | + |
||
523 | +static void ltq_i2c_isr_prot(struct ltq_i2c *priv) |
||
524 | +{ |
||
525 | + u32 i_pro = i2c_r32(p_irqss); |
||
526 | + |
||
527 | + pr_debug("i2c-p"); |
||
528 | + |
||
529 | + /* not acknowledge */ |
||
530 | + if (i_pro & I2C_P_IRQSS_NACK) { |
||
531 | + priv->msg_err |= LTQ_I2C_NACK; |
||
532 | + pr_debug(" nack"); |
||
533 | + } |
||
534 | + |
||
535 | + /* arbitration lost */ |
||
536 | + if (i_pro & I2C_P_IRQSS_AL) { |
||
537 | + priv->msg_err |= LTQ_I2C_ARB_LOST; |
||
538 | + pr_debug(" arb-lost"); |
||
539 | + } |
||
540 | + /* tx -> rx switch */ |
||
541 | + if (i_pro & I2C_P_IRQSS_RX) |
||
542 | + pr_debug(" rx"); |
||
543 | + |
||
544 | + /* tx end */ |
||
545 | + if (i_pro & I2C_P_IRQSS_TX_END) |
||
546 | + pr_debug(" txend"); |
||
547 | + pr_debug("\n"); |
||
548 | + |
||
549 | + if (!priv->msg_err) { |
||
550 | + /* tx -> rx switch */ |
||
551 | + if (i_pro & I2C_P_IRQSS_RX) { |
||
552 | + priv->status = STATUS_READ; |
||
553 | + enable_burst_irq(priv); |
||
554 | + } |
||
555 | + if (i_pro & I2C_P_IRQSS_TX_END) { |
||
556 | + if (priv->status == STATUS_READ) |
||
557 | + priv->status = STATUS_READ_END; |
||
558 | + else { |
||
559 | + disable_burst_irq(priv); |
||
560 | + priv->status = STATUS_STOP; |
||
561 | + } |
||
562 | + } |
||
563 | + } |
||
564 | + |
||
565 | + i2c_w32(i_pro, p_irqsc); |
||
566 | +} |
||
567 | + |
||
568 | +static irqreturn_t ltq_i2c_isr(int irq, void *dev_id) |
||
569 | +{ |
||
570 | + u32 i_raw, i_err = 0; |
||
571 | + struct ltq_i2c *priv = dev_id; |
||
572 | + |
||
573 | + i_raw = i2c_r32(mis); |
||
574 | + pr_debug("i_raw 0x%08X\n", i_raw); |
||
575 | + |
||
576 | + /* error interrupt */ |
||
577 | + if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { |
||
578 | + i_err = i2c_r32(err_irqss); |
||
579 | + pr_debug("i_err 0x%08X bus_stat 0x%04X\n", |
||
580 | + i_err, i2c_r32(bus_stat)); |
||
581 | + |
||
582 | + /* tx fifo overflow (8) */ |
||
583 | + if (i_err & I2C_ERR_IRQSS_TXF_OFL) |
||
584 | + priv->msg_err |= LTQ_I2C_TX_OFL; |
||
585 | + |
||
586 | + /* tx fifo underflow (4) */ |
||
587 | + if (i_err & I2C_ERR_IRQSS_TXF_UFL) |
||
588 | + priv->msg_err |= LTQ_I2C_TX_UFL; |
||
589 | + |
||
590 | + /* rx fifo overflow (2) */ |
||
591 | + if (i_err & I2C_ERR_IRQSS_RXF_OFL) |
||
592 | + priv->msg_err |= LTQ_I2C_RX_OFL; |
||
593 | + |
||
594 | + /* rx fifo underflow (1) */ |
||
595 | + if (i_err & I2C_ERR_IRQSS_RXF_UFL) |
||
596 | + priv->msg_err |= LTQ_I2C_RX_UFL; |
||
597 | + |
||
598 | + i2c_w32(i_err, err_irqsc); |
||
599 | + } |
||
600 | + |
||
601 | + /* protocol interrupt */ |
||
602 | + if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) |
||
603 | + ltq_i2c_isr_prot(priv); |
||
604 | + |
||
605 | + if ((priv->msg_err) || (priv->status == STATUS_STOP)) |
||
606 | + complete(&priv->cmd_complete); |
||
607 | + |
||
608 | + return IRQ_HANDLED; |
||
609 | +} |
||
610 | + |
||
611 | +static u32 ltq_i2c_functionality(struct i2c_adapter *adap) |
||
612 | +{ |
||
613 | + return I2C_FUNC_I2C | |
||
614 | + I2C_FUNC_10BIT_ADDR | |
||
615 | + I2C_FUNC_SMBUS_EMUL; |
||
616 | +} |
||
617 | + |
||
618 | +static struct i2c_algorithm ltq_i2c_algorithm = { |
||
619 | + .master_xfer = ltq_i2c_xfer, |
||
620 | + .functionality = ltq_i2c_functionality, |
||
621 | +}; |
||
622 | + |
||
623 | +static int ltq_i2c_probe(struct platform_device *pdev) |
||
624 | +{ |
||
625 | + struct device_node *node = pdev->dev.of_node; |
||
626 | + struct ltq_i2c *priv; |
||
627 | + struct i2c_adapter *adap; |
||
628 | + struct resource *mmres, irqres[4]; |
||
629 | + int ret = 0; |
||
630 | + |
||
631 | + dev_dbg(&pdev->dev, "probing\n"); |
||
632 | + |
||
633 | + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||
634 | + ret = of_irq_to_resource_table(node, irqres, 4); |
||
635 | + if (!mmres || (ret != 4)) { |
||
636 | + dev_err(&pdev->dev, "no resources\n"); |
||
637 | + return -ENODEV; |
||
638 | + } |
||
639 | + |
||
640 | + /* allocate private data */ |
||
641 | + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
||
642 | + if (!priv) { |
||
643 | + dev_err(&pdev->dev, "can't allocate private data\n"); |
||
644 | + return -ENOMEM; |
||
645 | + } |
||
646 | + |
||
647 | + adap = &priv->adap; |
||
648 | + i2c_set_adapdata(adap, priv); |
||
649 | + adap->owner = THIS_MODULE; |
||
650 | + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; |
||
651 | + strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); |
||
652 | + adap->algo = <q_i2c_algorithm; |
||
653 | + adap->dev.parent = &pdev->dev; |
||
654 | + adap->dev.of_node = pdev->dev.of_node; |
||
655 | + |
||
656 | + if (of_property_read_u32(node, "clock-frequency", &priv->i2c_clock)) { |
||
657 | + dev_warn(&pdev->dev, "No I2C speed selected, using 100kHz\n"); |
||
658 | + priv->i2c_clock = 100000; |
||
659 | + } |
||
660 | + |
||
661 | + init_completion(&priv->cmd_complete); |
||
662 | + mutex_init(&priv->mutex); |
||
663 | + |
||
664 | + priv->membase = devm_ioremap_resource(&pdev->dev, mmres); |
||
665 | + if (IS_ERR(priv->membase)) |
||
666 | + return PTR_ERR(priv->membase); |
||
667 | + |
||
668 | + priv->dev = &pdev->dev; |
||
669 | + priv->irq_lb = irqres[0].start; |
||
670 | + |
||
671 | + ret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst, |
||
672 | + 0x0, "i2c lb", priv); |
||
673 | + if (ret) { |
||
674 | + dev_err(&pdev->dev, "can't get last burst IRQ %d\n", |
||
675 | + irqres[0].start); |
||
676 | + return -ENODEV; |
||
677 | + } |
||
678 | + |
||
679 | + ret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst, |
||
680 | + 0x0, "i2c b", priv); |
||
681 | + if (ret) { |
||
682 | + dev_err(&pdev->dev, "can't get burst IRQ %d\n", |
||
683 | + irqres[1].start); |
||
684 | + return -ENODEV; |
||
685 | + } |
||
686 | + |
||
687 | + ret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr, |
||
688 | + 0x0, "i2c err", priv); |
||
689 | + if (ret) { |
||
690 | + dev_err(&pdev->dev, "can't get error IRQ %d\n", |
||
691 | + irqres[2].start); |
||
692 | + return -ENODEV; |
||
693 | + } |
||
694 | + |
||
695 | + ret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr, |
||
696 | + 0x0, "i2c p", priv); |
||
697 | + if (ret) { |
||
698 | + dev_err(&pdev->dev, "can't get protocol IRQ %d\n", |
||
699 | + irqres[3].start); |
||
700 | + return -ENODEV; |
||
701 | + } |
||
702 | + |
||
703 | + dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); |
||
704 | + dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres[0].start, |
||
705 | + irqres[1].start, irqres[2].start, irqres[3].start); |
||
706 | + |
||
707 | + priv->clk_gate = devm_clk_get(&pdev->dev, NULL); |
||
708 | + if (IS_ERR(priv->clk_gate)) { |
||
709 | + dev_err(&pdev->dev, "failed to get i2c clk\n"); |
||
710 | + return -ENOENT; |
||
711 | + } |
||
712 | + |
||
713 | + /* this is a static clock, which has no refcounting */ |
||
714 | + priv->clk_input = clk_get_fpi(); |
||
715 | + if (IS_ERR(priv->clk_input)) { |
||
716 | + dev_err(&pdev->dev, "failed to get fpi clk\n"); |
||
717 | + return -ENOENT; |
||
718 | + } |
||
719 | + |
||
720 | + clk_activate(priv->clk_gate); |
||
721 | + |
||
722 | + /* add our adapter to the i2c stack */ |
||
723 | + ret = i2c_add_numbered_adapter(adap); |
||
724 | + if (ret) { |
||
725 | + dev_err(&pdev->dev, "can't register I2C adapter\n"); |
||
726 | + goto out; |
||
727 | + } |
||
728 | + |
||
729 | + platform_set_drvdata(pdev, priv); |
||
730 | + i2c_set_adapdata(adap, priv); |
||
731 | + |
||
732 | + /* print module version information */ |
||
733 | + dev_dbg(&pdev->dev, "module id=%u revision=%u\n", |
||
734 | + (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, |
||
735 | + (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); |
||
736 | + |
||
737 | + /* initialize HW */ |
||
738 | + ret = ltq_i2c_hw_init(adap); |
||
739 | + if (ret) { |
||
740 | + dev_err(&pdev->dev, "can't configure adapter\n"); |
||
741 | + i2c_del_adapter(adap); |
||
742 | + platform_set_drvdata(pdev, NULL); |
||
743 | + goto out; |
||
744 | + } else { |
||
745 | + dev_info(&pdev->dev, "version %s\n", DRV_VERSION); |
||
746 | + } |
||
747 | + |
||
748 | +out: |
||
749 | + /* if init failed, we need to deactivate the clock gate */ |
||
750 | + if (ret) |
||
751 | + clk_deactivate(priv->clk_gate); |
||
752 | + |
||
753 | + return ret; |
||
754 | +} |
||
755 | + |
||
756 | +static int ltq_i2c_remove(struct platform_device *pdev) |
||
757 | +{ |
||
758 | + struct ltq_i2c *priv = platform_get_drvdata(pdev); |
||
759 | + |
||
760 | + /* disable bus */ |
||
761 | + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); |
||
762 | + |
||
763 | + /* power down the core */ |
||
764 | + clk_deactivate(priv->clk_gate); |
||
765 | + |
||
766 | + /* remove driver */ |
||
767 | + i2c_del_adapter(&priv->adap); |
||
768 | + kfree(priv); |
||
769 | + |
||
770 | + dev_dbg(&pdev->dev, "removed\n"); |
||
771 | + platform_set_drvdata(pdev, NULL); |
||
772 | + |
||
773 | + return 0; |
||
774 | +} |
||
775 | +static const struct of_device_id ltq_i2c_match[] = { |
||
776 | + { .compatible = "lantiq,lantiq-i2c" }, |
||
777 | + {}, |
||
778 | +}; |
||
779 | +MODULE_DEVICE_TABLE(of, ltq_i2c_match); |
||
780 | + |
||
781 | +static struct platform_driver ltq_i2c_driver = { |
||
782 | + .probe = ltq_i2c_probe, |
||
783 | + .remove = ltq_i2c_remove, |
||
784 | + .driver = { |
||
785 | + .name = DRV_NAME, |
||
786 | + .owner = THIS_MODULE, |
||
787 | + .of_match_table = ltq_i2c_match, |
||
788 | + }, |
||
789 | +}; |
||
790 | + |
||
791 | +module_platform_driver(ltq_i2c_driver); |
||
792 | + |
||
793 | +MODULE_DESCRIPTION("Lantiq I2C bus adapter"); |
||
794 | +MODULE_AUTHOR("Thomas Langer <thomas.langer@lantiq.com>"); |
||
795 | +MODULE_ALIAS("platform:" DRV_NAME); |
||
796 | +MODULE_LICENSE("GPL"); |
||
797 | +MODULE_VERSION(DRV_VERSION); |
||
798 | --- /dev/null |
||
799 | +++ b/drivers/i2c/busses/i2c-lantiq.h |
||
800 | @@ -0,0 +1,234 @@ |
||
801 | +#ifndef I2C_LANTIQ_H |
||
802 | +#define I2C_LANTIQ_H |
||
803 | + |
||
804 | +/* I2C register structure */ |
||
805 | +struct lantiq_reg_i2c { |
||
806 | + /* I2C Kernel Clock Control Register */ |
||
807 | + unsigned int clc; /* 0x00000000 */ |
||
808 | + /* Reserved */ |
||
809 | + unsigned int res_0; /* 0x00000004 */ |
||
810 | + /* I2C Identification Register */ |
||
811 | + unsigned int id; /* 0x00000008 */ |
||
812 | + /* Reserved */ |
||
813 | + unsigned int res_1; /* 0x0000000C */ |
||
814 | + /* |
||
815 | + * I2C RUN Control Register |
||
816 | + * This register enables and disables the I2C peripheral. Before |
||
817 | + * enabling, the I2C has to be configured properly. After enabling |
||
818 | + * no configuration is possible |
||
819 | + */ |
||
820 | + unsigned int run_ctrl; /* 0x00000010 */ |
||
821 | + /* |
||
822 | + * I2C End Data Control Register |
||
823 | + * This register is used to either turn around the data transmission |
||
824 | + * direction or to address another slave without sending a stop |
||
825 | + * condition. Also the software can stop the slave-transmitter by |
||
826 | + * sending a not-accolade when working as master-receiver or even |
||
827 | + * stop data transmission immediately when operating as |
||
828 | + * master-transmitter. The writing to the bits of this control |
||
829 | + * register is only effective when in MASTER RECEIVES BYTES, MASTER |
||
830 | + * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state |
||
831 | + */ |
||
832 | + unsigned int endd_ctrl; /* 0x00000014 */ |
||
833 | + /* |
||
834 | + * I2C Fractional Divider Configuration Register |
||
835 | + * These register is used to program the fractional divider of the I2C |
||
836 | + * bus. Before the peripheral is switched on by setting the RUN-bit the |
||
837 | + * two (fixed) values for the two operating frequencies are programmed |
||
838 | + * into these (configuration) registers. The Register FDIV_HIGH_CFG has |
||
839 | + * the same layout as I2C_FDIV_CFG. |
||
840 | + */ |
||
841 | + unsigned int fdiv_cfg; /* 0x00000018 */ |
||
842 | + /* |
||
843 | + * I2C Fractional Divider (highspeed mode) Configuration Register |
||
844 | + * These register is used to program the fractional divider of the I2C |
||
845 | + * bus. Before the peripheral is switched on by setting the RUN-bit the |
||
846 | + * two (fixed) values for the two operating frequencies are programmed |
||
847 | + * into these (configuration) registers. The Register FDIV_CFG has the |
||
848 | + * same layout as I2C_FDIV_CFG. |
||
849 | + */ |
||
850 | + unsigned int fdiv_high_cfg; /* 0x0000001C */ |
||
851 | + /* I2C Address Configuration Register */ |
||
852 | + unsigned int addr_cfg; /* 0x00000020 */ |
||
853 | + /* I2C Bus Status Register |
||
854 | + * This register gives a status information of the I2C. This additional |
||
855 | + * information can be used by the software to start proper actions. |
||
856 | + */ |
||
857 | + unsigned int bus_stat; /* 0x00000024 */ |
||
858 | + /* I2C FIFO Configuration Register */ |
||
859 | + unsigned int fifo_cfg; /* 0x00000028 */ |
||
860 | + /* I2C Maximum Received Packet Size Register */ |
||
861 | + unsigned int mrps_ctrl; /* 0x0000002C */ |
||
862 | + /* I2C Received Packet Size Status Register */ |
||
863 | + unsigned int rps_stat; /* 0x00000030 */ |
||
864 | + /* I2C Transmit Packet Size Register */ |
||
865 | + unsigned int tps_ctrl; /* 0x00000034 */ |
||
866 | + /* I2C Filled FIFO Stages Status Register */ |
||
867 | + unsigned int ffs_stat; /* 0x00000038 */ |
||
868 | + /* Reserved */ |
||
869 | + unsigned int res_2; /* 0x0000003C */ |
||
870 | + /* I2C Timing Configuration Register */ |
||
871 | + unsigned int tim_cfg; /* 0x00000040 */ |
||
872 | + /* Reserved */ |
||
873 | + unsigned int res_3[7]; /* 0x00000044 */ |
||
874 | + /* I2C Error Interrupt Request Source Mask Register */ |
||
875 | + unsigned int err_irqsm; /* 0x00000060 */ |
||
876 | + /* I2C Error Interrupt Request Source Status Register */ |
||
877 | + unsigned int err_irqss; /* 0x00000064 */ |
||
878 | + /* I2C Error Interrupt Request Source Clear Register */ |
||
879 | + unsigned int err_irqsc; /* 0x00000068 */ |
||
880 | + /* Reserved */ |
||
881 | + unsigned int res_4; /* 0x0000006C */ |
||
882 | + /* I2C Protocol Interrupt Request Source Mask Register */ |
||
883 | + unsigned int p_irqsm; /* 0x00000070 */ |
||
884 | + /* I2C Protocol Interrupt Request Source Status Register */ |
||
885 | + unsigned int p_irqss; /* 0x00000074 */ |
||
886 | + /* I2C Protocol Interrupt Request Source Clear Register */ |
||
887 | + unsigned int p_irqsc; /* 0x00000078 */ |
||
888 | + /* Reserved */ |
||
889 | + unsigned int res_5; /* 0x0000007C */ |
||
890 | + /* I2C Raw Interrupt Status Register */ |
||
891 | + unsigned int ris; /* 0x00000080 */ |
||
892 | + /* I2C Interrupt Mask Control Register */ |
||
893 | + unsigned int imsc; /* 0x00000084 */ |
||
894 | + /* I2C Masked Interrupt Status Register */ |
||
895 | + unsigned int mis; /* 0x00000088 */ |
||
896 | + /* I2C Interrupt Clear Register */ |
||
897 | + unsigned int icr; /* 0x0000008C */ |
||
898 | + /* I2C Interrupt Set Register */ |
||
899 | + unsigned int isr; /* 0x00000090 */ |
||
900 | + /* I2C DMA Enable Register */ |
||
901 | + unsigned int dmae; /* 0x00000094 */ |
||
902 | + /* Reserved */ |
||
903 | + unsigned int res_6[8154]; /* 0x00000098 */ |
||
904 | + /* I2C Transmit Data Register */ |
||
905 | + unsigned int txd; /* 0x00008000 */ |
||
906 | + /* Reserved */ |
||
907 | + unsigned int res_7[4095]; /* 0x00008004 */ |
||
908 | + /* I2C Receive Data Register */ |
||
909 | + unsigned int rxd; /* 0x0000C000 */ |
||
910 | + /* Reserved */ |
||
911 | + unsigned int res_8[4095]; /* 0x0000C004 */ |
||
912 | +}; |
||
913 | + |
||
914 | +/* |
||
915 | + * Clock Divider for Normal Run Mode |
||
916 | + * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long |
||
917 | + * as the new divider value RMC is not valid, the register returns 0x0000 00xx |
||
918 | + * on reading. |
||
919 | + */ |
||
920 | +#define I2C_CLC_RMC_MASK 0x0000FF00 |
||
921 | +/* field offset */ |
||
922 | +#define I2C_CLC_RMC_OFFSET 8 |
||
923 | + |
||
924 | +/* Fields of "I2C Identification Register" */ |
||
925 | +/* Module ID */ |
||
926 | +#define I2C_ID_ID_MASK 0x0000FF00 |
||
927 | +/* field offset */ |
||
928 | +#define I2C_ID_ID_OFFSET 8 |
||
929 | +/* Revision */ |
||
930 | +#define I2C_ID_REV_MASK 0x000000FF |
||
931 | +/* field offset */ |
||
932 | +#define I2C_ID_REV_OFFSET 0 |
||
933 | + |
||
934 | +/* Fields of "I2C Interrupt Mask Control Register" */ |
||
935 | +/* Enable */ |
||
936 | +#define I2C_IMSC_BREQ_INT_EN 0x00000008 |
||
937 | +/* Enable */ |
||
938 | +#define I2C_IMSC_LBREQ_INT_EN 0x00000004 |
||
939 | + |
||
940 | +/* Fields of "I2C Fractional Divider Configuration Register" */ |
||
941 | +/* field offset */ |
||
942 | +#define I2C_FDIV_CFG_INC_OFFSET 16 |
||
943 | + |
||
944 | +/* Fields of "I2C Interrupt Mask Control Register" */ |
||
945 | +/* Enable */ |
||
946 | +#define I2C_IMSC_I2C_P_INT_EN 0x00000020 |
||
947 | +/* Enable */ |
||
948 | +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 |
||
949 | + |
||
950 | +/* Fields of "I2C Error Interrupt Request Source Status Register" */ |
||
951 | +/* TXF_OFL */ |
||
952 | +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 |
||
953 | +/* TXF_UFL */ |
||
954 | +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 |
||
955 | +/* RXF_OFL */ |
||
956 | +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 |
||
957 | +/* RXF_UFL */ |
||
958 | +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 |
||
959 | + |
||
960 | +/* Fields of "I2C Raw Interrupt Status Register" */ |
||
961 | +/* Read: Interrupt occurred. */ |
||
962 | +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 |
||
963 | +/* Read: Interrupt occurred. */ |
||
964 | +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 |
||
965 | + |
||
966 | +/* Fields of "I2C FIFO Configuration Register" */ |
||
967 | +/* TX FIFO Flow Control */ |
||
968 | +#define I2C_FIFO_CFG_TXFC 0x00020000 |
||
969 | +/* RX FIFO Flow Control */ |
||
970 | +#define I2C_FIFO_CFG_RXFC 0x00010000 |
||
971 | +/* Word aligned (character alignment of four characters) */ |
||
972 | +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 |
||
973 | +/* Word aligned (character alignment of four characters) */ |
||
974 | +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 |
||
975 | +/* 1 word */ |
||
976 | +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 |
||
977 | + |
||
978 | +/* Fields of "I2C FIFO Configuration Register" */ |
||
979 | +/* 1 word */ |
||
980 | +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 |
||
981 | +/* Stop on Packet End Enable */ |
||
982 | +#define I2C_ADDR_CFG_SOPE_EN 0x00200000 |
||
983 | +/* Stop on Not Acknowledge Enable */ |
||
984 | +#define I2C_ADDR_CFG_SONA_EN 0x00100000 |
||
985 | +/* Enable */ |
||
986 | +#define I2C_ADDR_CFG_MnS_EN 0x00080000 |
||
987 | + |
||
988 | +/* Fields of "I2C Interrupt Clear Register" */ |
||
989 | +/* Clear */ |
||
990 | +#define I2C_ICR_BREQ_INT_CLR 0x00000008 |
||
991 | +/* Clear */ |
||
992 | +#define I2C_ICR_LBREQ_INT_CLR 0x00000004 |
||
993 | + |
||
994 | +/* Fields of "I2C Fractional Divider Configuration Register" */ |
||
995 | +/* field offset */ |
||
996 | +#define I2C_FDIV_CFG_DEC_OFFSET 0 |
||
997 | + |
||
998 | +/* Fields of "I2C Bus Status Register" */ |
||
999 | +/* Bus Status */ |
||
1000 | +#define I2C_BUS_STAT_BS_MASK 0x00000003 |
||
1001 | +/* Read from I2C Bus. */ |
||
1002 | +#define I2C_BUS_STAT_RNW_READ 0x00000004 |
||
1003 | +/* I2C Bus is free. */ |
||
1004 | +#define I2C_BUS_STAT_BS_FREE 0x00000000 |
||
1005 | +/* |
||
1006 | + * The device is working as master and has claimed the control on the |
||
1007 | + * I2C-bus (busy master). |
||
1008 | + */ |
||
1009 | +#define I2C_BUS_STAT_BS_BM 0x00000002 |
||
1010 | + |
||
1011 | +/* Fields of "I2C RUN Control Register" */ |
||
1012 | +/* Enable */ |
||
1013 | +#define I2C_RUN_CTRL_RUN_EN 0x00000001 |
||
1014 | + |
||
1015 | +/* Fields of "I2C End Data Control Register" */ |
||
1016 | +/* |
||
1017 | + * Set End of Transmission |
||
1018 | + * Note:Do not write '1' to this bit when bus is free. This will cause an |
||
1019 | + * abort after the first byte when a new transfer is started. |
||
1020 | + */ |
||
1021 | +#define I2C_ENDD_CTRL_SETEND 0x00000002 |
||
1022 | + |
||
1023 | +/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ |
||
1024 | +/* NACK */ |
||
1025 | +#define I2C_P_IRQSS_NACK 0x00000010 |
||
1026 | +/* AL */ |
||
1027 | +#define I2C_P_IRQSS_AL 0x00000008 |
||
1028 | +/* RX */ |
||
1029 | +#define I2C_P_IRQSS_RX 0x00000040 |
||
1030 | +/* TX_END */ |
||
1031 | +#define I2C_P_IRQSS_TX_END 0x00000020 |
||
1032 | + |
||
1033 | + |
||
1034 | +#endif /* I2C_LANTIQ_H */ |