OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 490d103232287eb51c92c49a4ef8865fd0a9d59e Mon Sep 17 00:00:00 2001 |
2 | From: Sham Muthayyan <smuthayy@codeaurora.org> |
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3 | Date: Tue, 19 Jul 2016 18:58:18 +0530 |
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4 | Subject: PCI: qcom: Fixed IPQ806x PCIE reset changes |
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5 | |||
6 | Change-Id: Ia6590e960b9754b1e8b7a51f318788cd63e9e321 |
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7 | Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> |
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8 | --- |
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9 | drivers/pci/host/pcie-qcom.c | 24 +++++++++++++++++++----- |
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10 | 1 file changed, 19 insertions(+), 5 deletions(-) |
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11 | |||
12 | --- a/drivers/pci/dwc/pcie-qcom.c |
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13 | +++ b/drivers/pci/dwc/pcie-qcom.c |
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14 | @@ -98,6 +98,7 @@ struct qcom_pcie_resources_2_1_0 { |
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15 | struct reset_control *ahb_reset; |
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16 | struct reset_control *por_reset; |
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17 | struct reset_control *phy_reset; |
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18 | + struct reset_control *ext_reset; |
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19 | struct regulator *vdda; |
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20 | struct regulator *vdda_phy; |
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21 | struct regulator *vdda_refclk; |
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22 | @@ -275,6 +276,10 @@ static int qcom_pcie_get_resources_2_1_0 |
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23 | if (IS_ERR(res->por_reset)) |
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24 | return PTR_ERR(res->por_reset); |
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25 | |||
26 | + res->ext_reset = devm_reset_control_get(dev, "ext"); |
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27 | + if (IS_ERR(res->ext_reset)) |
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28 | + return PTR_ERR(res->ext_reset); |
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29 | + |
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30 | res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); |
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31 | return PTR_ERR_OR_ZERO(res->phy_reset); |
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32 | } |
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33 | @@ -288,6 +293,7 @@ static void qcom_pcie_deinit_2_1_0(struc |
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34 | reset_control_assert(res->ahb_reset); |
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35 | reset_control_assert(res->por_reset); |
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36 | reset_control_assert(res->pci_reset); |
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37 | + reset_control_assert(res->ext_reset); |
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38 | clk_disable_unprepare(res->iface_clk); |
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39 | clk_disable_unprepare(res->core_clk); |
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40 | clk_disable_unprepare(res->phy_clk); |
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41 | @@ -306,6 +312,12 @@ static int qcom_pcie_init_2_1_0(struct q |
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42 | u32 val; |
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43 | int ret; |
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44 | |||
45 | + ret = reset_control_assert(res->ahb_reset); |
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46 | + if (ret) { |
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47 | + dev_err(dev, "cannot assert ahb reset\n"); |
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48 | + return ret; |
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49 | + } |
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50 | + |
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51 | ret = regulator_enable(res->vdda); |
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52 | if (ret) { |
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53 | dev_err(dev, "cannot enable vdda regulator\n"); |
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54 | @@ -324,16 +336,16 @@ static int qcom_pcie_init_2_1_0(struct q |
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55 | goto err_vdda_phy; |
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56 | } |
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57 | |||
58 | - ret = reset_control_assert(res->ahb_reset); |
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59 | + ret = reset_control_deassert(res->ext_reset); |
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60 | if (ret) { |
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61 | - dev_err(dev, "cannot assert ahb reset\n"); |
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62 | - goto err_assert_ahb; |
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63 | + dev_err(dev, "cannot assert ext reset\n"); |
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64 | + goto err_reset_ext; |
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65 | } |
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66 | |||
67 | ret = clk_prepare_enable(res->iface_clk); |
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68 | if (ret) { |
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69 | dev_err(dev, "cannot prepare/enable iface clock\n"); |
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70 | - goto err_assert_ahb; |
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71 | + goto err_iface; |
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72 | } |
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73 | |||
74 | ret = clk_prepare_enable(res->core_clk); |
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75 | @@ -422,7 +434,9 @@ err_clk_phy: |
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76 | clk_disable_unprepare(res->core_clk); |
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77 | err_clk_core: |
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78 | clk_disable_unprepare(res->iface_clk); |
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79 | -err_assert_ahb: |
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80 | +err_iface: |
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81 | + reset_control_assert(res->ext_reset); |
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82 | +err_reset_ext: |
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83 | regulator_disable(res->vdda_phy); |
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84 | err_vdda_phy: |
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85 | regulator_disable(res->vdda_refclk); |