OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From: Niklas Cassel <niklas.cassel@linaro.org> |
2 | Subject: [PATCH] ARM: dts: qcom: ipq4019: Fix MSI IRQ type |
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3 | Date: Thu, 24 Jan 2019 14:00:47 +0100 |
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4 | |||
5 | The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level |
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6 | triggered interrupt. |
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7 | |||
8 | The msi_ctrl_int will be high for as long as any MSI status bit is set, |
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9 | thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the |
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10 | IRQ handler to keep getting called, as long as any MSI status bit is set. |
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11 | |||
12 | A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has |
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13 | configured this IRQ incorrectly. |
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14 | |||
15 | Not having the correct IRQ type defined will cause us to lose interrupts, |
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16 | which in turn causes timeouts in the PCIe endpoint drivers. |
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17 | |||
18 | Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> |
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19 | Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> |
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20 | --- |
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21 | |||
22 | --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi |
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23 | +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi |
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24 | @@ -404,7 +404,7 @@ |
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25 | ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, |
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26 | <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; |
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27 | |||
28 | - interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; |
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29 | + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
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30 | interrupt-names = "msi"; |
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31 | #interrupt-cells = <1>; |
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32 | interrupt-map-mask = <0 0 0 0x7>; |