OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * ar8327.c: AR8216 switch driver |
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3 | * |
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4 | * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> |
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5 | * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or |
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8 | * modify it under the terms of the GNU General Public License |
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9 | * as published by the Free Software Foundation; either version 2 |
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10 | * of the License, or (at your option) any later version. |
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11 | * |
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12 | * This program is distributed in the hope that it will be useful, |
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13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | * GNU General Public License for more details. |
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16 | */ |
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17 | |||
18 | #include <linux/list.h> |
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19 | #include <linux/bitops.h> |
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20 | #include <linux/switch.h> |
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21 | #include <linux/delay.h> |
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22 | #include <linux/phy.h> |
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23 | #include <linux/lockdep.h> |
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24 | #include <linux/ar8216_platform.h> |
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25 | #include <linux/workqueue.h> |
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26 | #include <linux/of_device.h> |
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27 | #include <linux/leds.h> |
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28 | #include <linux/mdio.h> |
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29 | |||
30 | #include "ar8216.h" |
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31 | #include "ar8327.h" |
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32 | |||
33 | extern const struct ar8xxx_mib_desc ar8236_mibs[39]; |
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34 | extern const struct switch_attr ar8xxx_sw_attr_vlan[1]; |
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35 | |||
36 | static u32 |
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37 | ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg) |
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38 | { |
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39 | u32 t; |
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40 | |||
41 | if (!cfg) |
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42 | return 0; |
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43 | |||
44 | t = 0; |
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45 | switch (cfg->mode) { |
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46 | case AR8327_PAD_NC: |
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47 | break; |
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48 | |||
49 | case AR8327_PAD_MAC2MAC_MII: |
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50 | t = AR8327_PAD_MAC_MII_EN; |
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51 | if (cfg->rxclk_sel) |
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52 | t |= AR8327_PAD_MAC_MII_RXCLK_SEL; |
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53 | if (cfg->txclk_sel) |
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54 | t |= AR8327_PAD_MAC_MII_TXCLK_SEL; |
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55 | break; |
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56 | |||
57 | case AR8327_PAD_MAC2MAC_GMII: |
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58 | t = AR8327_PAD_MAC_GMII_EN; |
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59 | if (cfg->rxclk_sel) |
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60 | t |= AR8327_PAD_MAC_GMII_RXCLK_SEL; |
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61 | if (cfg->txclk_sel) |
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62 | t |= AR8327_PAD_MAC_GMII_TXCLK_SEL; |
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63 | break; |
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64 | |||
65 | case AR8327_PAD_MAC_SGMII: |
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66 | t = AR8327_PAD_SGMII_EN; |
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67 | |||
68 | /* |
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69 | * WAR for the QUalcomm Atheros AP136 board. |
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70 | * It seems that RGMII TX/RX delay settings needs to be |
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71 | * applied for SGMII mode as well, The ethernet is not |
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72 | * reliable without this. |
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73 | */ |
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74 | t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; |
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75 | t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; |
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76 | if (cfg->rxclk_delay_en) |
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77 | t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; |
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78 | if (cfg->txclk_delay_en) |
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79 | t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; |
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80 | |||
81 | if (cfg->sgmii_delay_en) |
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82 | t |= AR8327_PAD_SGMII_DELAY_EN; |
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83 | |||
84 | break; |
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85 | |||
86 | case AR8327_PAD_MAC2PHY_MII: |
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87 | t = AR8327_PAD_PHY_MII_EN; |
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88 | if (cfg->rxclk_sel) |
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89 | t |= AR8327_PAD_PHY_MII_RXCLK_SEL; |
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90 | if (cfg->txclk_sel) |
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91 | t |= AR8327_PAD_PHY_MII_TXCLK_SEL; |
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92 | break; |
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93 | |||
94 | case AR8327_PAD_MAC2PHY_GMII: |
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95 | t = AR8327_PAD_PHY_GMII_EN; |
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96 | if (cfg->pipe_rxclk_sel) |
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97 | t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL; |
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98 | if (cfg->rxclk_sel) |
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99 | t |= AR8327_PAD_PHY_GMII_RXCLK_SEL; |
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100 | if (cfg->txclk_sel) |
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101 | t |= AR8327_PAD_PHY_GMII_TXCLK_SEL; |
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102 | break; |
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103 | |||
104 | case AR8327_PAD_MAC_RGMII: |
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105 | t = AR8327_PAD_RGMII_EN; |
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106 | t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S; |
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107 | t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S; |
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108 | if (cfg->rxclk_delay_en) |
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109 | t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN; |
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110 | if (cfg->txclk_delay_en) |
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111 | t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN; |
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112 | break; |
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113 | |||
114 | case AR8327_PAD_PHY_GMII: |
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115 | t = AR8327_PAD_PHYX_GMII_EN; |
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116 | break; |
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117 | |||
118 | case AR8327_PAD_PHY_RGMII: |
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119 | t = AR8327_PAD_PHYX_RGMII_EN; |
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120 | break; |
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121 | |||
122 | case AR8327_PAD_PHY_MII: |
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123 | t = AR8327_PAD_PHYX_MII_EN; |
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124 | break; |
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125 | } |
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126 | |||
127 | return t; |
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128 | } |
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129 | |||
130 | static void |
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131 | ar8327_phy_rgmii_set(struct ar8xxx_priv *priv, struct phy_device *phydev) |
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132 | { |
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133 | u16 phy_val = 0; |
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134 | int phyaddr = phydev->mdio.addr; |
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135 | struct device_node *np = phydev->mdio.dev.of_node; |
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136 | |||
137 | if (!np) |
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138 | return; |
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139 | |||
140 | if (!of_property_read_bool(np, "qca,phy-rgmii-en")) { |
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141 | pr_err("ar8327: qca,phy-rgmii-en is not specified\n"); |
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142 | return; |
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143 | } |
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144 | ar8xxx_phy_dbg_read(priv, phyaddr, |
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145 | AR8327_PHY_MODE_SEL, &phy_val); |
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146 | phy_val |= AR8327_PHY_MODE_SEL_RGMII; |
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147 | ar8xxx_phy_dbg_write(priv, phyaddr, |
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148 | AR8327_PHY_MODE_SEL, phy_val); |
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149 | |||
150 | /* set rgmii tx clock delay if needed */ |
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151 | if (!of_property_read_bool(np, "qca,txclk-delay-en")) { |
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152 | pr_err("ar8327: qca,txclk-delay-en is not specified\n"); |
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153 | return; |
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154 | } |
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155 | ar8xxx_phy_dbg_read(priv, phyaddr, |
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156 | AR8327_PHY_SYS_CTRL, &phy_val); |
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157 | phy_val |= AR8327_PHY_SYS_CTRL_RGMII_TX_DELAY; |
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158 | ar8xxx_phy_dbg_write(priv, phyaddr, |
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159 | AR8327_PHY_SYS_CTRL, phy_val); |
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160 | |||
161 | /* set rgmii rx clock delay if needed */ |
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162 | if (!of_property_read_bool(np, "qca,rxclk-delay-en")) { |
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163 | pr_err("ar8327: qca,rxclk-delay-en is not specified\n"); |
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164 | return; |
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165 | } |
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166 | ar8xxx_phy_dbg_read(priv, phyaddr, |
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167 | AR8327_PHY_TEST_CTRL, &phy_val); |
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168 | phy_val |= AR8327_PHY_TEST_CTRL_RGMII_RX_DELAY; |
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169 | ar8xxx_phy_dbg_write(priv, phyaddr, |
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170 | AR8327_PHY_TEST_CTRL, phy_val); |
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171 | } |
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172 | |||
173 | static void |
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174 | ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy) |
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175 | { |
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176 | switch (priv->chip_rev) { |
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177 | case 1: |
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178 | /* For 100M waveform */ |
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179 | ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea); |
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180 | /* Turn on Gigabit clock */ |
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181 | ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0); |
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182 | break; |
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183 | |||
184 | case 2: |
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185 | ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0); |
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186 | /* fallthrough */ |
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187 | case 4: |
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188 | ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f); |
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189 | ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860); |
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190 | ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46); |
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191 | ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000); |
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192 | break; |
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193 | } |
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194 | } |
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195 | |||
196 | static u32 |
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197 | ar8327_get_port_init_status(struct ar8327_port_cfg *cfg) |
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198 | { |
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199 | u32 t; |
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200 | |||
201 | if (!cfg->force_link) |
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202 | return AR8216_PORT_STATUS_LINK_AUTO; |
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203 | |||
204 | t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC; |
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205 | t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0; |
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206 | t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0; |
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207 | t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0; |
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208 | |||
209 | switch (cfg->speed) { |
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210 | case AR8327_PORT_SPEED_10: |
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211 | t |= AR8216_PORT_SPEED_10M; |
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212 | break; |
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213 | case AR8327_PORT_SPEED_100: |
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214 | t |= AR8216_PORT_SPEED_100M; |
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215 | break; |
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216 | case AR8327_PORT_SPEED_1000: |
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217 | t |= AR8216_PORT_SPEED_1000M; |
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218 | break; |
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219 | } |
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220 | |||
221 | return t; |
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222 | } |
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223 | |||
224 | #define AR8327_LED_ENTRY(_num, _reg, _shift) \ |
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225 | [_num] = { .reg = (_reg), .shift = (_shift) } |
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226 | |||
227 | static const struct ar8327_led_entry |
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228 | ar8327_led_map[AR8327_NUM_LEDS] = { |
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229 | AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14), |
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230 | AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14), |
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231 | AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14), |
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232 | |||
233 | AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8), |
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234 | AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10), |
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235 | AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12), |
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236 | |||
237 | AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14), |
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238 | AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16), |
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239 | AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18), |
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240 | |||
241 | AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20), |
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242 | AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22), |
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243 | AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24), |
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244 | |||
245 | AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30), |
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246 | AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30), |
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247 | AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30), |
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248 | }; |
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249 | |||
250 | static void |
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251 | ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num, |
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252 | enum ar8327_led_pattern pattern) |
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253 | { |
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254 | const struct ar8327_led_entry *entry; |
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255 | |||
256 | entry = &ar8327_led_map[led_num]; |
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257 | ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg), |
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258 | (3 << entry->shift), pattern << entry->shift); |
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259 | } |
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260 | |||
261 | static void |
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262 | ar8327_led_work_func(struct work_struct *work) |
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263 | { |
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264 | struct ar8327_led *aled; |
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265 | u8 pattern; |
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266 | |||
267 | aled = container_of(work, struct ar8327_led, led_work); |
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268 | |||
269 | pattern = aled->pattern; |
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270 | |||
271 | ar8327_set_led_pattern(aled->sw_priv, aled->led_num, |
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272 | pattern); |
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273 | } |
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274 | |||
275 | static void |
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276 | ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern) |
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277 | { |
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278 | if (aled->pattern == pattern) |
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279 | return; |
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280 | |||
281 | aled->pattern = pattern; |
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282 | schedule_work(&aled->led_work); |
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283 | } |
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284 | |||
285 | static inline struct ar8327_led * |
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286 | led_cdev_to_ar8327_led(struct led_classdev *led_cdev) |
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287 | { |
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288 | return container_of(led_cdev, struct ar8327_led, cdev); |
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289 | } |
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290 | |||
291 | static int |
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292 | ar8327_led_blink_set(struct led_classdev *led_cdev, |
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293 | unsigned long *delay_on, |
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294 | unsigned long *delay_off) |
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295 | { |
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296 | struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); |
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297 | |||
298 | if (*delay_on == 0 && *delay_off == 0) { |
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299 | *delay_on = 125; |
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300 | *delay_off = 125; |
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301 | } |
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302 | |||
303 | if (*delay_on != 125 || *delay_off != 125) { |
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304 | /* |
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305 | * The hardware only supports blinking at 4Hz. Fall back |
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306 | * to software implementation in other cases. |
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307 | */ |
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308 | return -EINVAL; |
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309 | } |
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310 | |||
311 | spin_lock(&aled->lock); |
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312 | |||
313 | aled->enable_hw_mode = false; |
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314 | ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK); |
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315 | |||
316 | spin_unlock(&aled->lock); |
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317 | |||
318 | return 0; |
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319 | } |
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320 | |||
321 | static void |
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322 | ar8327_led_set_brightness(struct led_classdev *led_cdev, |
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323 | enum led_brightness brightness) |
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324 | { |
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325 | struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); |
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326 | u8 pattern; |
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327 | bool active; |
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328 | |||
329 | active = (brightness != LED_OFF); |
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330 | active ^= aled->active_low; |
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331 | |||
332 | pattern = (active) ? AR8327_LED_PATTERN_ON : |
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333 | AR8327_LED_PATTERN_OFF; |
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334 | |||
335 | spin_lock(&aled->lock); |
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336 | |||
337 | aled->enable_hw_mode = false; |
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338 | ar8327_led_schedule_change(aled, pattern); |
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339 | |||
340 | spin_unlock(&aled->lock); |
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341 | } |
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342 | |||
343 | static ssize_t |
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344 | ar8327_led_enable_hw_mode_show(struct device *dev, |
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345 | struct device_attribute *attr, |
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346 | char *buf) |
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347 | { |
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348 | struct led_classdev *led_cdev = dev_get_drvdata(dev); |
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349 | struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); |
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350 | ssize_t ret = 0; |
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351 | |||
352 | ret += scnprintf(buf, PAGE_SIZE, "%d\n", aled->enable_hw_mode); |
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353 | |||
354 | return ret; |
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355 | } |
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356 | |||
357 | static ssize_t |
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358 | ar8327_led_enable_hw_mode_store(struct device *dev, |
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359 | struct device_attribute *attr, |
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360 | const char *buf, |
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361 | size_t size) |
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362 | { |
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363 | struct led_classdev *led_cdev = dev_get_drvdata(dev); |
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364 | struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev); |
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365 | u8 pattern; |
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366 | u8 value; |
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367 | int ret; |
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368 | |||
369 | ret = kstrtou8(buf, 10, &value); |
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370 | if (ret < 0) |
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371 | return -EINVAL; |
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372 | |||
373 | spin_lock(&aled->lock); |
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374 | |||
375 | aled->enable_hw_mode = !!value; |
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376 | if (aled->enable_hw_mode) |
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377 | pattern = AR8327_LED_PATTERN_RULE; |
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378 | else |
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379 | pattern = AR8327_LED_PATTERN_OFF; |
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380 | |||
381 | ar8327_led_schedule_change(aled, pattern); |
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382 | |||
383 | spin_unlock(&aled->lock); |
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384 | |||
385 | return size; |
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386 | } |
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387 | |||
388 | static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR, |
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389 | ar8327_led_enable_hw_mode_show, |
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390 | ar8327_led_enable_hw_mode_store); |
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391 | |||
392 | static int |
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393 | ar8327_led_register(struct ar8327_led *aled) |
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394 | { |
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395 | int ret; |
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396 | |||
397 | ret = led_classdev_register(NULL, &aled->cdev); |
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398 | if (ret < 0) |
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399 | return ret; |
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400 | |||
401 | if (aled->mode == AR8327_LED_MODE_HW) { |
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402 | ret = device_create_file(aled->cdev.dev, |
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403 | &dev_attr_enable_hw_mode); |
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404 | if (ret) |
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405 | goto err_unregister; |
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406 | } |
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407 | |||
408 | return 0; |
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409 | |||
410 | err_unregister: |
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411 | led_classdev_unregister(&aled->cdev); |
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412 | return ret; |
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413 | } |
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414 | |||
415 | static void |
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416 | ar8327_led_unregister(struct ar8327_led *aled) |
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417 | { |
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418 | if (aled->mode == AR8327_LED_MODE_HW) |
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419 | device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode); |
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420 | |||
421 | led_classdev_unregister(&aled->cdev); |
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422 | cancel_work_sync(&aled->led_work); |
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423 | } |
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424 | |||
425 | static int |
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426 | ar8327_led_create(struct ar8xxx_priv *priv, |
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427 | const struct ar8327_led_info *led_info) |
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428 | { |
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429 | struct ar8327_data *data = priv->chip_data; |
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430 | struct ar8327_led *aled; |
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431 | int ret; |
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432 | |||
433 | if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS)) |
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434 | return 0; |
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435 | |||
436 | if (!led_info->name) |
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437 | return -EINVAL; |
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438 | |||
439 | if (led_info->led_num >= AR8327_NUM_LEDS) |
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440 | return -EINVAL; |
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441 | |||
442 | aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1, |
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443 | GFP_KERNEL); |
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444 | if (!aled) |
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445 | return -ENOMEM; |
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446 | |||
447 | aled->sw_priv = priv; |
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448 | aled->led_num = led_info->led_num; |
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449 | aled->active_low = led_info->active_low; |
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450 | aled->mode = led_info->mode; |
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451 | |||
452 | if (aled->mode == AR8327_LED_MODE_HW) |
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453 | aled->enable_hw_mode = true; |
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454 | |||
455 | aled->name = (char *)(aled + 1); |
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456 | strcpy(aled->name, led_info->name); |
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457 | |||
458 | aled->cdev.name = aled->name; |
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459 | aled->cdev.brightness_set = ar8327_led_set_brightness; |
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460 | aled->cdev.blink_set = ar8327_led_blink_set; |
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461 | aled->cdev.default_trigger = led_info->default_trigger; |
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462 | |||
463 | spin_lock_init(&aled->lock); |
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464 | mutex_init(&aled->mutex); |
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465 | INIT_WORK(&aled->led_work, ar8327_led_work_func); |
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466 | |||
467 | ret = ar8327_led_register(aled); |
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468 | if (ret) |
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469 | goto err_free; |
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470 | |||
471 | data->leds[data->num_leds++] = aled; |
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472 | |||
473 | return 0; |
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474 | |||
475 | err_free: |
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476 | kfree(aled); |
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477 | return ret; |
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478 | } |
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479 | |||
480 | static void |
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481 | ar8327_led_destroy(struct ar8327_led *aled) |
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482 | { |
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483 | ar8327_led_unregister(aled); |
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484 | kfree(aled); |
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485 | } |
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486 | |||
487 | static void |
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488 | ar8327_leds_init(struct ar8xxx_priv *priv) |
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489 | { |
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490 | struct ar8327_data *data = priv->chip_data; |
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491 | unsigned i; |
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492 | |||
493 | if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS)) |
||
494 | return; |
||
495 | |||
496 | for (i = 0; i < data->num_leds; i++) { |
||
497 | struct ar8327_led *aled; |
||
498 | |||
499 | aled = data->leds[i]; |
||
500 | |||
501 | if (aled->enable_hw_mode) |
||
502 | aled->pattern = AR8327_LED_PATTERN_RULE; |
||
503 | else |
||
504 | aled->pattern = AR8327_LED_PATTERN_OFF; |
||
505 | |||
506 | ar8327_set_led_pattern(priv, aled->led_num, aled->pattern); |
||
507 | } |
||
508 | } |
||
509 | |||
510 | static void |
||
511 | ar8327_leds_cleanup(struct ar8xxx_priv *priv) |
||
512 | { |
||
513 | struct ar8327_data *data = priv->chip_data; |
||
514 | unsigned i; |
||
515 | |||
516 | if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS)) |
||
517 | return; |
||
518 | |||
519 | for (i = 0; i < data->num_leds; i++) { |
||
520 | struct ar8327_led *aled; |
||
521 | |||
522 | aled = data->leds[i]; |
||
523 | ar8327_led_destroy(aled); |
||
524 | } |
||
525 | |||
526 | kfree(data->leds); |
||
527 | } |
||
528 | |||
529 | static int |
||
530 | ar8327_hw_config_pdata(struct ar8xxx_priv *priv, |
||
531 | struct ar8327_platform_data *pdata) |
||
532 | { |
||
533 | struct ar8327_led_cfg *led_cfg; |
||
534 | struct ar8327_data *data = priv->chip_data; |
||
535 | u32 pos, new_pos; |
||
536 | u32 t; |
||
537 | |||
538 | if (!pdata) |
||
539 | return -EINVAL; |
||
540 | |||
541 | priv->get_port_link = pdata->get_port_link; |
||
542 | |||
543 | data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg); |
||
544 | data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg); |
||
545 | |||
546 | t = ar8327_get_pad_cfg(pdata->pad0_cfg); |
||
547 | if (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis) |
||
548 | t |= AR8337_PAD_MAC06_EXCHANGE_EN; |
||
549 | ar8xxx_write(priv, AR8327_REG_PAD0_MODE, t); |
||
550 | |||
551 | t = ar8327_get_pad_cfg(pdata->pad5_cfg); |
||
552 | ar8xxx_write(priv, AR8327_REG_PAD5_MODE, t); |
||
553 | t = ar8327_get_pad_cfg(pdata->pad6_cfg); |
||
554 | ar8xxx_write(priv, AR8327_REG_PAD6_MODE, t); |
||
555 | |||
556 | pos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRIP); |
||
557 | new_pos = pos; |
||
558 | |||
559 | led_cfg = pdata->led_cfg; |
||
560 | if (led_cfg) { |
||
561 | if (led_cfg->open_drain) |
||
562 | new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN; |
||
563 | else |
||
564 | new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN; |
||
565 | |||
566 | ar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0); |
||
567 | ar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1); |
||
568 | ar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2); |
||
569 | ar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3); |
||
570 | |||
571 | if (new_pos != pos) |
||
572 | new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL; |
||
573 | } |
||
574 | |||
575 | if (pdata->sgmii_cfg) { |
||
576 | t = pdata->sgmii_cfg->sgmii_ctrl; |
||
577 | if (priv->chip_rev == 1) |
||
578 | t |= AR8327_SGMII_CTRL_EN_PLL | |
||
579 | AR8327_SGMII_CTRL_EN_RX | |
||
580 | AR8327_SGMII_CTRL_EN_TX; |
||
581 | else |
||
582 | t &= ~(AR8327_SGMII_CTRL_EN_PLL | |
||
583 | AR8327_SGMII_CTRL_EN_RX | |
||
584 | AR8327_SGMII_CTRL_EN_TX); |
||
585 | |||
586 | ar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t); |
||
587 | |||
588 | if (pdata->sgmii_cfg->serdes_aen) |
||
589 | new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN; |
||
590 | else |
||
591 | new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN; |
||
592 | } |
||
593 | |||
594 | ar8xxx_write(priv, AR8327_REG_POWER_ON_STRIP, new_pos); |
||
595 | |||
596 | if (pdata->leds && pdata->num_leds) { |
||
597 | int i; |
||
598 | |||
599 | data->leds = kzalloc(pdata->num_leds * sizeof(void *), |
||
600 | GFP_KERNEL); |
||
601 | if (!data->leds) |
||
602 | return -ENOMEM; |
||
603 | |||
604 | for (i = 0; i < pdata->num_leds; i++) |
||
605 | ar8327_led_create(priv, &pdata->leds[i]); |
||
606 | } |
||
607 | |||
608 | return 0; |
||
609 | } |
||
610 | |||
611 | #ifdef CONFIG_OF |
||
612 | static int |
||
613 | ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np) |
||
614 | { |
||
615 | struct ar8327_data *data = priv->chip_data; |
||
616 | const __be32 *paddr; |
||
617 | int len; |
||
618 | int i; |
||
619 | |||
620 | paddr = of_get_property(np, "qca,ar8327-initvals", &len); |
||
621 | if (!paddr || len < (2 * sizeof(*paddr))) |
||
622 | return -EINVAL; |
||
623 | |||
624 | len /= sizeof(*paddr); |
||
625 | |||
626 | for (i = 0; i < len - 1; i += 2) { |
||
627 | u32 reg; |
||
628 | u32 val; |
||
629 | |||
630 | reg = be32_to_cpup(paddr + i); |
||
631 | val = be32_to_cpup(paddr + i + 1); |
||
632 | |||
633 | switch (reg) { |
||
634 | case AR8327_REG_PORT_STATUS(0): |
||
635 | data->port0_status = val; |
||
636 | break; |
||
637 | case AR8327_REG_PORT_STATUS(6): |
||
638 | data->port6_status = val; |
||
639 | break; |
||
640 | default: |
||
641 | ar8xxx_write(priv, reg, val); |
||
642 | break; |
||
643 | } |
||
644 | } |
||
645 | |||
646 | return 0; |
||
647 | } |
||
648 | #else |
||
649 | static inline int |
||
650 | ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np) |
||
651 | { |
||
652 | return -EINVAL; |
||
653 | } |
||
654 | #endif |
||
655 | |||
656 | static int |
||
657 | ar8327_hw_init(struct ar8xxx_priv *priv) |
||
658 | { |
||
659 | int ret; |
||
660 | |||
661 | priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL); |
||
662 | if (!priv->chip_data) |
||
663 | return -ENOMEM; |
||
664 | |||
665 | if (priv->phy->mdio.dev.of_node) |
||
666 | ret = ar8327_hw_config_of(priv, priv->phy->mdio.dev.of_node); |
||
667 | else |
||
668 | ret = ar8327_hw_config_pdata(priv, |
||
669 | priv->phy->mdio.dev.platform_data); |
||
670 | |||
671 | if (ret) |
||
672 | return ret; |
||
673 | |||
674 | ar8327_leds_init(priv); |
||
675 | |||
676 | ar8xxx_phy_init(priv); |
||
677 | |||
678 | return 0; |
||
679 | } |
||
680 | |||
681 | static void |
||
682 | ar8327_cleanup(struct ar8xxx_priv *priv) |
||
683 | { |
||
684 | ar8327_leds_cleanup(priv); |
||
685 | } |
||
686 | |||
687 | static void |
||
688 | ar8327_init_globals(struct ar8xxx_priv *priv) |
||
689 | { |
||
690 | struct ar8327_data *data = priv->chip_data; |
||
691 | u32 t; |
||
692 | int i; |
||
693 | |||
694 | /* enable CPU port and disable mirror port */ |
||
695 | t = AR8327_FWD_CTRL0_CPU_PORT_EN | |
||
696 | AR8327_FWD_CTRL0_MIRROR_PORT; |
||
697 | ar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t); |
||
698 | |||
699 | /* forward multicast and broadcast frames to CPU */ |
||
700 | t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) | |
||
701 | (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) | |
||
702 | (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S); |
||
703 | ar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t); |
||
704 | |||
705 | /* enable jumbo frames */ |
||
706 | ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE, |
||
707 | AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2); |
||
708 | |||
709 | /* Enable MIB counters */ |
||
710 | ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN, |
||
711 | AR8327_MODULE_EN_MIB); |
||
712 | |||
713 | /* Disable EEE on all phy's due to stability issues */ |
||
714 | for (i = 0; i < AR8XXX_NUM_PHYS; i++) |
||
715 | data->eee[i] = false; |
||
716 | } |
||
717 | |||
718 | static void |
||
719 | ar8327_init_port(struct ar8xxx_priv *priv, int port) |
||
720 | { |
||
721 | struct ar8327_data *data = priv->chip_data; |
||
722 | u32 t; |
||
723 | |||
724 | if (port == AR8216_PORT_CPU) |
||
725 | t = data->port0_status; |
||
726 | else if (port == 6) |
||
727 | t = data->port6_status; |
||
728 | else |
||
729 | t = AR8216_PORT_STATUS_LINK_AUTO; |
||
730 | |||
731 | if (port != AR8216_PORT_CPU && port != 6) { |
||
732 | /*hw limitation:if configure mac when there is traffic, |
||
733 | port MAC may work abnormal. Need disable lan&wan mac at fisrt*/ |
||
734 | ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), 0); |
||
735 | msleep(100); |
||
736 | t |= AR8216_PORT_STATUS_FLOW_CONTROL; |
||
737 | ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t); |
||
738 | } else { |
||
739 | ar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t); |
||
740 | } |
||
741 | |||
742 | ar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0); |
||
743 | |||
744 | ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), 0); |
||
745 | |||
746 | t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S; |
||
747 | ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t); |
||
748 | |||
749 | t = AR8327_PORT_LOOKUP_LEARN; |
||
750 | t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; |
||
751 | ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t); |
||
752 | } |
||
753 | |||
754 | static u32 |
||
755 | ar8327_read_port_status(struct ar8xxx_priv *priv, int port) |
||
756 | { |
||
757 | u32 t; |
||
758 | |||
759 | t = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port)); |
||
760 | /* map the flow control autoneg result bits to the flow control bits |
||
761 | * used in forced mode to allow ar8216_read_port_link detect |
||
762 | * flow control properly if autoneg is used |
||
763 | */ |
||
764 | if (t & AR8216_PORT_STATUS_LINK_UP && |
||
765 | t & AR8216_PORT_STATUS_LINK_AUTO) { |
||
766 | t &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW); |
||
767 | if (t & AR8327_PORT_STATUS_TXFLOW_AUTO) |
||
768 | t |= AR8216_PORT_STATUS_TXFLOW; |
||
769 | if (t & AR8327_PORT_STATUS_RXFLOW_AUTO) |
||
770 | t |= AR8216_PORT_STATUS_RXFLOW; |
||
771 | } |
||
772 | |||
773 | return t; |
||
774 | } |
||
775 | |||
776 | static u32 |
||
777 | ar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port) |
||
778 | { |
||
779 | int phy; |
||
780 | u16 t; |
||
781 | |||
782 | if (port >= priv->dev.ports) |
||
783 | return 0; |
||
784 | |||
785 | if (port == 0 || port == 6) |
||
786 | return 0; |
||
787 | |||
788 | phy = port - 1; |
||
789 | |||
790 | /* EEE Ability Auto-negotiation Result */ |
||
791 | t = ar8xxx_phy_mmd_read(priv, phy, 0x7, 0x8000); |
||
792 | |||
793 | return mmd_eee_adv_to_ethtool_adv_t(t); |
||
794 | } |
||
795 | |||
796 | static int |
||
797 | ar8327_atu_flush(struct ar8xxx_priv *priv) |
||
798 | { |
||
799 | int ret; |
||
800 | |||
801 | ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC, |
||
802 | AR8327_ATU_FUNC_BUSY, 0); |
||
803 | if (!ret) |
||
804 | ar8xxx_write(priv, AR8327_REG_ATU_FUNC, |
||
805 | AR8327_ATU_FUNC_OP_FLUSH | |
||
806 | AR8327_ATU_FUNC_BUSY); |
||
807 | |||
808 | return ret; |
||
809 | } |
||
810 | |||
811 | static int |
||
812 | ar8327_atu_flush_port(struct ar8xxx_priv *priv, int port) |
||
813 | { |
||
814 | u32 t; |
||
815 | int ret; |
||
816 | |||
817 | ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC, |
||
818 | AR8327_ATU_FUNC_BUSY, 0); |
||
819 | if (!ret) { |
||
820 | t = (port << AR8327_ATU_PORT_NUM_S); |
||
821 | t |= AR8327_ATU_FUNC_OP_FLUSH_PORT; |
||
822 | t |= AR8327_ATU_FUNC_BUSY; |
||
823 | ar8xxx_write(priv, AR8327_REG_ATU_FUNC, t); |
||
824 | } |
||
825 | |||
826 | return ret; |
||
827 | } |
||
828 | |||
829 | static int |
||
830 | ar8327_get_port_igmp(struct ar8xxx_priv *priv, int port) |
||
831 | { |
||
832 | u32 fwd_ctrl, frame_ack; |
||
833 | |||
834 | fwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S); |
||
835 | frame_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD | |
||
836 | AR8327_FRAME_ACK_CTRL_IGMP_JOIN | |
||
837 | AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) << |
||
838 | AR8327_FRAME_ACK_CTRL_S(port)); |
||
839 | |||
840 | return (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) & |
||
841 | fwd_ctrl) == fwd_ctrl && |
||
842 | (ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) & |
||
843 | frame_ack) == frame_ack; |
||
844 | } |
||
845 | |||
846 | static void |
||
847 | ar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable) |
||
848 | { |
||
849 | int reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port); |
||
850 | u32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD | |
||
851 | AR8327_FRAME_ACK_CTRL_IGMP_JOIN | |
||
852 | AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) << |
||
853 | AR8327_FRAME_ACK_CTRL_S(port); |
||
854 | |||
855 | if (enable) { |
||
856 | ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1, |
||
857 | BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S, |
||
858 | BIT(port) << AR8327_FWD_CTRL1_IGMP_S); |
||
859 | ar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack); |
||
860 | } else { |
||
861 | ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1, |
||
862 | BIT(port) << AR8327_FWD_CTRL1_IGMP_S, |
||
863 | BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S); |
||
864 | ar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack); |
||
865 | } |
||
866 | } |
||
867 | |||
868 | static void |
||
869 | ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val) |
||
870 | { |
||
871 | if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1, |
||
872 | AR8327_VTU_FUNC1_BUSY, 0)) |
||
873 | return; |
||
874 | |||
875 | if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD) |
||
876 | ar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val); |
||
877 | |||
878 | op |= AR8327_VTU_FUNC1_BUSY; |
||
879 | ar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op); |
||
880 | } |
||
881 | |||
882 | static void |
||
883 | ar8327_vtu_flush(struct ar8xxx_priv *priv) |
||
884 | { |
||
885 | ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0); |
||
886 | } |
||
887 | |||
888 | static void |
||
889 | ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask) |
||
890 | { |
||
891 | u32 op; |
||
892 | u32 val; |
||
893 | int i; |
||
894 | |||
895 | op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S); |
||
896 | val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL; |
||
897 | for (i = 0; i < AR8327_NUM_PORTS; i++) { |
||
898 | u32 mode; |
||
899 | |||
900 | if ((port_mask & BIT(i)) == 0) |
||
901 | mode = AR8327_VTU_FUNC0_EG_MODE_NOT; |
||
902 | else if (priv->vlan == 0) |
||
903 | mode = AR8327_VTU_FUNC0_EG_MODE_KEEP; |
||
904 | else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid)) |
||
905 | mode = AR8327_VTU_FUNC0_EG_MODE_TAG; |
||
906 | else |
||
907 | mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG; |
||
908 | |||
909 | val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i); |
||
910 | } |
||
911 | ar8327_vtu_op(priv, op, val); |
||
912 | } |
||
913 | |||
914 | static void |
||
915 | ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members) |
||
916 | { |
||
917 | u32 t; |
||
918 | u32 egress, ingress; |
||
919 | u32 pvid = priv->vlan_id[priv->pvid[port]]; |
||
920 | |||
921 | if (priv->vlan) { |
||
922 | egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD; |
||
923 | ingress = AR8216_IN_SECURE; |
||
924 | } else { |
||
925 | egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH; |
||
926 | ingress = AR8216_IN_PORT_ONLY; |
||
927 | } |
||
928 | |||
929 | t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S; |
||
930 | t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S; |
||
931 | if (priv->vlan && priv->port_vlan_prio[port]) { |
||
932 | u32 prio = priv->port_vlan_prio[port]; |
||
933 | |||
934 | t |= prio << AR8327_PORT_VLAN0_DEF_SPRI_S; |
||
935 | t |= prio << AR8327_PORT_VLAN0_DEF_CPRI_S; |
||
936 | } |
||
937 | ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t); |
||
938 | |||
939 | t = AR8327_PORT_VLAN1_PORT_VLAN_PROP; |
||
940 | t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S; |
||
941 | if (priv->vlan && priv->port_vlan_prio[port]) |
||
942 | t |= AR8327_PORT_VLAN1_VLAN_PRI_PROP; |
||
943 | |||
944 | ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t); |
||
945 | |||
946 | t = members; |
||
947 | t |= AR8327_PORT_LOOKUP_LEARN; |
||
948 | t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S; |
||
949 | t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S; |
||
950 | ar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t); |
||
951 | } |
||
952 | |||
953 | static int |
||
954 | ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val) |
||
955 | { |
||
956 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
957 | u8 ports = priv->vlan_table[val->port_vlan]; |
||
958 | int i; |
||
959 | |||
960 | val->len = 0; |
||
961 | for (i = 0; i < dev->ports; i++) { |
||
962 | struct switch_port *p; |
||
963 | |||
964 | if (!(ports & (1 << i))) |
||
965 | continue; |
||
966 | |||
967 | p = &val->value.ports[val->len++]; |
||
968 | p->id = i; |
||
969 | if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan)) |
||
970 | p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); |
||
971 | else |
||
972 | p->flags = 0; |
||
973 | } |
||
974 | return 0; |
||
975 | } |
||
976 | |||
977 | static int |
||
978 | ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val) |
||
979 | { |
||
980 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
981 | u8 *vt = &priv->vlan_table[val->port_vlan]; |
||
982 | int i; |
||
983 | |||
984 | *vt = 0; |
||
985 | for (i = 0; i < val->len; i++) { |
||
986 | struct switch_port *p = &val->value.ports[i]; |
||
987 | |||
988 | if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) { |
||
989 | if (val->port_vlan == priv->pvid[p->id]) { |
||
990 | priv->vlan_tagged |= (1 << p->id); |
||
991 | } |
||
992 | } else { |
||
993 | priv->vlan_tagged &= ~(1 << p->id); |
||
994 | priv->pvid[p->id] = val->port_vlan; |
||
995 | } |
||
996 | |||
997 | *vt |= 1 << p->id; |
||
998 | } |
||
999 | return 0; |
||
1000 | } |
||
1001 | |||
1002 | static void |
||
1003 | ar8327_set_mirror_regs(struct ar8xxx_priv *priv) |
||
1004 | { |
||
1005 | int port; |
||
1006 | |||
1007 | /* reset all mirror registers */ |
||
1008 | ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0, |
||
1009 | AR8327_FWD_CTRL0_MIRROR_PORT, |
||
1010 | (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S)); |
||
1011 | for (port = 0; port < AR8327_NUM_PORTS; port++) { |
||
1012 | ar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port), |
||
1013 | AR8327_PORT_LOOKUP_ING_MIRROR_EN); |
||
1014 | |||
1015 | ar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port), |
||
1016 | AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN); |
||
1017 | } |
||
1018 | |||
1019 | /* now enable mirroring if necessary */ |
||
1020 | if (priv->source_port >= AR8327_NUM_PORTS || |
||
1021 | priv->monitor_port >= AR8327_NUM_PORTS || |
||
1022 | priv->source_port == priv->monitor_port) { |
||
1023 | return; |
||
1024 | } |
||
1025 | |||
1026 | ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0, |
||
1027 | AR8327_FWD_CTRL0_MIRROR_PORT, |
||
1028 | (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S)); |
||
1029 | |||
1030 | if (priv->mirror_rx) |
||
1031 | ar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port), |
||
1032 | AR8327_PORT_LOOKUP_ING_MIRROR_EN); |
||
1033 | |||
1034 | if (priv->mirror_tx) |
||
1035 | ar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port), |
||
1036 | AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN); |
||
1037 | } |
||
1038 | |||
1039 | static int |
||
1040 | ar8327_sw_set_eee(struct switch_dev *dev, |
||
1041 | const struct switch_attr *attr, |
||
1042 | struct switch_val *val) |
||
1043 | { |
||
1044 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1045 | struct ar8327_data *data = priv->chip_data; |
||
1046 | int port = val->port_vlan; |
||
1047 | int phy; |
||
1048 | |||
1049 | if (port >= dev->ports) |
||
1050 | return -EINVAL; |
||
1051 | if (port == 0 || port == 6) |
||
1052 | return -EOPNOTSUPP; |
||
1053 | |||
1054 | phy = port - 1; |
||
1055 | |||
1056 | data->eee[phy] = !!(val->value.i); |
||
1057 | |||
1058 | return 0; |
||
1059 | } |
||
1060 | |||
1061 | static int |
||
1062 | ar8327_sw_get_eee(struct switch_dev *dev, |
||
1063 | const struct switch_attr *attr, |
||
1064 | struct switch_val *val) |
||
1065 | { |
||
1066 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1067 | const struct ar8327_data *data = priv->chip_data; |
||
1068 | int port = val->port_vlan; |
||
1069 | int phy; |
||
1070 | |||
1071 | if (port >= dev->ports) |
||
1072 | return -EINVAL; |
||
1073 | if (port == 0 || port == 6) |
||
1074 | return -EOPNOTSUPP; |
||
1075 | |||
1076 | phy = port - 1; |
||
1077 | |||
1078 | val->value.i = data->eee[phy]; |
||
1079 | |||
1080 | return 0; |
||
1081 | } |
||
1082 | |||
1083 | static void |
||
1084 | ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1) |
||
1085 | { |
||
1086 | int timeout = 20; |
||
1087 | |||
1088 | while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout) { |
||
1089 | udelay(10); |
||
1090 | cond_resched(); |
||
1091 | } |
||
1092 | |||
1093 | if (!timeout) |
||
1094 | pr_err("ar8327: timeout waiting for atu to become ready\n"); |
||
1095 | } |
||
1096 | |||
1097 | static void ar8327_get_arl_entry(struct ar8xxx_priv *priv, |
||
1098 | struct arl_entry *a, u32 *status, enum arl_op op) |
||
1099 | { |
||
1100 | struct mii_bus *bus = priv->mii_bus; |
||
1101 | u16 r2, page; |
||
1102 | u16 r1_data0, r1_data1, r1_data2, r1_func; |
||
1103 | u32 val0, val1, val2; |
||
1104 | |||
1105 | split_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page); |
||
1106 | r2 |= 0x10; |
||
1107 | |||
1108 | r1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e; |
||
1109 | r1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e; |
||
1110 | r1_func = (AR8327_REG_ATU_FUNC >> 1) & 0x1e; |
||
1111 | |||
1112 | switch (op) { |
||
1113 | case AR8XXX_ARL_INITIALIZE: |
||
1114 | /* all ATU registers are on the same page |
||
1115 | * therefore set page only once |
||
1116 | */ |
||
1117 | bus->write(bus, 0x18, 0, page); |
||
1118 | wait_for_page_switch(); |
||
1119 | |||
1120 | ar8327_wait_atu_ready(priv, r2, r1_func); |
||
1121 | |||
1122 | ar8xxx_mii_write32(priv, r2, r1_data0, 0); |
||
1123 | ar8xxx_mii_write32(priv, r2, r1_data1, 0); |
||
1124 | ar8xxx_mii_write32(priv, r2, r1_data2, 0); |
||
1125 | break; |
||
1126 | case AR8XXX_ARL_GET_NEXT: |
||
1127 | ar8xxx_mii_write32(priv, r2, r1_func, |
||
1128 | AR8327_ATU_FUNC_OP_GET_NEXT | |
||
1129 | AR8327_ATU_FUNC_BUSY); |
||
1130 | ar8327_wait_atu_ready(priv, r2, r1_func); |
||
1131 | |||
1132 | val0 = ar8xxx_mii_read32(priv, r2, r1_data0); |
||
1133 | val1 = ar8xxx_mii_read32(priv, r2, r1_data1); |
||
1134 | val2 = ar8xxx_mii_read32(priv, r2, r1_data2); |
||
1135 | |||
1136 | *status = val2 & AR8327_ATU_STATUS; |
||
1137 | if (!*status) |
||
1138 | break; |
||
1139 | |||
1140 | a->portmap = (val1 & AR8327_ATU_PORTS) >> AR8327_ATU_PORTS_S; |
||
1141 | a->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S; |
||
1142 | a->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S; |
||
1143 | a->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S; |
||
1144 | a->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S; |
||
1145 | a->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S; |
||
1146 | a->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S; |
||
1147 | break; |
||
1148 | } |
||
1149 | } |
||
1150 | |||
1151 | static int |
||
1152 | ar8327_sw_hw_apply(struct switch_dev *dev) |
||
1153 | { |
||
1154 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1155 | const struct ar8327_data *data = priv->chip_data; |
||
1156 | int ret, i; |
||
1157 | |||
1158 | ret = ar8xxx_sw_hw_apply(dev); |
||
1159 | if (ret) |
||
1160 | return ret; |
||
1161 | |||
1162 | for (i=0; i < AR8XXX_NUM_PHYS; i++) { |
||
1163 | if (data->eee[i]) |
||
1164 | ar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL, |
||
1165 | AR8327_EEE_CTRL_DISABLE_PHY(i)); |
||
1166 | else |
||
1167 | ar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL, |
||
1168 | AR8327_EEE_CTRL_DISABLE_PHY(i)); |
||
1169 | } |
||
1170 | |||
1171 | return 0; |
||
1172 | } |
||
1173 | |||
1174 | int |
||
1175 | ar8327_sw_get_port_igmp_snooping(struct switch_dev *dev, |
||
1176 | const struct switch_attr *attr, |
||
1177 | struct switch_val *val) |
||
1178 | { |
||
1179 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1180 | int port = val->port_vlan; |
||
1181 | |||
1182 | if (port >= dev->ports) |
||
1183 | return -EINVAL; |
||
1184 | |||
1185 | mutex_lock(&priv->reg_mutex); |
||
1186 | val->value.i = ar8327_get_port_igmp(priv, port); |
||
1187 | mutex_unlock(&priv->reg_mutex); |
||
1188 | |||
1189 | return 0; |
||
1190 | } |
||
1191 | |||
1192 | int |
||
1193 | ar8327_sw_set_port_igmp_snooping(struct switch_dev *dev, |
||
1194 | const struct switch_attr *attr, |
||
1195 | struct switch_val *val) |
||
1196 | { |
||
1197 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1198 | int port = val->port_vlan; |
||
1199 | |||
1200 | if (port >= dev->ports) |
||
1201 | return -EINVAL; |
||
1202 | |||
1203 | mutex_lock(&priv->reg_mutex); |
||
1204 | ar8327_set_port_igmp(priv, port, val->value.i); |
||
1205 | mutex_unlock(&priv->reg_mutex); |
||
1206 | |||
1207 | return 0; |
||
1208 | } |
||
1209 | |||
1210 | int |
||
1211 | ar8327_sw_get_igmp_snooping(struct switch_dev *dev, |
||
1212 | const struct switch_attr *attr, |
||
1213 | struct switch_val *val) |
||
1214 | { |
||
1215 | int port; |
||
1216 | |||
1217 | for (port = 0; port < dev->ports; port++) { |
||
1218 | val->port_vlan = port; |
||
1219 | if (ar8327_sw_get_port_igmp_snooping(dev, attr, val) || |
||
1220 | !val->value.i) |
||
1221 | break; |
||
1222 | } |
||
1223 | |||
1224 | return 0; |
||
1225 | } |
||
1226 | |||
1227 | int |
||
1228 | ar8327_sw_set_igmp_snooping(struct switch_dev *dev, |
||
1229 | const struct switch_attr *attr, |
||
1230 | struct switch_val *val) |
||
1231 | { |
||
1232 | int port; |
||
1233 | |||
1234 | for (port = 0; port < dev->ports; port++) { |
||
1235 | val->port_vlan = port; |
||
1236 | if (ar8327_sw_set_port_igmp_snooping(dev, attr, val)) |
||
1237 | break; |
||
1238 | } |
||
1239 | |||
1240 | return 0; |
||
1241 | } |
||
1242 | |||
1243 | int |
||
1244 | ar8327_sw_get_igmp_v3(struct switch_dev *dev, |
||
1245 | const struct switch_attr *attr, |
||
1246 | struct switch_val *val) |
||
1247 | { |
||
1248 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1249 | u32 val_reg; |
||
1250 | |||
1251 | mutex_lock(&priv->reg_mutex); |
||
1252 | val_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1); |
||
1253 | val->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0); |
||
1254 | mutex_unlock(&priv->reg_mutex); |
||
1255 | |||
1256 | return 0; |
||
1257 | } |
||
1258 | |||
1259 | int |
||
1260 | ar8327_sw_set_igmp_v3(struct switch_dev *dev, |
||
1261 | const struct switch_attr *attr, |
||
1262 | struct switch_val *val) |
||
1263 | { |
||
1264 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1265 | |||
1266 | mutex_lock(&priv->reg_mutex); |
||
1267 | if (val->value.i) |
||
1268 | ar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1, |
||
1269 | AR8327_FRAME_ACK_CTRL_IGMP_V3_EN); |
||
1270 | else |
||
1271 | ar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1, |
||
1272 | AR8327_FRAME_ACK_CTRL_IGMP_V3_EN); |
||
1273 | mutex_unlock(&priv->reg_mutex); |
||
1274 | |||
1275 | return 0; |
||
1276 | } |
||
1277 | |||
1278 | static int |
||
1279 | ar8327_sw_set_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr, |
||
1280 | struct switch_val *val) |
||
1281 | { |
||
1282 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1283 | int port = val->port_vlan; |
||
1284 | |||
1285 | if (port >= dev->ports) |
||
1286 | return -EINVAL; |
||
1287 | if (port == 0 || port == 6) |
||
1288 | return -EOPNOTSUPP; |
||
1289 | if (val->value.i < 0 || val->value.i > 7) |
||
1290 | return -EINVAL; |
||
1291 | |||
1292 | priv->port_vlan_prio[port] = val->value.i; |
||
1293 | |||
1294 | return 0; |
||
1295 | } |
||
1296 | |||
1297 | static int |
||
1298 | ar8327_sw_get_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr, |
||
1299 | struct switch_val *val) |
||
1300 | { |
||
1301 | struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); |
||
1302 | int port = val->port_vlan; |
||
1303 | |||
1304 | val->value.i = priv->port_vlan_prio[port]; |
||
1305 | |||
1306 | return 0; |
||
1307 | } |
||
1308 | |||
1309 | static const struct switch_attr ar8327_sw_attr_globals[] = { |
||
1310 | { |
||
1311 | .type = SWITCH_TYPE_INT, |
||
1312 | .name = "enable_vlan", |
||
1313 | .description = "Enable VLAN mode", |
||
1314 | .set = ar8xxx_sw_set_vlan, |
||
1315 | .get = ar8xxx_sw_get_vlan, |
||
1316 | .max = 1 |
||
1317 | }, |
||
1318 | { |
||
1319 | .type = SWITCH_TYPE_NOVAL, |
||
1320 | .name = "reset_mibs", |
||
1321 | .description = "Reset all MIB counters", |
||
1322 | .set = ar8xxx_sw_set_reset_mibs, |
||
1323 | }, |
||
1324 | { |
||
1325 | .type = SWITCH_TYPE_INT, |
||
1326 | .name = "enable_mirror_rx", |
||
1327 | .description = "Enable mirroring of RX packets", |
||
1328 | .set = ar8xxx_sw_set_mirror_rx_enable, |
||
1329 | .get = ar8xxx_sw_get_mirror_rx_enable, |
||
1330 | .max = 1 |
||
1331 | }, |
||
1332 | { |
||
1333 | .type = SWITCH_TYPE_INT, |
||
1334 | .name = "enable_mirror_tx", |
||
1335 | .description = "Enable mirroring of TX packets", |
||
1336 | .set = ar8xxx_sw_set_mirror_tx_enable, |
||
1337 | .get = ar8xxx_sw_get_mirror_tx_enable, |
||
1338 | .max = 1 |
||
1339 | }, |
||
1340 | { |
||
1341 | .type = SWITCH_TYPE_INT, |
||
1342 | .name = "mirror_monitor_port", |
||
1343 | .description = "Mirror monitor port", |
||
1344 | .set = ar8xxx_sw_set_mirror_monitor_port, |
||
1345 | .get = ar8xxx_sw_get_mirror_monitor_port, |
||
1346 | .max = AR8327_NUM_PORTS - 1 |
||
1347 | }, |
||
1348 | { |
||
1349 | .type = SWITCH_TYPE_INT, |
||
1350 | .name = "mirror_source_port", |
||
1351 | .description = "Mirror source port", |
||
1352 | .set = ar8xxx_sw_set_mirror_source_port, |
||
1353 | .get = ar8xxx_sw_get_mirror_source_port, |
||
1354 | .max = AR8327_NUM_PORTS - 1 |
||
1355 | }, |
||
1356 | { |
||
1357 | .type = SWITCH_TYPE_INT, |
||
1358 | .name = "arl_age_time", |
||
1359 | .description = "ARL age time (secs)", |
||
1360 | .set = ar8xxx_sw_set_arl_age_time, |
||
1361 | .get = ar8xxx_sw_get_arl_age_time, |
||
1362 | }, |
||
1363 | { |
||
1364 | .type = SWITCH_TYPE_STRING, |
||
1365 | .name = "arl_table", |
||
1366 | .description = "Get ARL table", |
||
1367 | .set = NULL, |
||
1368 | .get = ar8xxx_sw_get_arl_table, |
||
1369 | }, |
||
1370 | { |
||
1371 | .type = SWITCH_TYPE_NOVAL, |
||
1372 | .name = "flush_arl_table", |
||
1373 | .description = "Flush ARL table", |
||
1374 | .set = ar8xxx_sw_set_flush_arl_table, |
||
1375 | }, |
||
1376 | { |
||
1377 | .type = SWITCH_TYPE_INT, |
||
1378 | .name = "igmp_snooping", |
||
1379 | .description = "Enable IGMP Snooping", |
||
1380 | .set = ar8327_sw_set_igmp_snooping, |
||
1381 | .get = ar8327_sw_get_igmp_snooping, |
||
1382 | .max = 1 |
||
1383 | }, |
||
1384 | { |
||
1385 | .type = SWITCH_TYPE_INT, |
||
1386 | .name = "igmp_v3", |
||
1387 | .description = "Enable IGMPv3 support", |
||
1388 | .set = ar8327_sw_set_igmp_v3, |
||
1389 | .get = ar8327_sw_get_igmp_v3, |
||
1390 | .max = 1 |
||
1391 | }, |
||
1392 | }; |
||
1393 | |||
1394 | static const struct switch_attr ar8327_sw_attr_port[] = { |
||
1395 | { |
||
1396 | .type = SWITCH_TYPE_NOVAL, |
||
1397 | .name = "reset_mib", |
||
1398 | .description = "Reset single port MIB counters", |
||
1399 | .set = ar8xxx_sw_set_port_reset_mib, |
||
1400 | }, |
||
1401 | { |
||
1402 | .type = SWITCH_TYPE_STRING, |
||
1403 | .name = "mib", |
||
1404 | .description = "Get port's MIB counters", |
||
1405 | .set = NULL, |
||
1406 | .get = ar8xxx_sw_get_port_mib, |
||
1407 | }, |
||
1408 | { |
||
1409 | .type = SWITCH_TYPE_INT, |
||
1410 | .name = "enable_eee", |
||
1411 | .description = "Enable EEE PHY sleep mode", |
||
1412 | .set = ar8327_sw_set_eee, |
||
1413 | .get = ar8327_sw_get_eee, |
||
1414 | .max = 1, |
||
1415 | }, |
||
1416 | { |
||
1417 | .type = SWITCH_TYPE_NOVAL, |
||
1418 | .name = "flush_arl_table", |
||
1419 | .description = "Flush port's ARL table entries", |
||
1420 | .set = ar8xxx_sw_set_flush_port_arl_table, |
||
1421 | }, |
||
1422 | { |
||
1423 | .type = SWITCH_TYPE_INT, |
||
1424 | .name = "igmp_snooping", |
||
1425 | .description = "Enable port's IGMP Snooping", |
||
1426 | .set = ar8327_sw_set_port_igmp_snooping, |
||
1427 | .get = ar8327_sw_get_port_igmp_snooping, |
||
1428 | .max = 1 |
||
1429 | }, |
||
1430 | { |
||
1431 | .type = SWITCH_TYPE_INT, |
||
1432 | .name = "vlan_prio", |
||
1433 | .description = "Port VLAN default priority (VLAN PCP) (0-7)", |
||
1434 | .set = ar8327_sw_set_port_vlan_prio, |
||
1435 | .get = ar8327_sw_get_port_vlan_prio, |
||
1436 | .max = 7, |
||
1437 | }, |
||
1438 | }; |
||
1439 | |||
1440 | static const struct switch_dev_ops ar8327_sw_ops = { |
||
1441 | .attr_global = { |
||
1442 | .attr = ar8327_sw_attr_globals, |
||
1443 | .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals), |
||
1444 | }, |
||
1445 | .attr_port = { |
||
1446 | .attr = ar8327_sw_attr_port, |
||
1447 | .n_attr = ARRAY_SIZE(ar8327_sw_attr_port), |
||
1448 | }, |
||
1449 | .attr_vlan = { |
||
1450 | .attr = ar8xxx_sw_attr_vlan, |
||
1451 | .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan), |
||
1452 | }, |
||
1453 | .get_port_pvid = ar8xxx_sw_get_pvid, |
||
1454 | .set_port_pvid = ar8xxx_sw_set_pvid, |
||
1455 | .get_vlan_ports = ar8327_sw_get_ports, |
||
1456 | .set_vlan_ports = ar8327_sw_set_ports, |
||
1457 | .apply_config = ar8327_sw_hw_apply, |
||
1458 | .reset_switch = ar8xxx_sw_reset_switch, |
||
1459 | .get_port_link = ar8xxx_sw_get_port_link, |
||
1460 | /* The following op is disabled as it hogs the CPU and degrades performance. |
||
1461 | An implementation has been attempted in 4d8a66d but reading MIB data is slow |
||
1462 | on ar8xxx switches. |
||
1463 | |||
1464 | The high CPU load has been traced down to the ar8xxx_reg_wait() call in |
||
1465 | ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by |
||
1466 | the request to update the MIB counter is cleared. */ |
||
1467 | #if 0 |
||
1468 | .get_port_stats = ar8xxx_sw_get_port_stats, |
||
1469 | #endif |
||
1470 | }; |
||
1471 | |||
1472 | const struct ar8xxx_chip ar8327_chip = { |
||
1473 | .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS, |
||
1474 | .config_at_probe = true, |
||
1475 | .mii_lo_first = true, |
||
1476 | |||
1477 | .name = "Atheros AR8327", |
||
1478 | .ports = AR8327_NUM_PORTS, |
||
1479 | .vlans = AR8X16_MAX_VLANS, |
||
1480 | .swops = &ar8327_sw_ops, |
||
1481 | |||
1482 | .reg_port_stats_start = 0x1000, |
||
1483 | .reg_port_stats_length = 0x100, |
||
1484 | .reg_arl_ctrl = AR8327_REG_ARL_CTRL, |
||
1485 | |||
1486 | .hw_init = ar8327_hw_init, |
||
1487 | .cleanup = ar8327_cleanup, |
||
1488 | .init_globals = ar8327_init_globals, |
||
1489 | .init_port = ar8327_init_port, |
||
1490 | .setup_port = ar8327_setup_port, |
||
1491 | .read_port_status = ar8327_read_port_status, |
||
1492 | .read_port_eee_status = ar8327_read_port_eee_status, |
||
1493 | .atu_flush = ar8327_atu_flush, |
||
1494 | .atu_flush_port = ar8327_atu_flush_port, |
||
1495 | .vtu_flush = ar8327_vtu_flush, |
||
1496 | .vtu_load_vlan = ar8327_vtu_load_vlan, |
||
1497 | .phy_fixup = ar8327_phy_fixup, |
||
1498 | .set_mirror_regs = ar8327_set_mirror_regs, |
||
1499 | .get_arl_entry = ar8327_get_arl_entry, |
||
1500 | .sw_hw_apply = ar8327_sw_hw_apply, |
||
1501 | |||
1502 | .num_mibs = ARRAY_SIZE(ar8236_mibs), |
||
1503 | .mib_decs = ar8236_mibs, |
||
1504 | .mib_func = AR8327_REG_MIB_FUNC |
||
1505 | }; |
||
1506 | |||
1507 | const struct ar8xxx_chip ar8337_chip = { |
||
1508 | .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS, |
||
1509 | .config_at_probe = true, |
||
1510 | .mii_lo_first = true, |
||
1511 | |||
1512 | .name = "Atheros AR8337", |
||
1513 | .ports = AR8327_NUM_PORTS, |
||
1514 | .vlans = AR8X16_MAX_VLANS, |
||
1515 | .swops = &ar8327_sw_ops, |
||
1516 | |||
1517 | .reg_port_stats_start = 0x1000, |
||
1518 | .reg_port_stats_length = 0x100, |
||
1519 | .reg_arl_ctrl = AR8327_REG_ARL_CTRL, |
||
1520 | |||
1521 | .hw_init = ar8327_hw_init, |
||
1522 | .cleanup = ar8327_cleanup, |
||
1523 | .init_globals = ar8327_init_globals, |
||
1524 | .init_port = ar8327_init_port, |
||
1525 | .setup_port = ar8327_setup_port, |
||
1526 | .read_port_status = ar8327_read_port_status, |
||
1527 | .read_port_eee_status = ar8327_read_port_eee_status, |
||
1528 | .atu_flush = ar8327_atu_flush, |
||
1529 | .atu_flush_port = ar8327_atu_flush_port, |
||
1530 | .vtu_flush = ar8327_vtu_flush, |
||
1531 | .vtu_load_vlan = ar8327_vtu_load_vlan, |
||
1532 | .phy_fixup = ar8327_phy_fixup, |
||
1533 | .set_mirror_regs = ar8327_set_mirror_regs, |
||
1534 | .get_arl_entry = ar8327_get_arl_entry, |
||
1535 | .sw_hw_apply = ar8327_sw_hw_apply, |
||
1536 | .phy_rgmii_set = ar8327_phy_rgmii_set, |
||
1537 | |||
1538 | .num_mibs = ARRAY_SIZE(ar8236_mibs), |
||
1539 | .mib_decs = ar8236_mibs, |
||
1540 | .mib_func = AR8327_REG_MIB_FUNC |
||
1541 | }; |