OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/mach-cns3xxx/pcie.c |
2 | +++ b/arch/arm/mach-cns3xxx/pcie.c |
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3 | @@ -18,6 +18,7 @@ |
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4 | #include <linux/io.h> |
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5 | #include <linux/ioport.h> |
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6 | #include <linux/interrupt.h> |
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7 | +#include <linux/irq.h> |
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8 | #include <linux/ptrace.h> |
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9 | #include <asm/mach/map.h> |
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10 | #include "cns3xxx.h" |
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11 | @@ -27,7 +28,7 @@ struct cns3xxx_pcie { |
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12 | void __iomem *host_regs; /* PCI config registers for host bridge */ |
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13 | void __iomem *cfg0_regs; /* PCI Type 0 config registers */ |
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14 | void __iomem *cfg1_regs; /* PCI Type 1 config registers */ |
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15 | - unsigned int irqs[2]; |
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16 | + unsigned int irqs[5]; |
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17 | struct resource res_io; |
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18 | struct resource res_mem; |
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19 | int port; |
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20 | @@ -95,7 +96,7 @@ static inline int check_master_abort(str |
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21 | void __iomem *host_base; |
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22 | u32 sreg, ereg; |
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23 | |||
24 | - host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; |
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25 | + host_base = (void __iomem *) cnspci->host_regs; |
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26 | sreg = __raw_readw(host_base + 0x6) & 0xF900; |
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27 | ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg |
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28 | |||
29 | @@ -209,7 +210,7 @@ static struct pci_ops cns3xxx_pcie_ops = |
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30 | static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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31 | { |
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32 | struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); |
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33 | - int irq = cnspci->irqs[!!dev->bus->number]; |
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34 | + int irq = cnspci->irqs[!!dev->bus->number + pin - 1]; |
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35 | |||
36 | pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", |
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37 | pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), |
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38 | @@ -235,7 +236,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[ |
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39 | .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */ |
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40 | .flags = IORESOURCE_MEM, |
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41 | }, |
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42 | - .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, |
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43 | + .irqs = { |
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44 | + IRQ_CNS3XXX_PCIE0_RC, |
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45 | + IRQ_CNS3XXX_PCIE0_DEVICE, |
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46 | + IRQ_CNS3XXX_PCIE0_DEVICE, |
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47 | + IRQ_CNS3XXX_PCIE0_DEVICE, |
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48 | + IRQ_CNS3XXX_PCIE0_DEVICE, |
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49 | + }, |
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50 | .port = 0, |
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51 | }, |
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52 | [1] = { |
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53 | @@ -254,7 +261,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[ |
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54 | .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */ |
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55 | .flags = IORESOURCE_MEM, |
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56 | }, |
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57 | - .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, |
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58 | + .irqs = { |
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59 | + IRQ_CNS3XXX_PCIE1_RC, |
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60 | + IRQ_CNS3XXX_PCIE1_DEVICE, |
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61 | + IRQ_CNS3XXX_PCIE1_DEVICE, |
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62 | + IRQ_CNS3XXX_PCIE1_DEVICE, |
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63 | + IRQ_CNS3XXX_PCIE1_DEVICE, |
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64 | + }, |
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65 | .port = 1, |
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66 | }, |
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67 | }; |
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68 | @@ -346,6 +359,14 @@ static int cns3xxx_pcie_abort_handler(un |
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69 | return 0; |
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70 | } |
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71 | |||
72 | +void __init cns3xxx_pcie_set_irqs(int bus, int *irqs) |
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73 | +{ |
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74 | + int i; |
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75 | + |
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76 | + for (i = 0; i < 4; i++) |
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77 | + cns3xxx_pcie[bus].irqs[i + 1] = irqs[i]; |
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78 | +} |
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79 | + |
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80 | void __init cns3xxx_pcie_init_late(void) |
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81 | { |
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82 | int i; |
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83 | --- a/arch/arm/mach-cns3xxx/core.h |
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84 | +++ b/arch/arm/mach-cns3xxx/core.h |
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85 | @@ -18,8 +18,10 @@ extern void cns3xxx_timer_init(void); |
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86 | |||
87 | #ifdef CONFIG_PCI |
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88 | extern void __init cns3xxx_pcie_init_late(void); |
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89 | +extern void __init cns3xxx_pcie_set_irqs(int bus, int *irqs); |
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90 | #else |
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91 | static inline void __init cns3xxx_pcie_init_late(void) {} |
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92 | +static inline void cns3xxx_pcie_set_irqs(int bus, int *irqs) {} |
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93 | #endif |
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94 | |||
95 | void __init cns3xxx_map_io(void); |