OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Gateworks Corporation Laguna Platform |
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3 | * |
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4 | * Copyright 2000 Deep Blue Solutions Ltd |
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5 | * Copyright 2008 ARM Limited |
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6 | * Copyright 2008 Cavium Networks |
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7 | * Scott Shu |
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8 | * Copyright 2010 MontaVista Software, LLC. |
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9 | * Anton Vorontsov <avorontsov@mvista.com> |
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10 | * Copyright 2011 Gateworks Corporation |
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11 | * Chris Lang <clang@gateworks.com> |
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12 | * Copyright 2012-2013 Gateworks Corporation |
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13 | * Tim Harvey <tharvey@gateworks.com> |
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14 | * |
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15 | * This file is free software; you can redistribute it and/or modify |
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16 | * it under the terms of the GNU General Public License, Version 2, as |
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17 | * published by the Free Software Foundation. |
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18 | */ |
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19 | |||
20 | #include <linux/init.h> |
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21 | #include <linux/kernel.h> |
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22 | #include <linux/compiler.h> |
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23 | #include <linux/io.h> |
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24 | #include <linux/irq.h> |
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25 | #include <linux/gpio.h> |
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26 | #include <linux/dma-mapping.h> |
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27 | #include <linux/serial_core.h> |
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28 | #include <linux/serial_8250.h> |
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29 | #include <linux/platform_device.h> |
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30 | #include <linux/mtd/mtd.h> |
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31 | #include <linux/mtd/physmap.h> |
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32 | #include <linux/mtd/partitions.h> |
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33 | #include <linux/leds.h> |
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34 | #include <linux/i2c.h> |
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35 | #include <linux/platform_data/at24.h> |
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36 | #include <linux/platform_data/pca953x.h> |
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37 | #include <linux/spi/spi.h> |
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38 | #include <linux/spi/flash.h> |
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39 | #include <linux/if_ether.h> |
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40 | #include <linux/pps-gpio.h> |
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41 | #include <linux/usb/ehci_pdriver.h> |
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42 | #include <linux/usb/ohci_pdriver.h> |
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43 | #include <linux/clk-provider.h> |
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44 | #include <linux/clkdev.h> |
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45 | #include <linux/platform_data/cns3xxx.h> |
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46 | #include <asm/setup.h> |
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47 | #include <asm/mach-types.h> |
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48 | #include <asm/mach/arch.h> |
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49 | #include <asm/mach/map.h> |
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50 | #include <asm/mach/time.h> |
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51 | #include <mach/gpio.h> |
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52 | #include "core.h" |
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53 | #include "devices.h" |
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54 | #include "cns3xxx.h" |
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55 | #include "pm.h" |
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56 | |||
57 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) |
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58 | |||
59 | // Config 1 Bitmap |
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60 | #define ETH0_LOAD BIT(0) |
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61 | #define ETH1_LOAD BIT(1) |
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62 | #define ETH2_LOAD BIT(2) |
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63 | #define SATA0_LOAD BIT(3) |
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64 | #define SATA1_LOAD BIT(4) |
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65 | #define PCM_LOAD BIT(5) |
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66 | #define I2S_LOAD BIT(6) |
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67 | #define SPI0_LOAD BIT(7) |
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68 | #define SPI1_LOAD BIT(8) |
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69 | #define PCIE0_LOAD BIT(9) |
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70 | #define PCIE1_LOAD BIT(10) |
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71 | #define USB0_LOAD BIT(11) |
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72 | #define USB1_LOAD BIT(12) |
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73 | #define USB1_ROUTE BIT(13) |
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74 | #define SD_LOAD BIT(14) |
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75 | #define UART0_LOAD BIT(15) |
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76 | #define UART1_LOAD BIT(16) |
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77 | #define UART2_LOAD BIT(17) |
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78 | #define MPCI0_LOAD BIT(18) |
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79 | #define MPCI1_LOAD BIT(19) |
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80 | #define MPCI2_LOAD BIT(20) |
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81 | #define MPCI3_LOAD BIT(21) |
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82 | #define FP_BUT_LOAD BIT(22) |
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83 | #define FP_BUT_HEADER_LOAD BIT(23) |
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84 | #define FP_LED_LOAD BIT(24) |
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85 | #define FP_LED_HEADER_LOAD BIT(25) |
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86 | #define FP_TAMPER_LOAD BIT(26) |
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87 | #define HEADER_33V_LOAD BIT(27) |
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88 | #define SATA_POWER_LOAD BIT(28) |
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89 | #define FP_POWER_LOAD BIT(29) |
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90 | #define GPIO_HEADER_LOAD BIT(30) |
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91 | #define GSP_BAT_LOAD BIT(31) |
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92 | |||
93 | // Config 2 Bitmap |
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94 | #define FAN_LOAD BIT(0) |
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95 | #define SPI_FLASH_LOAD BIT(1) |
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96 | #define NOR_FLASH_LOAD BIT(2) |
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97 | #define GPS_LOAD BIT(3) |
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98 | #define SUPPLY_5V_LOAD BIT(6) |
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99 | #define SUPPLY_33V_LOAD BIT(7) |
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100 | |||
101 | struct laguna_board_info { |
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102 | char model[16]; |
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103 | u32 config_bitmap; |
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104 | u32 config2_bitmap; |
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105 | u8 nor_flash_size; |
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106 | u8 spi_flash_size; |
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107 | }; |
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108 | |||
109 | static struct laguna_board_info laguna_info __initdata; |
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110 | |||
111 | /* |
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112 | * NOR Flash |
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113 | */ |
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114 | static struct mtd_partition laguna_nor_partitions[] = { |
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115 | { |
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116 | .name = "uboot", |
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117 | .size = SZ_256K, |
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118 | .offset = 0, |
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119 | .mask_flags = MTD_WRITEABLE, |
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120 | }, { |
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121 | .name = "params", |
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122 | .size = SZ_128K, |
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123 | .offset = SZ_256K, |
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124 | }, { |
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125 | .name = "firmware", |
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126 | .offset = SZ_256K + SZ_128K, |
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127 | }, |
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128 | }; |
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129 | |||
130 | static struct physmap_flash_data laguna_nor_pdata = { |
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131 | .width = 2, |
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132 | .parts = laguna_nor_partitions, |
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133 | .nr_parts = ARRAY_SIZE(laguna_nor_partitions), |
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134 | }; |
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135 | |||
136 | static struct resource laguna_nor_res = { |
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137 | .start = CNS3XXX_FLASH_BASE, |
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138 | .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, |
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139 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, |
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140 | }; |
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141 | |||
142 | static struct platform_device laguna_nor_pdev = { |
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143 | .name = "physmap-flash", |
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144 | .id = 0, |
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145 | .resource = &laguna_nor_res, |
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146 | .num_resources = 1, |
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147 | .dev = { |
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148 | .platform_data = &laguna_nor_pdata, |
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149 | }, |
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150 | }; |
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151 | |||
152 | /* |
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153 | * SPI |
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154 | */ |
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155 | static struct mtd_partition laguna_spi_partitions[] = { |
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156 | { |
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157 | .name = "uboot", |
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158 | .size = SZ_256K, |
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159 | .offset = 0, |
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160 | .mask_flags = MTD_WRITEABLE, |
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161 | }, { |
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162 | .name = "params", |
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163 | .size = SZ_256K, |
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164 | .offset = SZ_256K, |
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165 | }, { |
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166 | .name = "firmware", |
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167 | .offset = SZ_512K, |
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168 | }, |
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169 | }; |
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170 | |||
171 | static struct flash_platform_data laguna_spi_pdata = { |
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172 | .parts = laguna_spi_partitions, |
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173 | .nr_parts = ARRAY_SIZE(laguna_spi_partitions), |
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174 | }; |
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175 | |||
176 | static struct spi_board_info __initdata laguna_spi_devices[] = { |
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177 | { |
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178 | .modalias = "m25p80", |
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179 | .platform_data = &laguna_spi_pdata, |
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180 | .max_speed_hz = 50000000, |
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181 | .bus_num = 1, |
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182 | .chip_select = 0, |
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183 | }, |
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184 | }; |
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185 | |||
186 | static struct resource laguna_spi_resource = { |
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187 | .start = CNS3XXX_SSP_BASE + 0x40, |
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188 | .end = CNS3XXX_SSP_BASE + 0x6f, |
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189 | .flags = IORESOURCE_MEM, |
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190 | }; |
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191 | |||
192 | static struct platform_device laguna_spi_controller = { |
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193 | .name = "cns3xxx_spi", |
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194 | .resource = &laguna_spi_resource, |
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195 | .num_resources = 1, |
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196 | }; |
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197 | |||
198 | /* |
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199 | * LED's |
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200 | */ |
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201 | static struct gpio_led laguna_gpio_leds[] = { |
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202 | { |
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203 | .name = "user1", /* Green Led */ |
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204 | .gpio = 115, |
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205 | .active_low = 1, |
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206 | },{ |
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207 | .name = "user2", /* Red Led */ |
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208 | .gpio = 114, |
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209 | .active_low = 1, |
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210 | },{ |
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211 | .name = "pwr1", /* Green Led */ |
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212 | .gpio = 116, |
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213 | .active_low = 1, |
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214 | },{ |
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215 | .name = "pwr2", /* Yellow Led */ |
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216 | .gpio = 117, |
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217 | .active_low = 1, |
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218 | },{ |
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219 | .name = "txd1", /* Green Led */ |
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220 | .gpio = 118, |
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221 | .active_low = 1, |
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222 | },{ |
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223 | .name = "txd2", /* Yellow Led */ |
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224 | .gpio = 119, |
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225 | .active_low = 1, |
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226 | },{ |
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227 | .name = "rxd1", /* Green Led */ |
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228 | .gpio = 120, |
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229 | .active_low = 1, |
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230 | },{ |
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231 | .name = "rxd2", /* Yellow Led */ |
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232 | .gpio = 121, |
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233 | .active_low = 1, |
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234 | },{ |
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235 | .name = "ser1", /* Green Led */ |
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236 | .gpio = 122, |
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237 | .active_low = 1, |
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238 | },{ |
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239 | .name = "ser2", /* Yellow Led */ |
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240 | .gpio = 123, |
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241 | .active_low = 1, |
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242 | },{ |
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243 | .name = "enet1", /* Green Led */ |
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244 | .gpio = 124, |
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245 | .active_low = 1, |
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246 | },{ |
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247 | .name = "enet2", /* Yellow Led */ |
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248 | .gpio = 125, |
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249 | .active_low = 1, |
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250 | },{ |
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251 | .name = "sig1_1", /* Green Led */ |
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252 | .gpio = 126, |
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253 | .active_low = 1, |
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254 | },{ |
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255 | .name = "sig1_2", /* Yellow Led */ |
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256 | .gpio = 127, |
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257 | .active_low = 1, |
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258 | },{ |
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259 | .name = "sig2_1", /* Green Led */ |
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260 | .gpio = 128, |
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261 | .active_low = 1, |
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262 | },{ |
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263 | .name = "sig2_2", /* Yellow Led */ |
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264 | .gpio = 129, |
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265 | .active_low = 1, |
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266 | },{ |
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267 | .name = "sig3_1", /* Green Led */ |
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268 | .gpio = 130, |
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269 | .active_low = 1, |
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270 | },{ |
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271 | .name = "sig3_2", /* Yellow Led */ |
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272 | .gpio = 131, |
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273 | .active_low = 1, |
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274 | },{ |
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275 | .name = "net1", /*Green Led */ |
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276 | .gpio = 109, |
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277 | .active_low = 1, |
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278 | },{ |
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279 | .name = "net2", /* Red Led */ |
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280 | .gpio = 110, |
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281 | .active_low = 1, |
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282 | },{ |
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283 | .name = "mod1", /* Green Led */ |
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284 | .gpio = 111, |
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285 | .active_low = 1, |
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286 | },{ |
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287 | .name = "mod2", /* Red Led */ |
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288 | .gpio = 112, |
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289 | .active_low = 1, |
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290 | }, |
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291 | }; |
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292 | |||
293 | static struct gpio_led_platform_data laguna_gpio_leds_data = { |
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294 | .num_leds = 22, |
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295 | .leds = laguna_gpio_leds, |
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296 | }; |
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297 | |||
298 | static struct platform_device laguna_gpio_leds_device = { |
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299 | .name = "leds-gpio", |
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300 | .id = PLATFORM_DEVID_NONE, |
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301 | .dev.platform_data = &laguna_gpio_leds_data, |
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302 | }; |
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303 | |||
304 | /* |
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305 | * Ethernet |
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306 | */ |
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307 | static struct cns3xxx_plat_info laguna_net_data = { |
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308 | .ports = 0, |
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309 | .phy = { |
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310 | 0, |
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311 | 1, |
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312 | 2, |
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313 | }, |
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314 | }; |
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315 | |||
316 | static struct resource laguna_net_resource[] = { |
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317 | { |
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318 | .name = "eth0_mem", |
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319 | .start = CNS3XXX_SWITCH_BASE, |
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320 | .end = CNS3XXX_SWITCH_BASE + SZ_4K - 1, |
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321 | .flags = IORESOURCE_MEM |
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322 | }, { |
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323 | .name = "eth_rx", |
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324 | .start = IRQ_CNS3XXX_SW_R0RXC, |
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325 | .end = IRQ_CNS3XXX_SW_R0RXC, |
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326 | .flags = IORESOURCE_IRQ |
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327 | }, { |
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328 | .name = "eth_stat", |
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329 | .start = IRQ_CNS3XXX_SW_STATUS, |
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330 | .end = IRQ_CNS3XXX_SW_STATUS, |
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331 | .flags = IORESOURCE_IRQ |
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332 | } |
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333 | }; |
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334 | |||
335 | static u64 laguna_net_dmamask = DMA_BIT_MASK(32); |
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336 | static struct platform_device laguna_net_device = { |
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337 | .name = "cns3xxx_eth", |
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338 | .id = 0, |
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339 | .resource = laguna_net_resource, |
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340 | .num_resources = ARRAY_SIZE(laguna_net_resource), |
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341 | .dev = { |
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342 | .dma_mask = &laguna_net_dmamask, |
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343 | .coherent_dma_mask = DMA_BIT_MASK(32), |
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344 | .platform_data = &laguna_net_data, |
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345 | } |
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346 | }; |
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347 | |||
348 | /* |
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349 | * UART |
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350 | */ |
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351 | static void __init laguna_early_serial_setup(void) |
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352 | { |
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353 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
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354 | static struct uart_port laguna_serial_port = { |
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355 | .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, |
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356 | .mapbase = CNS3XXX_UART0_BASE, |
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357 | .irq = IRQ_CNS3XXX_UART0, |
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358 | .iotype = UPIO_MEM, |
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359 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, |
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360 | .regshift = 2, |
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361 | .uartclk = 24000000, |
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362 | .line = 0, |
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363 | .type = PORT_16550A, |
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364 | .fifosize = 16, |
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365 | }; |
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366 | |||
367 | early_serial_setup(&laguna_serial_port); |
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368 | #endif |
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369 | } |
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370 | |||
371 | static struct resource laguna_uart_resources[] = { |
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372 | { |
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373 | .start = CNS3XXX_UART0_BASE, |
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374 | .end = CNS3XXX_UART0_BASE + SZ_4K - 1, |
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375 | .flags = IORESOURCE_MEM |
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376 | },{ |
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377 | .start = CNS3XXX_UART1_BASE, |
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378 | .end = CNS3XXX_UART1_BASE + SZ_4K - 1, |
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379 | .flags = IORESOURCE_MEM |
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380 | },{ |
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381 | .start = CNS3XXX_UART2_BASE, |
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382 | .end = CNS3XXX_UART2_BASE + SZ_4K - 1, |
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383 | .flags = IORESOURCE_MEM |
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384 | }, |
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385 | }; |
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386 | |||
387 | static struct plat_serial8250_port laguna_uart_data[] = { |
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388 | { |
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389 | .mapbase = (CNS3XXX_UART0_BASE), |
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390 | .irq = IRQ_CNS3XXX_UART0, |
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391 | .iotype = UPIO_MEM, |
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392 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP, |
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393 | .regshift = 2, |
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394 | .uartclk = 24000000, |
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395 | .type = PORT_16550A, |
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396 | },{ |
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397 | .mapbase = (CNS3XXX_UART1_BASE), |
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398 | .irq = IRQ_CNS3XXX_UART1, |
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399 | .iotype = UPIO_MEM, |
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400 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP, |
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401 | .regshift = 2, |
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402 | .uartclk = 24000000, |
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403 | .type = PORT_16550A, |
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404 | },{ |
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405 | .mapbase = (CNS3XXX_UART2_BASE), |
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406 | .irq = IRQ_CNS3XXX_UART2, |
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407 | .iotype = UPIO_MEM, |
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408 | .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_IOREMAP, |
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409 | .regshift = 2, |
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410 | .uartclk = 24000000, |
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411 | .type = PORT_16550A, |
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412 | }, |
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413 | { }, |
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414 | }; |
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415 | |||
416 | static struct platform_device laguna_uart = { |
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417 | .name = "serial8250", |
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418 | .id = PLAT8250_DEV_PLATFORM, |
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419 | .dev.platform_data = laguna_uart_data, |
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420 | .num_resources = 3, |
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421 | .resource = laguna_uart_resources |
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422 | }; |
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423 | |||
424 | /* |
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425 | * USB |
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426 | */ |
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427 | static struct resource cns3xxx_usb_ehci_resources[] = { |
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428 | [0] = { |
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429 | .start = CNS3XXX_USB_BASE, |
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430 | .end = CNS3XXX_USB_BASE + SZ_16M - 1, |
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431 | .flags = IORESOURCE_MEM, |
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432 | }, |
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433 | [1] = { |
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434 | .start = IRQ_CNS3XXX_USB_EHCI, |
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435 | .flags = IORESOURCE_IRQ, |
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436 | }, |
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437 | }; |
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438 | |||
439 | static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); |
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440 | |||
441 | static int csn3xxx_usb_power_on(struct platform_device *pdev) |
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442 | { |
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443 | /* |
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444 | * EHCI and OHCI share the same clock and power, |
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445 | * resetting twice would cause the 1st controller been reset. |
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446 | * Therefore only do power up at the first up device, and |
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447 | * power down at the last down device. |
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448 | * |
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449 | * Set USB AHB INCR length to 16 |
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450 | */ |
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451 | if (atomic_inc_return(&usb_pwr_ref) == 1) { |
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452 | cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); |
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453 | cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); |
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454 | cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); |
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455 | __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), |
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456 | MISC_CHIP_CONFIG_REG); |
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457 | } |
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458 | |||
459 | return 0; |
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460 | } |
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461 | |||
462 | static void csn3xxx_usb_power_off(struct platform_device *pdev) |
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463 | { |
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464 | /* |
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465 | * EHCI and OHCI share the same clock and power, |
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466 | * resetting twice would cause the 1st controller been reset. |
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467 | * Therefore only do power up at the first up device, and |
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468 | * power down at the last down device. |
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469 | */ |
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470 | if (atomic_dec_return(&usb_pwr_ref) == 0) |
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471 | cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); |
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472 | } |
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473 | |||
474 | static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { |
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475 | .power_on = csn3xxx_usb_power_on, |
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476 | .power_off = csn3xxx_usb_power_off, |
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477 | }; |
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478 | |||
479 | static struct platform_device cns3xxx_usb_ehci_device = { |
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480 | .name = "ehci-platform", |
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481 | .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), |
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482 | .resource = cns3xxx_usb_ehci_resources, |
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483 | .dev = { |
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484 | .dma_mask = &cns3xxx_usb_ehci_dma_mask, |
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485 | .coherent_dma_mask = DMA_BIT_MASK(32), |
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486 | .platform_data = &cns3xxx_usb_ehci_pdata, |
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487 | }, |
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488 | }; |
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489 | |||
490 | static struct resource cns3xxx_usb_ohci_resources[] = { |
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491 | [0] = { |
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492 | .start = CNS3XXX_USB_OHCI_BASE, |
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493 | .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, |
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494 | .flags = IORESOURCE_MEM, |
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495 | }, |
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496 | [1] = { |
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497 | .start = IRQ_CNS3XXX_USB_OHCI, |
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498 | .flags = IORESOURCE_IRQ, |
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499 | }, |
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500 | }; |
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501 | |||
502 | static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); |
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503 | |||
504 | static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { |
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505 | .num_ports = 1, |
||
506 | .power_on = csn3xxx_usb_power_on, |
||
507 | .power_off = csn3xxx_usb_power_off, |
||
508 | }; |
||
509 | |||
510 | static struct platform_device cns3xxx_usb_ohci_device = { |
||
511 | .name = "ohci-platform", |
||
512 | .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), |
||
513 | .resource = cns3xxx_usb_ohci_resources, |
||
514 | .dev = { |
||
515 | .dma_mask = &cns3xxx_usb_ohci_dma_mask, |
||
516 | .coherent_dma_mask = DMA_BIT_MASK(32), |
||
517 | .platform_data = &cns3xxx_usb_ohci_pdata, |
||
518 | }, |
||
519 | }; |
||
520 | |||
521 | static struct resource cns3xxx_usb_otg_resources[] = { |
||
522 | [0] = { |
||
523 | .start = CNS3XXX_USBOTG_BASE, |
||
524 | .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1, |
||
525 | .flags = IORESOURCE_MEM, |
||
526 | }, |
||
527 | [1] = { |
||
528 | .start = IRQ_CNS3XXX_USB_OTG, |
||
529 | .flags = IORESOURCE_IRQ, |
||
530 | }, |
||
531 | }; |
||
532 | |||
533 | static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32); |
||
534 | |||
535 | static struct platform_device cns3xxx_usb_otg_device = { |
||
536 | .name = "dwc2", |
||
537 | .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources), |
||
538 | .resource = cns3xxx_usb_otg_resources, |
||
539 | .dev = { |
||
540 | .dma_mask = &cns3xxx_usb_otg_dma_mask, |
||
541 | .coherent_dma_mask = DMA_BIT_MASK(32), |
||
542 | }, |
||
543 | }; |
||
544 | |||
545 | /* |
||
546 | * I2C |
||
547 | */ |
||
548 | static struct resource laguna_i2c_resource[] = { |
||
549 | { |
||
550 | .start = CNS3XXX_SSP_BASE + 0x20, |
||
551 | .end = CNS3XXX_SSP_BASE + 0x3f, |
||
552 | .flags = IORESOURCE_MEM, |
||
553 | },{ |
||
554 | .start = IRQ_CNS3XXX_I2C, |
||
555 | .flags = IORESOURCE_IRQ, |
||
556 | }, |
||
557 | }; |
||
558 | |||
559 | static struct platform_device laguna_i2c_controller = { |
||
560 | .name = "cns3xxx-i2c", |
||
561 | .num_resources = 2, |
||
562 | .resource = laguna_i2c_resource, |
||
563 | }; |
||
564 | |||
565 | static struct nvmem_device *at24_nvmem; |
||
566 | |||
567 | static void at24_setup(struct nvmem_device *mem_acc, void *context) |
||
568 | { |
||
569 | char buf[16]; |
||
570 | |||
571 | at24_nvmem = mem_acc; |
||
572 | |||
573 | /* Read MAC addresses */ |
||
574 | if (nvmem_device_read(at24_nvmem, 0x100, 6, buf) == 6) |
||
575 | memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN); |
||
576 | if (nvmem_device_read(at24_nvmem, 0x106, 6, buf) == 6) |
||
577 | memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN); |
||
578 | if (nvmem_device_read(at24_nvmem, 0x10C, 6, buf) == 6) |
||
579 | memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN); |
||
580 | if (nvmem_device_read(at24_nvmem, 0x112, 6, buf) == 6) |
||
581 | memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN); |
||
582 | |||
583 | /* Read out Model Information */ |
||
584 | if (nvmem_device_read(at24_nvmem, 0x130, 16, buf) == 16) |
||
585 | memcpy(&laguna_info.model, buf, 16); |
||
586 | if (nvmem_device_read(at24_nvmem, 0x140, 1, buf) == 1) |
||
587 | memcpy(&laguna_info.nor_flash_size, buf, 1); |
||
588 | if (nvmem_device_read(at24_nvmem, 0x141, 1, buf) == 1) |
||
589 | memcpy(&laguna_info.spi_flash_size, buf, 1); |
||
590 | if (nvmem_device_read(at24_nvmem, 0x142, 4, buf) == 4) |
||
591 | memcpy(&laguna_info.config_bitmap, buf, 4); |
||
592 | if (nvmem_device_read(at24_nvmem, 0x146, 4, buf) == 4) |
||
593 | memcpy(&laguna_info.config2_bitmap, buf, 4); |
||
594 | }; |
||
595 | |||
596 | static struct at24_platform_data laguna_eeprom_info = { |
||
597 | .byte_len = 1024, |
||
598 | .page_size = 16, |
||
599 | .flags = AT24_FLAG_READONLY, |
||
600 | .setup = at24_setup, |
||
601 | }; |
||
602 | |||
603 | static struct pca953x_platform_data laguna_pca_data = { |
||
604 | .gpio_base = 100, |
||
605 | .irq_base = -1, |
||
606 | }; |
||
607 | |||
608 | static struct pca953x_platform_data laguna_pca2_data = { |
||
609 | .gpio_base = 116, |
||
610 | .irq_base = -1, |
||
611 | }; |
||
612 | |||
613 | static struct i2c_board_info __initdata laguna_i2c_devices[] = { |
||
614 | { |
||
615 | I2C_BOARD_INFO("pca9555", 0x23), |
||
616 | .platform_data = &laguna_pca_data, |
||
617 | },{ |
||
618 | I2C_BOARD_INFO("pca9555", 0x27), |
||
619 | .platform_data = &laguna_pca2_data, |
||
620 | },{ |
||
621 | I2C_BOARD_INFO("gsp", 0x29), |
||
622 | },{ |
||
623 | I2C_BOARD_INFO ("24c08",0x50), |
||
624 | .platform_data = &laguna_eeprom_info, |
||
625 | },{ |
||
626 | I2C_BOARD_INFO("ds1672", 0x68), |
||
627 | }, |
||
628 | }; |
||
629 | |||
630 | /* |
||
631 | * Watchdog |
||
632 | */ |
||
633 | |||
634 | static struct resource laguna_watchdog_resources[] = { |
||
635 | [0] = { |
||
636 | .start = CNS3XXX_TC11MP_TWD_BASE + 0x100, // CPU0 watchdog |
||
637 | .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1, |
||
638 | .flags = IORESOURCE_MEM, |
||
639 | }, |
||
640 | }; |
||
641 | |||
642 | static struct platform_device laguna_watchdog = { |
||
643 | .name = "mpcore_wdt", |
||
644 | .id = PLATFORM_DEVID_NONE, |
||
645 | .num_resources = ARRAY_SIZE(laguna_watchdog_resources), |
||
646 | .resource = laguna_watchdog_resources, |
||
647 | }; |
||
648 | |||
649 | /* |
||
650 | * GPS PPS |
||
651 | */ |
||
652 | static struct pps_gpio_platform_data laguna_pps_data = { |
||
653 | .gpio_pin = 0, |
||
654 | .gpio_label = "GPS_PPS", |
||
655 | .assert_falling_edge = 0, |
||
656 | .capture_clear = 0, |
||
657 | }; |
||
658 | |||
659 | static struct platform_device laguna_pps_device = { |
||
660 | .name = "pps-gpio", |
||
661 | .id = PLATFORM_DEVID_NONE, |
||
662 | .dev.platform_data = &laguna_pps_data, |
||
663 | }; |
||
664 | |||
665 | /* |
||
666 | * GPIO |
||
667 | */ |
||
668 | |||
669 | static struct gpio laguna_gpio_gw2391[] = { |
||
670 | { 0, GPIOF_IN , "*GPS_PPS" }, |
||
671 | { 1, GPIOF_IN , "*GSC_IRQ#" }, |
||
672 | { 2, GPIOF_IN , "*USB_FAULT#" }, |
||
673 | { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" }, |
||
674 | { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, |
||
675 | { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" }, |
||
676 | { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" }, |
||
677 | { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" }, |
||
678 | { 100, GPIOF_IN , "*USER_PB#" }, |
||
679 | { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" }, |
||
680 | { 108, GPIOF_IN , "DIO0" }, |
||
681 | { 109, GPIOF_IN , "DIO1" }, |
||
682 | { 110, GPIOF_IN , "DIO2" }, |
||
683 | { 111, GPIOF_IN , "DIO3" }, |
||
684 | { 112, GPIOF_IN , "DIO4" }, |
||
685 | }; |
||
686 | |||
687 | static struct gpio laguna_gpio_gw2388[] = { |
||
688 | { 0, GPIOF_IN , "*GPS_PPS" }, |
||
689 | { 1, GPIOF_IN , "*GSC_IRQ#" }, |
||
690 | { 3, GPIOF_IN , "*USB_FAULT#" }, |
||
691 | { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, |
||
692 | { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, |
||
693 | { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, |
||
694 | { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, |
||
695 | { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" }, |
||
696 | { 108, GPIOF_IN , "DIO0" }, |
||
697 | { 109, GPIOF_IN , "DIO1" }, |
||
698 | { 110, GPIOF_IN , "DIO2" }, |
||
699 | { 111, GPIOF_IN , "DIO3" }, |
||
700 | { 112, GPIOF_IN , "DIO4" }, |
||
701 | }; |
||
702 | |||
703 | static struct gpio laguna_gpio_gw2387[] = { |
||
704 | { 0, GPIOF_IN , "*GPS_PPS" }, |
||
705 | { 1, GPIOF_IN , "*GSC_IRQ#" }, |
||
706 | { 2, GPIOF_IN , "*USB_FAULT#" }, |
||
707 | { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" }, |
||
708 | { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, |
||
709 | { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, |
||
710 | { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, |
||
711 | { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, |
||
712 | { 100, GPIOF_IN , "*USER_PB#" }, |
||
713 | { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" }, |
||
714 | { 108, GPIOF_IN , "DIO0" }, |
||
715 | { 109, GPIOF_IN , "DIO1" }, |
||
716 | { 110, GPIOF_IN , "DIO2" }, |
||
717 | { 111, GPIOF_IN , "DIO3" }, |
||
718 | { 112, GPIOF_IN , "DIO4" }, |
||
719 | { 113, GPIOF_IN , "DIO5" }, |
||
720 | }; |
||
721 | |||
722 | static struct gpio laguna_gpio_gw2386[] = { |
||
723 | { 0, GPIOF_IN , "*GPS_PPS" }, |
||
724 | { 2, GPIOF_IN , "*USB_FAULT#" }, |
||
725 | { 6, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" }, |
||
726 | { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, |
||
727 | { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, |
||
728 | { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, |
||
729 | { 108, GPIOF_IN , "DIO0" }, |
||
730 | { 109, GPIOF_IN , "DIO1" }, |
||
731 | { 110, GPIOF_IN , "DIO2" }, |
||
732 | { 111, GPIOF_IN , "DIO3" }, |
||
733 | { 112, GPIOF_IN , "DIO4" }, |
||
734 | { 113, GPIOF_IN , "DIO5" }, |
||
735 | }; |
||
736 | |||
737 | static struct gpio laguna_gpio_gw2385[] = { |
||
738 | { 0, GPIOF_IN , "*GSC_IRQ#" }, |
||
739 | { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" }, |
||
740 | { 2, GPIOF_IN , "*USB_HST_FAULT#" }, |
||
741 | { 5, GPIOF_IN , "*USB_OTG_FAULT#" }, |
||
742 | { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" }, |
||
743 | { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, |
||
744 | { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, |
||
745 | { 9, GPIOF_OUT_INIT_LOW , "*SER_EN" }, |
||
746 | { 10, GPIOF_IN, "*USER_PB#" }, |
||
747 | { 11, GPIOF_OUT_INIT_HIGH, "*PERST#" }, |
||
748 | { 100, GPIOF_IN , "*USER_PB#" }, |
||
749 | { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" }, |
||
750 | }; |
||
751 | |||
752 | static struct gpio laguna_gpio_gw2384[] = { |
||
753 | { 0, GPIOF_IN , "*GSC_IRQ#" }, |
||
754 | { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" }, |
||
755 | { 2, GPIOF_IN , "*USB_HST_FAULT#" }, |
||
756 | { 5, GPIOF_IN , "*USB_OTG_FAULT#" }, |
||
757 | { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" }, |
||
758 | { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" }, |
||
759 | { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" }, |
||
760 | { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" }, |
||
761 | { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" }, |
||
762 | { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" }, |
||
763 | { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" }, |
||
764 | { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" }, |
||
765 | { 100, GPIOF_IN , "*USER_PB#" }, |
||
766 | { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" }, |
||
767 | { 108, GPIOF_IN , "J9_DIOGSC0" }, |
||
768 | }; |
||
769 | |||
770 | static struct gpio laguna_gpio_gw2383[] = { |
||
771 | { 0, GPIOF_IN , "*GPS_PPS" }, |
||
772 | { 1, GPIOF_IN , "*GSC_IRQ#" }, |
||
773 | { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" }, |
||
774 | { 3, GPIOF_IN , "GPIO0" }, |
||
775 | { 8, GPIOF_IN , "GPIO1" }, |
||
776 | { 100, GPIOF_IN , "DIO0" }, |
||
777 | { 101, GPIOF_IN , "DIO1" }, |
||
778 | { 108, GPIOF_IN , "*USER_PB#" }, |
||
779 | }; |
||
780 | |||
781 | static struct gpio laguna_gpio_gw2382[] = { |
||
782 | { 0, GPIOF_IN , "*GPS_PPS" }, |
||
783 | { 1, GPIOF_IN , "*GSC_IRQ#" }, |
||
784 | { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" }, |
||
785 | { 3, GPIOF_IN , "GPIO0" }, |
||
786 | { 4, GPIOF_IN , "GPIO1" }, |
||
787 | { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" }, |
||
788 | { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" }, |
||
789 | { 100, GPIOF_IN , "DIO0" }, |
||
790 | { 101, GPIOF_IN , "DIO1" }, |
||
791 | { 108, GPIOF_IN , "*USER_PB#" }, |
||
792 | }; |
||
793 | |||
794 | static struct gpio laguna_gpio_gw2380[] = { |
||
795 | { 0, GPIOF_IN , "*GPS_PPS" }, |
||
796 | { 1, GPIOF_IN , "*GSC_IRQ#" }, |
||
797 | { 3, GPIOF_IN , "GPIO0" }, |
||
798 | { 8, GPIOF_IN , "GPIO1" }, |
||
799 | { 100, GPIOF_IN , "DIO0" }, |
||
800 | { 101, GPIOF_IN , "DIO1" }, |
||
801 | { 102, GPIOF_IN , "DIO2" }, |
||
802 | { 103, GPIOF_IN , "DIO3" }, |
||
803 | { 108, GPIOF_IN , "*USER_PB#" }, |
||
804 | }; |
||
805 | |||
806 | /* |
||
807 | * Initialization |
||
808 | */ |
||
809 | static void __init laguna_init(void) |
||
810 | { |
||
811 | struct clk *clk; |
||
812 | u32 __iomem *reg; |
||
813 | |||
814 | clk = clk_register_fixed_rate(NULL, "cpu", NULL, |
||
815 | CLK_IGNORE_UNUSED, |
||
816 | cns3xxx_cpu_clock() * (1000000 / 8)); |
||
817 | clk_register_clkdev(clk, "cpu", NULL); |
||
818 | |||
819 | platform_device_register(&laguna_watchdog); |
||
820 | |||
821 | platform_device_register(&laguna_i2c_controller); |
||
822 | |||
823 | /* Set I2C 0-3 drive strength to 21 mA */ |
||
824 | reg = MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B; |
||
825 | *reg |= 0x300; |
||
826 | |||
827 | /* Enable SCL/SDA for I2C */ |
||
828 | reg = MISC_GPIOB_PIN_ENABLE_REG; |
||
829 | *reg |= BIT(12) | BIT(13); |
||
830 | |||
831 | /* Enable MMC/SD pins */ |
||
832 | *reg |= BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11); |
||
833 | |||
834 | cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); |
||
835 | cns3xxx_pwr_power_up(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); |
||
836 | cns3xxx_pwr_soft_rst(1 << PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C); |
||
837 | |||
838 | cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C)); |
||
839 | cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C)); |
||
840 | |||
841 | i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices)); |
||
842 | |||
843 | pm_power_off = cns3xxx_power_off; |
||
844 | } |
||
845 | |||
846 | static struct map_desc laguna_io_desc[] __initdata = { |
||
847 | { |
||
848 | .virtual = CNS3XXX_UART0_BASE_VIRT, |
||
849 | .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), |
||
850 | .length = SZ_4K, |
||
851 | .type = MT_DEVICE, |
||
852 | }, |
||
853 | }; |
||
854 | |||
855 | static void __init laguna_map_io(void) |
||
856 | { |
||
857 | cns3xxx_map_io(); |
||
858 | iotable_init(ARRAY_AND_SIZE(laguna_io_desc)); |
||
859 | laguna_early_serial_setup(); |
||
860 | } |
||
861 | |||
862 | static int laguna_register_gpio(struct gpio *array, size_t num) |
||
863 | { |
||
864 | int i, err, ret; |
||
865 | |||
866 | ret = 0; |
||
867 | for (i = 0; i < num; i++, array++) { |
||
868 | const char *label = array->label; |
||
869 | if (label[0] == '*') |
||
870 | label++; |
||
871 | err = gpio_request_one(array->gpio, array->flags, label); |
||
872 | if (err) |
||
873 | ret = err; |
||
874 | else { |
||
875 | err = gpio_export(array->gpio, array->label[0] != '*'); |
||
876 | } |
||
877 | } |
||
878 | return ret; |
||
879 | } |
||
880 | |||
881 | /* allow disabling of external isolated PCIe IRQs */ |
||
882 | static int cns3xxx_pciextirq = 1; |
||
883 | static int __init cns3xxx_pciextirq_disable(char *s) |
||
884 | { |
||
885 | cns3xxx_pciextirq = 0; |
||
886 | return 1; |
||
887 | } |
||
888 | __setup("noextirq", cns3xxx_pciextirq_disable); |
||
889 | |||
890 | static int __init laguna_pcie_init_irq(void) |
||
891 | { |
||
892 | u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004); |
||
893 | u32 reg = (__raw_readl(mem) >> 26) & 0xf; |
||
894 | int irqs[] = { |
||
895 | IRQ_CNS3XXX_EXTERNAL_PIN0, |
||
896 | IRQ_CNS3XXX_EXTERNAL_PIN1, |
||
897 | IRQ_CNS3XXX_EXTERNAL_PIN2, |
||
898 | 154, |
||
899 | }; |
||
900 | |||
901 | if (!machine_is_gw2388()) |
||
902 | return 0; |
||
903 | |||
904 | /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */ |
||
905 | if (cns3xxx_pciextirq && reg != 1) |
||
906 | cns3xxx_pciextirq = 0; |
||
907 | |||
908 | if (cns3xxx_pciextirq) { |
||
909 | printk("laguna: using isolated PCI interrupts:" |
||
910 | " irq%d/irq%d/irq%d/irq%d\n", |
||
911 | irqs[0], irqs[1], irqs[2], irqs[3]); |
||
912 | cns3xxx_pcie_set_irqs(0, irqs); |
||
913 | } else { |
||
914 | printk("laguna: using shared PCI interrupts: irq%d\n", |
||
915 | IRQ_CNS3XXX_PCIE0_DEVICE); |
||
916 | } |
||
917 | |||
918 | return 0; |
||
919 | } |
||
920 | subsys_initcall(laguna_pcie_init_irq); |
||
921 | |||
922 | static int __init laguna_model_setup(void) |
||
923 | { |
||
924 | u32 __iomem *mem; |
||
925 | u32 reg; |
||
926 | |||
927 | if (!machine_is_gw2388()) |
||
928 | return 0; |
||
929 | |||
930 | printk("Running on Gateworks Laguna %s\n", laguna_info.model); |
||
931 | cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA, |
||
932 | NR_IRQS_CNS3XXX); |
||
933 | |||
934 | /* |
||
935 | * If pcie external interrupts are supported and desired |
||
936 | * configure IRQ types and configure pin function. |
||
937 | * Note that cns3xxx_pciextirq is enabled by default, but can be |
||
938 | * unset via the 'noextirq' kernel param or by laguna_pcie_init() if |
||
939 | * the baseboard model does not support this hardware feature. |
||
940 | */ |
||
941 | if (cns3xxx_pciextirq) { |
||
942 | mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018); |
||
943 | reg = __raw_readl(mem); |
||
944 | /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */ |
||
945 | reg &= ~0x3c000000; |
||
946 | reg |= 0x38000000; |
||
947 | __raw_writel(reg, mem); |
||
948 | |||
949 | cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, |
||
950 | IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); |
||
951 | |||
952 | irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW); |
||
953 | irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH); |
||
954 | irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH); |
||
955 | irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH); |
||
956 | } else { |
||
957 | cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, |
||
958 | IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32); |
||
959 | } |
||
960 | |||
961 | if (strncmp(laguna_info.model, "GW", 2) == 0) { |
||
962 | if (laguna_info.config_bitmap & ETH0_LOAD) |
||
963 | laguna_net_data.ports |= BIT(0); |
||
964 | if (laguna_info.config_bitmap & ETH1_LOAD) |
||
965 | laguna_net_data.ports |= BIT(1); |
||
966 | if (laguna_info.config_bitmap & ETH2_LOAD) |
||
967 | laguna_net_data.ports |= BIT(2); |
||
968 | if (laguna_net_data.ports) |
||
969 | platform_device_register(&laguna_net_device); |
||
970 | |||
971 | if ((laguna_info.config_bitmap & SATA0_LOAD) || |
||
972 | (laguna_info.config_bitmap & SATA1_LOAD)) |
||
973 | cns3xxx_ahci_init(); |
||
974 | |||
975 | if (laguna_info.config_bitmap & (USB0_LOAD)) { |
||
976 | cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); |
||
977 | |||
978 | /* DRVVBUS pins share with GPIOA */ |
||
979 | mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014); |
||
980 | reg = __raw_readl(mem); |
||
981 | reg |= 0x8; |
||
982 | __raw_writel(reg, mem); |
||
983 | |||
984 | /* Enable OTG */ |
||
985 | mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808); |
||
986 | reg = __raw_readl(mem); |
||
987 | reg &= ~(1 << 10); |
||
988 | __raw_writel(reg, mem); |
||
989 | |||
990 | platform_device_register(&cns3xxx_usb_otg_device); |
||
991 | } |
||
992 | |||
993 | if (laguna_info.config_bitmap & (USB1_LOAD)) { |
||
994 | platform_device_register(&cns3xxx_usb_ehci_device); |
||
995 | platform_device_register(&cns3xxx_usb_ohci_device); |
||
996 | } |
||
997 | |||
998 | if (laguna_info.config_bitmap & (SD_LOAD)) |
||
999 | cns3xxx_sdhci_init(); |
||
1000 | |||
1001 | if (laguna_info.config_bitmap & (UART0_LOAD)) |
||
1002 | laguna_uart.num_resources = 1; |
||
1003 | if (laguna_info.config_bitmap & (UART1_LOAD)) |
||
1004 | laguna_uart.num_resources = 2; |
||
1005 | if (laguna_info.config_bitmap & (UART2_LOAD)) |
||
1006 | laguna_uart.num_resources = 3; |
||
1007 | platform_device_register(&laguna_uart); |
||
1008 | |||
1009 | if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) { |
||
1010 | laguna_nor_partitions[2].size = |
||
1011 | (SZ_4M << laguna_info.nor_flash_size) - |
||
1012 | laguna_nor_partitions[2].offset; |
||
1013 | laguna_nor_res.end = CNS3XXX_FLASH_BASE + |
||
1014 | laguna_nor_partitions[2].offset + |
||
1015 | laguna_nor_partitions[2].size - 1; |
||
1016 | platform_device_register(&laguna_nor_pdev); |
||
1017 | } |
||
1018 | |||
1019 | if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) { |
||
1020 | laguna_spi_partitions[2].size = |
||
1021 | (SZ_2M << laguna_info.spi_flash_size) - |
||
1022 | laguna_spi_partitions[2].offset; |
||
1023 | spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices)); |
||
1024 | } |
||
1025 | |||
1026 | if ((laguna_info.config_bitmap & SPI0_LOAD) || |
||
1027 | (laguna_info.config_bitmap & SPI1_LOAD)) |
||
1028 | platform_device_register(&laguna_spi_controller); |
||
1029 | |||
1030 | if (laguna_info.config2_bitmap & GPS_LOAD) |
||
1031 | platform_device_register(&laguna_pps_device); |
||
1032 | |||
1033 | /* |
||
1034 | * Do any model specific setup not known by the bitmap by matching |
||
1035 | * the first 6 characters of the model name |
||
1036 | */ |
||
1037 | |||
1038 | if ( (strncmp(laguna_info.model, "GW2388", 6) == 0) |
||
1039 | || (strncmp(laguna_info.model, "GW2389", 6) == 0) ) |
||
1040 | { |
||
1041 | // configure GPIO's |
||
1042 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388)); |
||
1043 | // configure LED's |
||
1044 | laguna_gpio_leds_data.num_leds = 2; |
||
1045 | } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) { |
||
1046 | // configure GPIO's |
||
1047 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387)); |
||
1048 | // configure LED's |
||
1049 | laguna_gpio_leds_data.num_leds = 2; |
||
1050 | } else if (strncmp(laguna_info.model, "GW2386", 6) == 0) { |
||
1051 | // configure GPIO's |
||
1052 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2386)); |
||
1053 | // configure LED's |
||
1054 | laguna_gpio_leds_data.num_leds = 2; |
||
1055 | } else if (strncmp(laguna_info.model, "GW2385", 6) == 0) { |
||
1056 | // configure GPIO's |
||
1057 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2385)); |
||
1058 | // configure LED's |
||
1059 | laguna_gpio_leds[0].gpio = 115; |
||
1060 | laguna_gpio_leds[1].gpio = 12; |
||
1061 | laguna_gpio_leds[1].name = "red"; |
||
1062 | laguna_gpio_leds[1].active_low = 0, |
||
1063 | laguna_gpio_leds[2].gpio = 14; |
||
1064 | laguna_gpio_leds[2].name = "green"; |
||
1065 | laguna_gpio_leds[2].active_low = 0, |
||
1066 | laguna_gpio_leds[3].gpio = 15; |
||
1067 | laguna_gpio_leds[3].name = "blue"; |
||
1068 | laguna_gpio_leds[3].active_low = 0, |
||
1069 | laguna_gpio_leds_data.num_leds = 4; |
||
1070 | } else if ( (strncmp(laguna_info.model, "GW2384", 6) == 0) |
||
1071 | || (strncmp(laguna_info.model, "GW2394", 6) == 0) ) |
||
1072 | { |
||
1073 | // configure GPIO's |
||
1074 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384)); |
||
1075 | // configure LED's |
||
1076 | laguna_gpio_leds_data.num_leds = 1; |
||
1077 | } else if (strncmp(laguna_info.model, "GW2383", 6) == 0) { |
||
1078 | // configure GPIO's |
||
1079 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2383)); |
||
1080 | // configure LED's |
||
1081 | laguna_gpio_leds[0].gpio = 107; |
||
1082 | laguna_gpio_leds_data.num_leds = 1; |
||
1083 | } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) { |
||
1084 | // configure GPIO's |
||
1085 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382)); |
||
1086 | // configure LED's |
||
1087 | laguna_gpio_leds[0].gpio = 107; |
||
1088 | laguna_gpio_leds_data.num_leds = 1; |
||
1089 | } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) { |
||
1090 | // configure GPIO's |
||
1091 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380)); |
||
1092 | // configure LED's |
||
1093 | laguna_gpio_leds[0].gpio = 107; |
||
1094 | laguna_gpio_leds[1].gpio = 106; |
||
1095 | laguna_gpio_leds_data.num_leds = 2; |
||
1096 | } else if ( (strncmp(laguna_info.model, "GW2391", 6) == 0) |
||
1097 | || (strncmp(laguna_info.model, "GW2393", 6) == 0) ) |
||
1098 | { |
||
1099 | // configure GPIO's |
||
1100 | laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391)); |
||
1101 | // configure LED's |
||
1102 | laguna_gpio_leds_data.num_leds = 2; |
||
1103 | } |
||
1104 | platform_device_register(&laguna_gpio_leds_device); |
||
1105 | } else { |
||
1106 | // Do some defaults here, not sure what yet |
||
1107 | } |
||
1108 | return 0; |
||
1109 | } |
||
1110 | late_initcall(laguna_model_setup); |
||
1111 | |||
1112 | MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform") |
||
1113 | .smp = smp_ops(cns3xxx_smp_ops), |
||
1114 | .atag_offset = 0x100, |
||
1115 | .map_io = laguna_map_io, |
||
1116 | .init_irq = cns3xxx_init_irq, |
||
1117 | .init_time = cns3xxx_timer_init, |
||
1118 | .init_machine = laguna_init, |
||
1119 | .init_late = cns3xxx_pcie_init_late, |
||
1120 | .restart = cns3xxx_restart, |
||
1121 | MACHINE_END |