OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Sun, 15 Jul 2012 20:08:57 +0200 |
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4 | Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports |
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5 | |||
6 | --- |
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7 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +++++++++++++ |
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8 | drivers/net/ethernet/broadcom/bcm63xx_enet.c | 12 ++++++++++++ |
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9 | 2 files changed, 25 insertions(+), 0 deletions(-) |
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10 | |||
11 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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12 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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13 | @@ -967,6 +967,19 @@ |
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14 | #define ENETSW_PORTOV_FDX_MASK (1 << 1) |
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15 | #define ENETSW_PORTOV_LINKUP_MASK (1 << 0) |
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16 | |||
17 | +/* Port RGMII control register */ |
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18 | +#define ENETSW_RGMII_CTRL_REG(x) (0x60 + (x)) |
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19 | +#define ENETSW_RGMII_CTRL_GMII_CLK_EN (1 << 7) |
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20 | +#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6) |
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21 | +#define ENETSW_RGMII_CTRL_MII_MODE_MASK (3 << 4) |
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22 | +#define ENETSW_RGMII_CTRL_RGMII_MODE (0 << 4) |
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23 | +#define ENETSW_RGMII_CTRL_MII_MODE (1 << 4) |
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24 | +#define ENETSW_RGMII_CTRL_RVMII_MODE (2 << 4) |
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25 | +#define ENETSW_RGMII_CTRL_TIMING_SEL_EN (1 << 0) |
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26 | + |
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27 | +/* Port RGMII timing register */ |
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28 | +#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x)) |
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29 | + |
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30 | /* MDIO control register */ |
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31 | #define ENETSW_MDIOC_REG (0xb0) |
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32 | #define ENETSW_MDIOC_EXT_MASK (1 << 16) |
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33 | --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c |
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34 | +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c |
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35 | @@ -2205,6 +2205,18 @@ static int bcm_enetsw_open(struct net_de |
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36 | priv->sw_port_link[i] = 0; |
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37 | } |
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38 | |||
39 | + /* enable external ports */ |
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40 | + for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) { |
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41 | + u8 rgmii_ctrl; |
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42 | + |
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43 | + if (!priv->used_ports[i].used) |
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44 | + continue; |
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45 | + |
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46 | + rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i)); |
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47 | + rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN; |
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48 | + enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i)); |
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49 | + } |
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50 | + |
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51 | /* reset mib */ |
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52 | val = enetsw_readb(priv, ENETSW_GMCR_REG); |
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53 | val |= ENETSW_GMCR_RST_MIB_MASK; |