OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From cad8f63047c0691e8185d3c9c6a2705b83310c9c Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Mon, 31 Jul 2017 20:10:36 +0200 |
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4 | Subject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree |
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5 | |||
6 | --- |
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7 | arch/mips/bcm63xx/clk.c | 15 +++++++++++++++ |
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8 | 1 file changed, 15 insertions(+) |
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9 | |||
10 | --- a/arch/mips/bcm63xx/clk.c |
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11 | +++ b/arch/mips/bcm63xx/clk.c |
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12 | @@ -488,6 +488,8 @@ static struct clk_lookup bcm3368_clks[] |
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13 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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14 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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15 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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16 | + CLKDEV_INIT("fff8c100.serial", "refclk", &clk_periph), |
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17 | + CLKDEV_INIT("fff8c120.serial", "refclk", &clk_periph), |
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18 | /* gated clocks */ |
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19 | CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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20 | CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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21 | @@ -504,7 +506,9 @@ static struct clk_lookup bcm6318_clks[] |
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22 | /* fixed rate clocks */ |
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23 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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24 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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25 | + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph), |
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26 | CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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27 | + CLKDEV_INIT("10003000.spi", "pll", &clk_hsspi_pll), |
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28 | /* gated clocks */ |
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29 | CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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30 | CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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31 | @@ -518,7 +522,10 @@ static struct clk_lookup bcm6328_clks[] |
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32 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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33 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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34 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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35 | + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph), |
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36 | + CLKDEV_INIT("10000120.serial", "refclk", &clk_periph), |
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37 | CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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38 | + CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll), |
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39 | /* gated clocks */ |
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40 | CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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41 | CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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42 | @@ -531,6 +538,7 @@ static struct clk_lookup bcm6338_clks[] |
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43 | /* fixed rate clocks */ |
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44 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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45 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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46 | + CLKDEV_INIT("fffe0300.serial", "refclk", &clk_periph), |
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47 | /* gated clocks */ |
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48 | CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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49 | CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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50 | @@ -545,6 +553,7 @@ static struct clk_lookup bcm6345_clks[] |
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51 | /* fixed rate clocks */ |
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52 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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53 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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54 | + CLKDEV_INIT("fffe0300.serial", "refclk", &clk_periph), |
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55 | /* gated clocks */ |
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56 | CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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57 | CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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58 | @@ -559,6 +568,7 @@ static struct clk_lookup bcm6348_clks[] |
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59 | /* fixed rate clocks */ |
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60 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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61 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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62 | + CLKDEV_INIT("fffe0300.serial", "refclk", &clk_periph), |
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63 | /* gated clocks */ |
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64 | CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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65 | CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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66 | @@ -575,6 +585,8 @@ static struct clk_lookup bcm6358_clks[] |
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67 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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68 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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69 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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70 | + CLKDEV_INIT("fffe0100.serial", "refclk", &clk_periph), |
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71 | + CLKDEV_INIT("fffe0120.serial", "refclk", &clk_periph), |
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72 | /* gated clocks */ |
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73 | CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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74 | CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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75 | @@ -594,7 +606,10 @@ static struct clk_lookup bcm6362_clks[] |
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76 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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77 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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78 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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79 | + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph), |
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80 | + CLKDEV_INIT("10000120.serial", "refclk", &clk_periph), |
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81 | CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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82 | + CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll), |
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83 | /* gated clocks */ |
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84 | CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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85 | CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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86 | @@ -610,6 +625,8 @@ static struct clk_lookup bcm6368_clks[] |
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87 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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88 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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89 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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90 | + CLKDEV_INIT("10000100.serial", "refclk", &clk_periph), |
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91 | + CLKDEV_INIT("10000120.serial", "refclk", &clk_periph), |
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92 | /* gated clocks */ |
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93 | CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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94 | CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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95 | @@ -624,7 +641,10 @@ static struct clk_lookup bcm63268_clks[] |
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96 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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97 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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98 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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99 | + CLKDEV_INIT("10000180.serial", "refclk", &clk_periph), |
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100 | + CLKDEV_INIT("100001a0.serial", "refclk", &clk_periph), |
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101 | CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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102 | + CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll), |
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103 | /* gated clocks */ |
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104 | CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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105 | CLKDEV_INIT(NULL, "usbh", &clk_usbh), |