OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 78b59478f96887aa293670f6dd494628a3714526 Mon Sep 17 00:00:00 2001 |
2 | From: Dave Stevenson <dave.stevenson@raspberrypi.org> |
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3 | Date: Fri, 8 Sep 2017 15:11:53 +0100 |
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4 | Subject: [PATCH 327/454] tc358743: Add support for 972Mbit/s link freq. |
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5 | |||
6 | Adds register setups for running the CSI lanes at 972Mbit/s, |
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7 | which allows 1080P50 UYVY down 2 lanes. |
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8 | |||
9 | Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org> |
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10 | --- |
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11 | drivers/media/i2c/tc358743.c | 47 +++++++++++++++++++++++++----------- |
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12 | 1 file changed, 33 insertions(+), 14 deletions(-) |
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13 | |||
14 | --- a/drivers/media/i2c/tc358743.c |
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15 | +++ b/drivers/media/i2c/tc358743.c |
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16 | @@ -1803,6 +1803,7 @@ static int tc358743_probe_of(struct tc35 |
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17 | /* |
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18 | * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps. |
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19 | * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60. |
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20 | + * 972 Mbps allows 1080P50 UYVY over 2-lane. |
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21 | */ |
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22 | bps_pr_lane = 2 * endpoint->link_frequencies[0]; |
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23 | if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) { |
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24 | @@ -1815,23 +1816,41 @@ static int tc358743_probe_of(struct tc35 |
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25 | state->pdata.refclk_hz * state->pdata.pll_prd; |
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26 | |||
27 | /* |
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28 | - * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz |
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29 | - * link frequency). In principle it should be possible to calculate |
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30 | + * FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane |
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31 | + * (297 MHz or 486 MHz link frequency). |
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32 | + * In principle it should be possible to calculate |
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33 | * them based on link frequency and resolution. |
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34 | */ |
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35 | - if (bps_pr_lane != 594000000U) |
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36 | + switch (bps_pr_lane) { |
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37 | + default: |
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38 | dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane); |
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39 | - state->pdata.lineinitcnt = 0xe80; |
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40 | - state->pdata.lptxtimecnt = 0x003; |
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41 | - /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ |
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42 | - state->pdata.tclk_headercnt = 0x1403; |
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43 | - state->pdata.tclk_trailcnt = 0x00; |
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44 | - /* ths-preparecnt: 3, ths-zerocnt: 1 */ |
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45 | - state->pdata.ths_headercnt = 0x0103; |
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46 | - state->pdata.twakeup = 0x4882; |
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47 | - state->pdata.tclk_postcnt = 0x008; |
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48 | - state->pdata.ths_trailcnt = 0x2; |
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49 | - state->pdata.hstxvregcnt = 0; |
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50 | + case 594000000U: |
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51 | + state->pdata.lineinitcnt = 0xe80; |
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52 | + state->pdata.lptxtimecnt = 0x003; |
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53 | + /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ |
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54 | + state->pdata.tclk_headercnt = 0x1403; |
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55 | + state->pdata.tclk_trailcnt = 0x00; |
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56 | + /* ths-preparecnt: 3, ths-zerocnt: 1 */ |
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57 | + state->pdata.ths_headercnt = 0x0103; |
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58 | + state->pdata.twakeup = 0x4882; |
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59 | + state->pdata.tclk_postcnt = 0x008; |
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60 | + state->pdata.ths_trailcnt = 0x2; |
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61 | + state->pdata.hstxvregcnt = 0; |
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62 | + break; |
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63 | + case 972000000U: |
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64 | + state->pdata.lineinitcnt = 0x1b58; |
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65 | + state->pdata.lptxtimecnt = 0x007; |
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66 | + /* tclk-preparecnt: 6, tclk-zerocnt: 40 */ |
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67 | + state->pdata.tclk_headercnt = 0x2806; |
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68 | + state->pdata.tclk_trailcnt = 0x00; |
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69 | + /* ths-preparecnt: 6, ths-zerocnt: 8 */ |
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70 | + state->pdata.ths_headercnt = 0x0806; |
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71 | + state->pdata.twakeup = 0x4268; |
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72 | + state->pdata.tclk_postcnt = 0x008; |
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73 | + state->pdata.ths_trailcnt = 0x5; |
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74 | + state->pdata.hstxvregcnt = 0; |
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75 | + break; |
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76 | + } |
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77 | |||
78 | state->reset_gpio = devm_gpiod_get_optional(dev, "reset", |
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79 | GPIOD_OUT_LOW); |