OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/pci/pci-ar71xx.c |
2 | +++ b/arch/mips/pci/pci-ar71xx.c |
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3 | @@ -54,11 +54,9 @@ |
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4 | struct ar71xx_pci_controller { |
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5 | struct device_node *np; |
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6 | void __iomem *cfg_base; |
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7 | - int irq; |
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8 | struct pci_controller pci_ctrl; |
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9 | struct resource io_res; |
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10 | struct resource mem_res; |
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11 | - struct irq_domain *domain; |
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12 | }; |
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13 | |||
14 | /* Byte lane enable bits */ |
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15 | @@ -230,104 +228,6 @@ static struct pci_ops ar71xx_pci_ops = { |
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16 | .write = ar71xx_pci_write_config, |
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17 | }; |
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18 | |||
19 | -static void ar71xx_pci_irq_handler(struct irq_desc *desc) |
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20 | -{ |
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21 | - void __iomem *base = ath79_reset_base; |
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22 | - struct irq_chip *chip = irq_desc_get_chip(desc); |
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23 | - struct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc); |
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24 | - u32 pending; |
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25 | - |
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26 | - chained_irq_enter(chip, desc); |
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27 | - pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & |
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28 | - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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29 | - |
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30 | - if (pending & AR71XX_PCI_INT_DEV0) |
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31 | - generic_handle_irq(irq_linear_revmap(apc->domain, 1)); |
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32 | - |
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33 | - else if (pending & AR71XX_PCI_INT_DEV1) |
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34 | - generic_handle_irq(irq_linear_revmap(apc->domain, 2)); |
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35 | - |
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36 | - else if (pending & AR71XX_PCI_INT_DEV2) |
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37 | - generic_handle_irq(irq_linear_revmap(apc->domain, 3)); |
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38 | - |
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39 | - else if (pending & AR71XX_PCI_INT_CORE) |
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40 | - generic_handle_irq(irq_linear_revmap(apc->domain, 4)); |
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41 | - |
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42 | - else |
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43 | - spurious_interrupt(); |
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44 | - chained_irq_exit(chip, desc); |
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45 | -} |
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46 | - |
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47 | -static void ar71xx_pci_irq_unmask(struct irq_data *d) |
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48 | -{ |
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49 | - struct ar71xx_pci_controller *apc; |
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50 | - unsigned int irq; |
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51 | - void __iomem *base = ath79_reset_base; |
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52 | - u32 t; |
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53 | - |
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54 | - apc = irq_data_get_irq_chip_data(d); |
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55 | - irq = irq_linear_revmap(apc->domain, d->irq); |
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56 | - |
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57 | - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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58 | - __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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59 | - |
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60 | - /* flush write */ |
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61 | - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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62 | -} |
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63 | - |
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64 | -static void ar71xx_pci_irq_mask(struct irq_data *d) |
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65 | -{ |
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66 | - struct ar71xx_pci_controller *apc; |
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67 | - unsigned int irq; |
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68 | - void __iomem *base = ath79_reset_base; |
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69 | - u32 t; |
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70 | - |
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71 | - apc = irq_data_get_irq_chip_data(d); |
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72 | - irq = irq_linear_revmap(apc->domain, d->irq); |
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73 | - |
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74 | - t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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75 | - __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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76 | - |
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77 | - /* flush write */ |
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78 | - __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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79 | -} |
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80 | - |
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81 | -static struct irq_chip ar71xx_pci_irq_chip = { |
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82 | - .name = "AR71XX PCI", |
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83 | - .irq_mask = ar71xx_pci_irq_mask, |
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84 | - .irq_unmask = ar71xx_pci_irq_unmask, |
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85 | - .irq_mask_ack = ar71xx_pci_irq_mask, |
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86 | -}; |
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87 | - |
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88 | -static int ar71xx_pci_irq_map(struct irq_domain *d, |
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89 | - unsigned int irq, irq_hw_number_t hw) |
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90 | -{ |
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91 | - struct ar71xx_pci_controller *apc = d->host_data; |
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92 | - |
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93 | - irq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq); |
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94 | - irq_set_chip_data(irq, apc); |
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95 | - |
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96 | - return 0; |
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97 | -} |
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98 | - |
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99 | -static const struct irq_domain_ops ar71xx_pci_domain_ops = { |
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100 | - .xlate = irq_domain_xlate_onecell, |
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101 | - .map = ar71xx_pci_irq_map, |
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102 | -}; |
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103 | - |
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104 | -static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) |
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105 | -{ |
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106 | - void __iomem *base = ath79_reset_base; |
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107 | - |
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108 | - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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109 | - __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); |
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110 | - |
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111 | - apc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT, |
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112 | - &ar71xx_pci_domain_ops, apc); |
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113 | - irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler, |
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114 | - apc); |
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115 | -} |
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116 | - |
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117 | static void ar71xx_pci_reset(void) |
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118 | { |
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119 | ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); |
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120 | @@ -361,10 +261,6 @@ static int ar71xx_pci_probe(struct platf |
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121 | if (IS_ERR(apc->cfg_base)) |
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122 | return PTR_ERR(apc->cfg_base); |
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123 | |||
124 | - apc->irq = platform_get_irq(pdev, 0); |
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125 | - if (apc->irq < 0) |
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126 | - return -EINVAL; |
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127 | - |
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128 | ar71xx_pci_reset(); |
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129 | |||
130 | /* setup COMMAND register */ |
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131 | @@ -375,8 +271,6 @@ static int ar71xx_pci_probe(struct platf |
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132 | /* clear bus errors */ |
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133 | ar71xx_pci_check_error(apc, 1); |
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134 | |||
135 | - ar71xx_pci_irq_init(apc); |
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136 | - |
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137 | apc->np = pdev->dev.of_node; |
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138 | apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; |
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139 | apc->pci_ctrl.mem_resource = &apc->mem_res; |