OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Atheros AR71xx built-in ethernet mac driver |
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3 | * |
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4 | * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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6 | * |
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7 | * Based on Atheros' AG7100 driver |
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8 | * |
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9 | * This program is free software; you can redistribute it and/or modify it |
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10 | * under the terms of the GNU General Public License version 2 as published |
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11 | * by the Free Software Foundation. |
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12 | */ |
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13 | |||
14 | #ifndef __AG71XX_H |
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15 | #define __AG71XX_H |
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16 | |||
17 | #include <linux/kernel.h> |
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18 | #include <linux/version.h> |
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19 | #include <linux/module.h> |
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20 | #include <linux/init.h> |
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21 | #include <linux/types.h> |
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22 | #include <linux/random.h> |
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23 | #include <linux/spinlock.h> |
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24 | #include <linux/interrupt.h> |
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25 | #include <linux/platform_device.h> |
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26 | #include <linux/ethtool.h> |
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27 | #include <linux/etherdevice.h> |
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28 | #include <linux/if_vlan.h> |
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29 | #include <linux/phy.h> |
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30 | #include <linux/skbuff.h> |
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31 | #include <linux/dma-mapping.h> |
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32 | #include <linux/workqueue.h> |
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33 | #include <linux/reset.h> |
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34 | #include <linux/of.h> |
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35 | #include <linux/mfd/syscon.h> |
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36 | #include <linux/regmap.h> |
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37 | |||
38 | #include <linux/bitops.h> |
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39 | |||
40 | #include <asm/mach-ath79/ar71xx_regs.h> |
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41 | #include <asm/mach-ath79/ath79.h> |
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42 | |||
43 | #define AG71XX_DRV_NAME "ag71xx" |
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44 | |||
45 | /* |
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46 | * For our NAPI weight bigger does *NOT* mean better - it means more |
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47 | * D-cache misses and lots more wasted cycles than we'll ever |
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48 | * possibly gain from saving instructions. |
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49 | */ |
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50 | #define AG71XX_NAPI_WEIGHT 32 |
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51 | #define AG71XX_OOM_REFILL (1 + HZ/10) |
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52 | |||
53 | #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) |
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54 | #define AG71XX_INT_TX (AG71XX_INT_TX_PS) |
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55 | #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) |
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56 | |||
57 | #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) |
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58 | #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) |
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59 | |||
60 | #define AG71XX_TX_MTU_LEN 1540 |
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61 | |||
62 | #define AG71XX_TX_RING_SPLIT 512 |
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63 | #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \ |
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64 | AG71XX_TX_RING_SPLIT) |
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65 | #define AG71XX_TX_RING_SIZE_DEFAULT 128 |
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66 | #define AG71XX_RX_RING_SIZE_DEFAULT 256 |
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67 | |||
68 | #define AG71XX_TX_RING_SIZE_MAX 128 |
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69 | #define AG71XX_RX_RING_SIZE_MAX 256 |
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70 | |||
71 | #ifdef CONFIG_AG71XX_DEBUG |
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72 | #define DBG(fmt, args...) pr_debug(fmt, ## args) |
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73 | #else |
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74 | #define DBG(fmt, args...) do {} while (0) |
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75 | #endif |
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76 | |||
77 | #define ag71xx_assert(_cond) \ |
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78 | do { \ |
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79 | if (_cond) \ |
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80 | break; \ |
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81 | printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ |
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82 | BUG(); \ |
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83 | } while (0) |
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84 | |||
85 | struct ag71xx_desc { |
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86 | u32 data; |
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87 | u32 ctrl; |
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88 | #define DESC_EMPTY BIT(31) |
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89 | #define DESC_MORE BIT(24) |
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90 | #define DESC_PKTLEN_M 0xfff |
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91 | u32 next; |
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92 | u32 pad; |
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93 | } __attribute__((aligned(4))); |
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94 | |||
95 | #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \ |
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96 | L1_CACHE_BYTES) |
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97 | |||
98 | struct ag71xx_buf { |
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99 | union { |
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100 | struct sk_buff *skb; |
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101 | void *rx_buf; |
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102 | }; |
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103 | union { |
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104 | dma_addr_t dma_addr; |
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105 | unsigned int len; |
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106 | }; |
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107 | }; |
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108 | |||
109 | struct ag71xx_ring { |
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110 | struct ag71xx_buf *buf; |
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111 | u8 *descs_cpu; |
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112 | dma_addr_t descs_dma; |
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113 | u16 desc_split; |
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114 | u16 order; |
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115 | unsigned int curr; |
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116 | unsigned int dirty; |
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117 | }; |
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118 | |||
119 | struct ag71xx_int_stats { |
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120 | unsigned long rx_pr; |
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121 | unsigned long rx_be; |
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122 | unsigned long rx_of; |
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123 | unsigned long tx_ps; |
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124 | unsigned long tx_be; |
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125 | unsigned long tx_ur; |
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126 | unsigned long total; |
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127 | }; |
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128 | |||
129 | struct ag71xx_napi_stats { |
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130 | unsigned long napi_calls; |
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131 | unsigned long rx_count; |
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132 | unsigned long rx_packets; |
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133 | unsigned long rx_packets_max; |
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134 | unsigned long tx_count; |
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135 | unsigned long tx_packets; |
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136 | unsigned long tx_packets_max; |
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137 | |||
138 | unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; |
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139 | unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; |
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140 | }; |
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141 | |||
142 | struct ag71xx_debug { |
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143 | struct dentry *debugfs_dir; |
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144 | |||
145 | struct ag71xx_int_stats int_stats; |
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146 | struct ag71xx_napi_stats napi_stats; |
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147 | }; |
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148 | |||
149 | struct ag71xx { |
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150 | /* |
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151 | * Critical data related to the per-packet data path are clustered |
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152 | * early in this structure to help improve the D-cache footprint. |
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153 | */ |
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154 | struct ag71xx_ring rx_ring ____cacheline_aligned; |
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155 | struct ag71xx_ring tx_ring ____cacheline_aligned; |
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156 | |||
157 | int mac_idx; |
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158 | |||
159 | u16 desc_pktlen_mask; |
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160 | u16 rx_buf_size; |
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161 | u8 rx_buf_offset; |
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162 | u8 tx_hang_workaround:1; |
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163 | |||
164 | struct net_device *dev; |
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165 | struct platform_device *pdev; |
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166 | spinlock_t lock; |
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167 | struct napi_struct napi; |
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168 | u32 msg_enable; |
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169 | |||
170 | /* |
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171 | * From this point onwards we're not looking at per-packet fields. |
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172 | */ |
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173 | void __iomem *mac_base; |
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174 | void __iomem *mii_base; |
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175 | |||
176 | struct ag71xx_desc *stop_desc; |
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177 | dma_addr_t stop_desc_dma; |
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178 | |||
179 | struct phy_device *phy_dev; |
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180 | void *phy_priv; |
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181 | int phy_if_mode; |
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182 | |||
183 | unsigned int link; |
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184 | unsigned int speed; |
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185 | int duplex; |
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186 | |||
187 | struct delayed_work restart_work; |
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188 | struct timer_list oom_timer; |
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189 | |||
190 | struct reset_control *mac_reset; |
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191 | |||
192 | u32 fifodata[3]; |
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193 | u32 plldata[3]; |
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194 | u32 pllreg[3]; |
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195 | struct regmap *pllregmap; |
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196 | |||
197 | #ifdef CONFIG_AG71XX_DEBUG_FS |
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198 | struct ag71xx_debug debug; |
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199 | #endif |
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200 | }; |
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201 | |||
202 | struct ag71xx_mdio { |
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203 | struct reset_control *mdio_reset; |
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204 | struct mii_bus *mii_bus; |
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205 | struct regmap *mii_regmap; |
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206 | }; |
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207 | |||
208 | extern struct ethtool_ops ag71xx_ethtool_ops; |
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209 | void ag71xx_link_adjust(struct ag71xx *ag); |
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210 | |||
211 | int ag71xx_phy_connect(struct ag71xx *ag); |
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212 | void ag71xx_phy_disconnect(struct ag71xx *ag); |
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213 | |||
214 | static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) |
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215 | { |
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216 | return (desc->ctrl & DESC_EMPTY) != 0; |
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217 | } |
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218 | |||
219 | static inline struct ag71xx_desc * |
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220 | ag71xx_ring_desc(struct ag71xx_ring *ring, int idx) |
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221 | { |
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222 | return (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE]; |
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223 | } |
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224 | |||
225 | static inline int |
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226 | ag71xx_ring_size_order(int size) |
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227 | { |
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228 | return fls(size - 1); |
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229 | } |
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230 | |||
231 | /* Register offsets */ |
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232 | #define AG71XX_REG_MAC_CFG1 0x0000 |
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233 | #define AG71XX_REG_MAC_CFG2 0x0004 |
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234 | #define AG71XX_REG_MAC_IPG 0x0008 |
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235 | #define AG71XX_REG_MAC_HDX 0x000c |
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236 | #define AG71XX_REG_MAC_MFL 0x0010 |
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237 | #define AG71XX_REG_MII_CFG 0x0020 |
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238 | #define AG71XX_REG_MII_CMD 0x0024 |
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239 | #define AG71XX_REG_MII_ADDR 0x0028 |
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240 | #define AG71XX_REG_MII_CTRL 0x002c |
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241 | #define AG71XX_REG_MII_STATUS 0x0030 |
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242 | #define AG71XX_REG_MII_IND 0x0034 |
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243 | #define AG71XX_REG_MAC_IFCTL 0x0038 |
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244 | #define AG71XX_REG_MAC_ADDR1 0x0040 |
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245 | #define AG71XX_REG_MAC_ADDR2 0x0044 |
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246 | #define AG71XX_REG_FIFO_CFG0 0x0048 |
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247 | #define AG71XX_REG_FIFO_CFG1 0x004c |
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248 | #define AG71XX_REG_FIFO_CFG2 0x0050 |
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249 | #define AG71XX_REG_FIFO_CFG3 0x0054 |
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250 | #define AG71XX_REG_FIFO_CFG4 0x0058 |
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251 | #define AG71XX_REG_FIFO_CFG5 0x005c |
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252 | #define AG71XX_REG_FIFO_RAM0 0x0060 |
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253 | #define AG71XX_REG_FIFO_RAM1 0x0064 |
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254 | #define AG71XX_REG_FIFO_RAM2 0x0068 |
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255 | #define AG71XX_REG_FIFO_RAM3 0x006c |
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256 | #define AG71XX_REG_FIFO_RAM4 0x0070 |
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257 | #define AG71XX_REG_FIFO_RAM5 0x0074 |
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258 | #define AG71XX_REG_FIFO_RAM6 0x0078 |
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259 | #define AG71XX_REG_FIFO_RAM7 0x007c |
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260 | |||
261 | #define AG71XX_REG_TX_CTRL 0x0180 |
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262 | #define AG71XX_REG_TX_DESC 0x0184 |
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263 | #define AG71XX_REG_TX_STATUS 0x0188 |
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264 | #define AG71XX_REG_RX_CTRL 0x018c |
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265 | #define AG71XX_REG_RX_DESC 0x0190 |
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266 | #define AG71XX_REG_RX_STATUS 0x0194 |
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267 | #define AG71XX_REG_INT_ENABLE 0x0198 |
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268 | #define AG71XX_REG_INT_STATUS 0x019c |
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269 | |||
270 | #define AG71XX_REG_FIFO_DEPTH 0x01a8 |
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271 | #define AG71XX_REG_RX_SM 0x01b0 |
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272 | #define AG71XX_REG_TX_SM 0x01b4 |
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273 | |||
274 | #define MAC_CFG1_TXE BIT(0) /* Tx Enable */ |
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275 | #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ |
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276 | #define MAC_CFG1_RXE BIT(2) /* Rx Enable */ |
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277 | #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ |
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278 | #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ |
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279 | #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ |
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280 | #define MAC_CFG1_LB BIT(8) /* Loopback mode */ |
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281 | #define MAC_CFG1_SR BIT(31) /* Soft Reset */ |
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282 | |||
283 | #define MAC_CFG2_FDX BIT(0) |
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284 | #define MAC_CFG2_CRC_EN BIT(1) |
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285 | #define MAC_CFG2_PAD_CRC_EN BIT(2) |
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286 | #define MAC_CFG2_LEN_CHECK BIT(4) |
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287 | #define MAC_CFG2_HUGE_FRAME_EN BIT(5) |
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288 | #define MAC_CFG2_IF_1000 BIT(9) |
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289 | #define MAC_CFG2_IF_10_100 BIT(8) |
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290 | |||
291 | #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ |
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292 | #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ |
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293 | #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ |
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294 | #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ |
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295 | #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ |
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296 | #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ |
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297 | | FIFO_CFG0_TXS | FIFO_CFG0_TXF) |
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298 | |||
299 | #define FIFO_CFG0_ENABLE_SHIFT 8 |
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300 | |||
301 | #define FIFO_CFG4_DE BIT(0) /* Drop Event */ |
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302 | #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ |
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303 | #define FIFO_CFG4_FC BIT(2) /* False Carrier */ |
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304 | #define FIFO_CFG4_CE BIT(3) /* Code Error */ |
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305 | #define FIFO_CFG4_CR BIT(4) /* CRC error */ |
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306 | #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ |
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307 | #define FIFO_CFG4_LO BIT(6) /* Length out of range */ |
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308 | #define FIFO_CFG4_OK BIT(7) /* Packet is OK */ |
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309 | #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ |
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310 | #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ |
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311 | #define FIFO_CFG4_DR BIT(10) /* Dribble */ |
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312 | #define FIFO_CFG4_LE BIT(11) /* Long Event */ |
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313 | #define FIFO_CFG4_CF BIT(12) /* Control Frame */ |
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314 | #define FIFO_CFG4_PF BIT(13) /* Pause Frame */ |
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315 | #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ |
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316 | #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ |
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317 | #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ |
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318 | #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ |
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319 | |||
320 | #define FIFO_CFG5_DE BIT(0) /* Drop Event */ |
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321 | #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ |
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322 | #define FIFO_CFG5_FC BIT(2) /* False Carrier */ |
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323 | #define FIFO_CFG5_CE BIT(3) /* Code Error */ |
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324 | #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ |
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325 | #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ |
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326 | #define FIFO_CFG5_OK BIT(6) /* Packet is OK */ |
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327 | #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ |
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328 | #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ |
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329 | #define FIFO_CFG5_DR BIT(9) /* Dribble */ |
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330 | #define FIFO_CFG5_CF BIT(10) /* Control Frame */ |
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331 | #define FIFO_CFG5_PF BIT(11) /* Pause Frame */ |
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332 | #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ |
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333 | #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ |
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334 | #define FIFO_CFG5_LE BIT(14) /* Long Event */ |
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335 | #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ |
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336 | #define FIFO_CFG5_16 BIT(16) /* unknown */ |
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337 | #define FIFO_CFG5_17 BIT(17) /* unknown */ |
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338 | #define FIFO_CFG5_SF BIT(18) /* Short Frame */ |
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339 | #define FIFO_CFG5_BM BIT(19) /* Byte Mode */ |
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340 | |||
341 | #define AG71XX_INT_TX_PS BIT(0) |
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342 | #define AG71XX_INT_TX_UR BIT(1) |
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343 | #define AG71XX_INT_TX_BE BIT(3) |
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344 | #define AG71XX_INT_RX_PR BIT(4) |
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345 | #define AG71XX_INT_RX_OF BIT(6) |
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346 | #define AG71XX_INT_RX_BE BIT(7) |
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347 | |||
348 | #define MAC_IFCTL_SPEED BIT(16) |
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349 | |||
350 | #define MII_CFG_CLK_DIV_4 0 |
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351 | #define MII_CFG_CLK_DIV_6 2 |
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352 | #define MII_CFG_CLK_DIV_8 3 |
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353 | #define MII_CFG_CLK_DIV_10 4 |
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354 | #define MII_CFG_CLK_DIV_14 5 |
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355 | #define MII_CFG_CLK_DIV_20 6 |
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356 | #define MII_CFG_CLK_DIV_28 7 |
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357 | #define MII_CFG_CLK_DIV_34 8 |
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358 | #define MII_CFG_CLK_DIV_42 9 |
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359 | #define MII_CFG_CLK_DIV_50 10 |
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360 | #define MII_CFG_CLK_DIV_58 11 |
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361 | #define MII_CFG_CLK_DIV_66 12 |
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362 | #define MII_CFG_CLK_DIV_74 13 |
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363 | #define MII_CFG_CLK_DIV_82 14 |
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364 | #define MII_CFG_CLK_DIV_98 15 |
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365 | #define MII_CFG_RESET BIT(31) |
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366 | |||
367 | #define MII_CMD_WRITE 0x0 |
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368 | #define MII_CMD_READ 0x1 |
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369 | #define MII_ADDR_SHIFT 8 |
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370 | #define MII_IND_BUSY BIT(0) |
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371 | #define MII_IND_INVALID BIT(2) |
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372 | |||
373 | #define TX_CTRL_TXE BIT(0) /* Tx Enable */ |
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374 | |||
375 | #define TX_STATUS_PS BIT(0) /* Packet Sent */ |
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376 | #define TX_STATUS_UR BIT(1) /* Tx Underrun */ |
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377 | #define TX_STATUS_BE BIT(3) /* Bus Error */ |
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378 | |||
379 | #define RX_CTRL_RXE BIT(0) /* Rx Enable */ |
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380 | |||
381 | #define RX_STATUS_PR BIT(0) /* Packet Received */ |
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382 | #define RX_STATUS_OF BIT(2) /* Rx Overflow */ |
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383 | #define RX_STATUS_BE BIT(3) /* Bus Error */ |
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384 | |||
385 | static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) |
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386 | { |
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387 | __raw_writel(value, ag->mac_base + reg); |
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388 | /* flush write */ |
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389 | (void) __raw_readl(ag->mac_base + reg); |
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390 | } |
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391 | |||
392 | static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) |
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393 | { |
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394 | return __raw_readl(ag->mac_base + reg); |
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395 | } |
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396 | |||
397 | static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) |
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398 | { |
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399 | void __iomem *r; |
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400 | |||
401 | r = ag->mac_base + reg; |
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402 | __raw_writel(__raw_readl(r) | mask, r); |
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403 | /* flush write */ |
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404 | (void) __raw_readl(r); |
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405 | } |
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406 | |||
407 | static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) |
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408 | { |
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409 | void __iomem *r; |
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410 | |||
411 | r = ag->mac_base + reg; |
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412 | __raw_writel(__raw_readl(r) & ~mask, r); |
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413 | /* flush write */ |
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414 | (void) __raw_readl(r); |
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415 | } |
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416 | |||
417 | static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) |
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418 | { |
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419 | ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); |
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420 | } |
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421 | |||
422 | static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) |
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423 | { |
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424 | ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); |
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425 | } |
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426 | |||
427 | #ifdef CONFIG_AG71XX_DEBUG_FS |
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428 | int ag71xx_debugfs_root_init(void); |
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429 | void ag71xx_debugfs_root_exit(void); |
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430 | int ag71xx_debugfs_init(struct ag71xx *ag); |
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431 | void ag71xx_debugfs_exit(struct ag71xx *ag); |
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432 | void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); |
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433 | void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); |
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434 | #else |
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435 | static inline int ag71xx_debugfs_root_init(void) { return 0; } |
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436 | static inline void ag71xx_debugfs_root_exit(void) {} |
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437 | static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } |
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438 | static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} |
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439 | static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, |
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440 | u32 status) {} |
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441 | static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, |
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442 | int rx, int tx) {} |
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443 | #endif /* CONFIG_AG71XX_DEBUG_FS */ |
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444 | |||
445 | int ag71xx_ar7240_init(struct ag71xx *ag, struct device_node *np); |
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446 | void ag71xx_ar7240_cleanup(struct ag71xx *ag); |
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447 | |||
448 | int ag71xx_setup_gmac(struct device_node *np); |
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449 | |||
450 | int ar7240sw_phy_read(struct mii_bus *mii, int addr, int reg); |
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451 | int ar7240sw_phy_write(struct mii_bus *mii, int addr, int reg, u16 val); |
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452 | |||
453 | #endif /* _AG71XX_H */ |