OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/ath79/irq.c |
2 | +++ b/arch/mips/ath79/irq.c |
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3 | @@ -27,6 +27,9 @@ |
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4 | #include "machtypes.h" |
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5 | |||
6 | |||
7 | +static struct irq_chip ip2_chip; |
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8 | +static struct irq_chip ip3_chip; |
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9 | + |
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10 | static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) |
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11 | { |
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12 | u32 status; |
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13 | @@ -50,8 +53,7 @@ static void ar934x_ip2_irq_init(void) |
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14 | |||
15 | for (i = ATH79_IP2_IRQ_BASE; |
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16 | i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) |
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17 | - irq_set_chip_and_handler(i, &dummy_irq_chip, |
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18 | - handle_level_irq); |
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19 | + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); |
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20 | |||
21 | irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); |
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22 | } |
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23 | @@ -79,7 +81,7 @@ static void qca953x_irq_init(void) |
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24 | |||
25 | for (i = ATH79_IP2_IRQ_BASE; |
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26 | i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) |
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27 | - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); |
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28 | + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); |
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29 | |||
30 | irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); |
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31 | } |
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32 | @@ -143,15 +145,13 @@ static void qca955x_irq_init(void) |
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33 | |||
34 | for (i = ATH79_IP2_IRQ_BASE; |
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35 | i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) |
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36 | - irq_set_chip_and_handler(i, &dummy_irq_chip, |
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37 | - handle_level_irq); |
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38 | + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); |
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39 | |||
40 | irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch); |
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41 | |||
42 | for (i = ATH79_IP3_IRQ_BASE; |
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43 | i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) |
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44 | - irq_set_chip_and_handler(i, &dummy_irq_chip, |
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45 | - handle_level_irq); |
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46 | + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); |
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47 | |||
48 | irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); |
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49 | } |
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50 | @@ -222,13 +222,13 @@ static void qca956x_irq_init(void) |
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51 | |||
52 | for (i = ATH79_IP2_IRQ_BASE; |
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53 | i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) |
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54 | - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); |
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55 | + irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq); |
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56 | |||
57 | irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch); |
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58 | |||
59 | for (i = ATH79_IP3_IRQ_BASE; |
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60 | i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++) |
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61 | - irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq); |
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62 | + irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq); |
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63 | |||
64 | irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); |
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65 | |||
66 | @@ -237,12 +237,40 @@ static void qca956x_irq_init(void) |
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67 | late_time_init = &qca956x_enable_timer_cb; |
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68 | } |
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69 | |||
70 | +static void ath79_ip2_disable(struct irq_data *data) |
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71 | +{ |
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72 | + disable_irq(ATH79_CPU_IRQ(2)); |
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73 | +} |
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74 | + |
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75 | +static void ath79_ip2_enable(struct irq_data *data) |
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76 | +{ |
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77 | + enable_irq(ATH79_CPU_IRQ(2)); |
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78 | +} |
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79 | + |
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80 | +static void ath79_ip3_disable(struct irq_data *data) |
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81 | +{ |
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82 | + disable_irq(ATH79_CPU_IRQ(3)); |
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83 | +} |
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84 | + |
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85 | +static void ath79_ip3_enable(struct irq_data *data) |
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86 | +{ |
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87 | + enable_irq(ATH79_CPU_IRQ(3)); |
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88 | +} |
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89 | + |
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90 | void __init arch_init_irq(void) |
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91 | { |
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92 | unsigned irq_wb_chan2 = -1; |
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93 | unsigned irq_wb_chan3 = -1; |
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94 | bool misc_is_ar71xx; |
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95 | |||
96 | + ip2_chip = dummy_irq_chip; |
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97 | + ip2_chip.irq_disable = ath79_ip2_disable; |
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98 | + ip2_chip.irq_enable = ath79_ip2_enable; |
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99 | + |
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100 | + ip3_chip = dummy_irq_chip; |
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101 | + ip3_chip.irq_disable = ath79_ip3_disable; |
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102 | + ip3_chip.irq_enable = ath79_ip3_enable; |
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103 | + |
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104 | if (mips_machtype == ATH79_MACH_GENERIC_OF) { |
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105 | irqchip_init(); |
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106 | return; |