OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * SPI controller driver for the Mikrotik RB4xx boards |
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3 | * |
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4 | * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org> |
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5 | * |
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6 | * This file was based on the patches for Linux 2.6.27.39 published by |
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7 | * MikroTik for their RouterBoard 4xx series devices. |
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8 | * |
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9 | * This program is free software; you can redistribute it and/or modify |
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10 | * it under the terms of the GNU General Public License version 2 as |
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11 | * published by the Free Software Foundation. |
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12 | * |
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13 | */ |
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14 | |||
15 | #include <linux/clk.h> |
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16 | #include <linux/err.h> |
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17 | #include <linux/kernel.h> |
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18 | #include <linux/module.h> |
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19 | #include <linux/init.h> |
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20 | #include <linux/delay.h> |
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21 | #include <linux/spinlock.h> |
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22 | #include <linux/workqueue.h> |
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23 | #include <linux/platform_device.h> |
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24 | #include <linux/spi/spi.h> |
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25 | |||
26 | #include <asm/mach-ath79/ar71xx_regs.h> |
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27 | #include <asm/mach-ath79/ath79.h> |
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28 | |||
29 | #define DRV_NAME "rb4xx-spi" |
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30 | #define DRV_DESC "Mikrotik RB4xx SPI controller driver" |
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31 | #define DRV_VERSION "0.1.0" |
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32 | |||
33 | #define SPI_CTRL_FASTEST 0x40 |
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34 | #define SPI_FLASH_HZ 33333334 |
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35 | #define SPI_CPLD_HZ 33333334 |
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36 | |||
37 | #define CPLD_CMD_READ_FAST 0x0b |
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38 | |||
39 | #undef RB4XX_SPI_DEBUG |
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40 | |||
41 | struct rb4xx_spi { |
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42 | void __iomem *base; |
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43 | struct spi_master *master; |
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44 | |||
45 | unsigned spi_ctrl_flash; |
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46 | unsigned spi_ctrl_fread; |
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47 | |||
48 | struct clk *ahb_clk; |
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49 | unsigned long ahb_freq; |
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50 | |||
51 | spinlock_t lock; |
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52 | struct list_head queue; |
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53 | int busy:1; |
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54 | int cs_wait; |
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55 | }; |
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56 | |||
57 | static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1; |
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58 | |||
59 | #ifdef RB4XX_SPI_DEBUG |
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60 | static inline void do_spi_delay(void) |
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61 | { |
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62 | ndelay(20000); |
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63 | } |
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64 | #else |
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65 | static inline void do_spi_delay(void) { } |
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66 | #endif |
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67 | |||
68 | static inline void do_spi_init(struct spi_device *spi) |
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69 | { |
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70 | unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1; |
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71 | |||
72 | if (!(spi->mode & SPI_CS_HIGH)) |
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73 | cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 : |
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74 | AR71XX_SPI_IOC_CS0; |
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75 | |||
76 | spi_clk_low = cs; |
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77 | } |
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78 | |||
79 | static inline void do_spi_finish(void __iomem *base) |
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80 | { |
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81 | do_spi_delay(); |
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82 | __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1, |
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83 | base + AR71XX_SPI_REG_IOC); |
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84 | } |
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85 | |||
86 | static inline void do_spi_clk(void __iomem *base, int bit) |
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87 | { |
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88 | unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0); |
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89 | |||
90 | do_spi_delay(); |
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91 | __raw_writel(bval, base + AR71XX_SPI_REG_IOC); |
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92 | do_spi_delay(); |
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93 | __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); |
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94 | } |
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95 | |||
96 | static void do_spi_byte(void __iomem *base, unsigned char byte) |
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97 | { |
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98 | do_spi_clk(base, byte >> 7); |
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99 | do_spi_clk(base, byte >> 6); |
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100 | do_spi_clk(base, byte >> 5); |
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101 | do_spi_clk(base, byte >> 4); |
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102 | do_spi_clk(base, byte >> 3); |
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103 | do_spi_clk(base, byte >> 2); |
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104 | do_spi_clk(base, byte >> 1); |
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105 | do_spi_clk(base, byte); |
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106 | |||
107 | pr_debug("spi_byte sent 0x%02x got 0x%02x\n", |
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108 | (unsigned)byte, |
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109 | (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS)); |
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110 | } |
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111 | |||
112 | static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1, |
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113 | unsigned bit2) |
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114 | { |
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115 | unsigned bval = (spi_clk_low | |
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116 | ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) | |
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117 | ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0)); |
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118 | do_spi_delay(); |
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119 | __raw_writel(bval, base + AR71XX_SPI_REG_IOC); |
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120 | do_spi_delay(); |
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121 | __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC); |
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122 | } |
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123 | |||
124 | static void do_spi_byte_fast(void __iomem *base, unsigned char byte) |
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125 | { |
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126 | do_spi_clk_fast(base, byte >> 7, byte >> 6); |
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127 | do_spi_clk_fast(base, byte >> 5, byte >> 4); |
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128 | do_spi_clk_fast(base, byte >> 3, byte >> 2); |
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129 | do_spi_clk_fast(base, byte >> 1, byte >> 0); |
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130 | |||
131 | pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n", |
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132 | (unsigned)byte, |
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133 | (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS)); |
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134 | } |
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135 | |||
136 | static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t) |
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137 | { |
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138 | const unsigned char *tx_ptr = t->tx_buf; |
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139 | unsigned char *rx_ptr = t->rx_buf; |
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140 | unsigned i; |
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141 | |||
142 | pr_debug("spi_txrx len %u tx %u rx %u\n", |
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143 | t->len, |
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144 | (t->tx_buf ? 1 : 0), |
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145 | (t->rx_buf ? 1 : 0)); |
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146 | |||
147 | for (i = 0; i < t->len; ++i) { |
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148 | unsigned char sdata = tx_ptr ? tx_ptr[i] : 0; |
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149 | |||
150 | if (t->tx_nbits == SPI_NBITS_DUAL) |
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151 | do_spi_byte_fast(base, sdata); |
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152 | else |
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153 | do_spi_byte(base, sdata); |
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154 | |||
155 | if (rx_ptr) |
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156 | rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff; |
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157 | } |
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158 | |||
159 | return i; |
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160 | } |
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161 | |||
162 | static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m) |
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163 | { |
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164 | struct spi_transfer *t = NULL; |
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165 | void __iomem *base = rbspi->base; |
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166 | |||
167 | m->status = 0; |
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168 | if (list_empty(&m->transfers)) |
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169 | return -1; |
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170 | |||
171 | __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS); |
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172 | __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL); |
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173 | do_spi_init(m->spi); |
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174 | |||
175 | list_for_each_entry(t, &m->transfers, transfer_list) { |
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176 | int len; |
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177 | |||
178 | len = rb4xx_spi_txrx(base, t); |
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179 | if (len != t->len) { |
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180 | m->status = -EMSGSIZE; |
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181 | break; |
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182 | } |
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183 | m->actual_length += len; |
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184 | |||
185 | if (t->cs_change) { |
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186 | if (list_is_last(&t->transfer_list, &m->transfers)) { |
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187 | /* wait for continuation */ |
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188 | return m->spi->chip_select; |
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189 | } |
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190 | do_spi_finish(base); |
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191 | ndelay(100); |
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192 | } |
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193 | } |
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194 | |||
195 | do_spi_finish(base); |
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196 | __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL); |
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197 | __raw_writel(0, base + AR71XX_SPI_REG_FS); |
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198 | return -1; |
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199 | } |
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200 | |||
201 | static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi, |
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202 | unsigned long *flags) |
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203 | { |
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204 | int cs = rbspi->cs_wait; |
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205 | |||
206 | rbspi->busy = 1; |
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207 | while (!list_empty(&rbspi->queue)) { |
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208 | struct spi_message *m; |
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209 | |||
210 | list_for_each_entry(m, &rbspi->queue, queue) |
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211 | if (cs < 0 || cs == m->spi->chip_select) |
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212 | break; |
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213 | |||
214 | if (&m->queue == &rbspi->queue) |
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215 | break; |
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216 | |||
217 | list_del_init(&m->queue); |
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218 | spin_unlock_irqrestore(&rbspi->lock, *flags); |
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219 | |||
220 | cs = rb4xx_spi_msg(rbspi, m); |
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221 | m->complete(m->context); |
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222 | |||
223 | spin_lock_irqsave(&rbspi->lock, *flags); |
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224 | } |
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225 | |||
226 | rbspi->cs_wait = cs; |
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227 | rbspi->busy = 0; |
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228 | |||
229 | if (cs >= 0) { |
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230 | /* TODO: add timer to unlock cs after 1s inactivity */ |
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231 | } |
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232 | } |
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233 | |||
234 | static int rb4xx_spi_transfer(struct spi_device *spi, |
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235 | struct spi_message *m) |
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236 | { |
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237 | struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); |
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238 | unsigned long flags; |
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239 | |||
240 | m->actual_length = 0; |
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241 | m->status = -EINPROGRESS; |
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242 | |||
243 | spin_lock_irqsave(&rbspi->lock, flags); |
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244 | list_add_tail(&m->queue, &rbspi->queue); |
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245 | if (rbspi->busy || |
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246 | (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) { |
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247 | /* job will be done later */ |
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248 | spin_unlock_irqrestore(&rbspi->lock, flags); |
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249 | return 0; |
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250 | } |
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251 | |||
252 | /* process job in current context */ |
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253 | rb4xx_spi_process_queue_locked(rbspi, &flags); |
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254 | spin_unlock_irqrestore(&rbspi->lock, flags); |
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255 | |||
256 | return 0; |
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257 | } |
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258 | |||
259 | static int rb4xx_spi_setup(struct spi_device *spi) |
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260 | { |
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261 | struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); |
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262 | unsigned long flags; |
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263 | |||
264 | if (spi->mode & ~(SPI_CS_HIGH | SPI_TX_DUAL)) { |
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265 | dev_err(&spi->dev, "mode %x not supported\n", |
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266 | (unsigned) spi->mode); |
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267 | return -EINVAL; |
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268 | } |
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269 | |||
270 | if (spi->bits_per_word != 8 && spi->bits_per_word != 0) { |
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271 | dev_err(&spi->dev, "bits_per_word %u not supported\n", |
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272 | (unsigned) spi->bits_per_word); |
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273 | return -EINVAL; |
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274 | } |
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275 | |||
276 | spin_lock_irqsave(&rbspi->lock, flags); |
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277 | if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) { |
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278 | rbspi->cs_wait = -1; |
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279 | rb4xx_spi_process_queue_locked(rbspi, &flags); |
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280 | } |
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281 | spin_unlock_irqrestore(&rbspi->lock, flags); |
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282 | |||
283 | return 0; |
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284 | } |
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285 | |||
286 | static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max, |
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287 | const char *name) |
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288 | { |
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289 | unsigned div; |
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290 | |||
291 | div = (rbspi->ahb_freq - 1) / (2 * hz_max); |
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292 | |||
293 | /* |
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294 | * CPU has a bug at (div == 0) - first bit read is random |
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295 | */ |
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296 | if (div == 0) |
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297 | ++div; |
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298 | |||
299 | if (name) { |
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300 | unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000; |
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301 | unsigned div_real = 2 * (div + 1); |
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302 | pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n", |
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303 | name, |
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304 | ahb_khz / div_real, |
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305 | ahb_khz, div_real); |
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306 | } |
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307 | |||
308 | return SPI_CTRL_FASTEST + div; |
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309 | } |
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310 | |||
311 | static int rb4xx_spi_probe(struct platform_device *pdev) |
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312 | { |
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313 | struct spi_master *master; |
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314 | struct rb4xx_spi *rbspi; |
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315 | struct resource *r; |
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316 | int err = 0; |
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317 | |||
318 | master = spi_alloc_master(&pdev->dev, sizeof(*rbspi)); |
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319 | if (master == NULL) { |
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320 | dev_err(&pdev->dev, "no memory for spi_master\n"); |
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321 | err = -ENOMEM; |
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322 | goto err_out; |
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323 | } |
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324 | |||
325 | master->bus_num = 0; |
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326 | master->num_chipselect = 3; |
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327 | master->mode_bits = SPI_TX_DUAL; |
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328 | master->setup = rb4xx_spi_setup; |
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329 | master->transfer = rb4xx_spi_transfer; |
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330 | |||
331 | rbspi = spi_master_get_devdata(master); |
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332 | |||
333 | rbspi->ahb_clk = clk_get(&pdev->dev, "ahb"); |
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334 | if (IS_ERR(rbspi->ahb_clk)) { |
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335 | err = PTR_ERR(rbspi->ahb_clk); |
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336 | goto err_put_master; |
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337 | } |
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338 | |||
339 | err = clk_prepare_enable(rbspi->ahb_clk); |
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340 | if (err) |
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341 | goto err_clk_put; |
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342 | |||
343 | rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk); |
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344 | if (!rbspi->ahb_freq) { |
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345 | err = -EINVAL; |
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346 | goto err_clk_disable; |
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347 | } |
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348 | |||
349 | platform_set_drvdata(pdev, rbspi); |
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350 | |||
351 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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352 | if (r == NULL) { |
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353 | err = -ENOENT; |
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354 | goto err_clk_disable; |
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355 | } |
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356 | |||
357 | rbspi->base = ioremap(r->start, r->end - r->start + 1); |
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358 | if (!rbspi->base) { |
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359 | err = -ENXIO; |
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360 | goto err_clk_disable; |
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361 | } |
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362 | |||
363 | rbspi->master = master; |
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364 | rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH"); |
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365 | rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD"); |
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366 | rbspi->cs_wait = -1; |
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367 | |||
368 | spin_lock_init(&rbspi->lock); |
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369 | INIT_LIST_HEAD(&rbspi->queue); |
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370 | |||
371 | err = spi_register_master(master); |
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372 | if (err) { |
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373 | dev_err(&pdev->dev, "failed to register SPI master\n"); |
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374 | goto err_iounmap; |
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375 | } |
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376 | |||
377 | return 0; |
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378 | |||
379 | err_iounmap: |
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380 | iounmap(rbspi->base); |
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381 | err_clk_disable: |
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382 | clk_disable_unprepare(rbspi->ahb_clk); |
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383 | err_clk_put: |
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384 | clk_put(rbspi->ahb_clk); |
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385 | err_put_master: |
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386 | platform_set_drvdata(pdev, NULL); |
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387 | spi_master_put(master); |
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388 | err_out: |
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389 | return err; |
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390 | } |
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391 | |||
392 | static int rb4xx_spi_remove(struct platform_device *pdev) |
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393 | { |
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394 | struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); |
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395 | |||
396 | iounmap(rbspi->base); |
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397 | clk_disable_unprepare(rbspi->ahb_clk); |
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398 | clk_put(rbspi->ahb_clk); |
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399 | platform_set_drvdata(pdev, NULL); |
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400 | spi_master_put(rbspi->master); |
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401 | |||
402 | return 0; |
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403 | } |
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404 | |||
405 | static struct platform_driver rb4xx_spi_drv = { |
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406 | .probe = rb4xx_spi_probe, |
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407 | .remove = rb4xx_spi_remove, |
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408 | .driver = { |
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409 | .name = DRV_NAME, |
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410 | .owner = THIS_MODULE, |
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411 | }, |
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412 | }; |
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413 | |||
414 | static int __init rb4xx_spi_init(void) |
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415 | { |
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416 | return platform_driver_register(&rb4xx_spi_drv); |
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417 | } |
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418 | subsys_initcall(rb4xx_spi_init); |
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419 | |||
420 | static void __exit rb4xx_spi_exit(void) |
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421 | { |
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422 | platform_driver_unregister(&rb4xx_spi_drv); |
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423 | } |
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424 | |||
425 | module_exit(rb4xx_spi_exit); |
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426 | |||
427 | MODULE_DESCRIPTION(DRV_DESC); |
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428 | MODULE_VERSION(DRV_VERSION); |
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429 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
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430 | MODULE_LICENSE("GPL v2"); |