OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Linksys WRT400N board support |
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3 | * |
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4 | * Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
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10 | */ |
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11 | |||
12 | #include <linux/mtd/mtd.h> |
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13 | #include <linux/mtd/partitions.h> |
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14 | |||
15 | #include <asm/mach-ath79/ath79.h> |
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16 | |||
17 | #include "dev-ap9x-pci.h" |
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18 | #include "dev-eth.h" |
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19 | #include "dev-gpio-buttons.h" |
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20 | #include "dev-leds-gpio.h" |
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21 | #include "dev-m25p80.h" |
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22 | #include "machtypes.h" |
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23 | |||
24 | #define WRT400N_GPIO_LED_POWER 1 |
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25 | #define WRT400N_GPIO_LED_WPS_BLUE 4 |
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26 | #define WRT400N_GPIO_LED_WPS_AMBER 5 |
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27 | #define WRT400N_GPIO_LED_WLAN 6 |
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28 | |||
29 | #define WRT400N_GPIO_BTN_RESET 8 |
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30 | #define WRT400N_GPIO_BTN_WLSEC 3 |
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31 | |||
32 | #define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */ |
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33 | #define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL) |
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34 | |||
35 | #define WRT400N_MAC_ADDR_OFFSET 0x120c |
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36 | #define WRT400N_CALDATA0_OFFSET 0x1000 |
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37 | #define WRT400N_CALDATA1_OFFSET 0x5000 |
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38 | |||
39 | static struct mtd_partition wrt400n_partitions[] = { |
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40 | { |
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41 | .name = "uboot", |
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42 | .offset = 0, |
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43 | .size = 0x030000, |
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44 | .mask_flags = MTD_WRITEABLE, |
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45 | }, { |
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46 | .name = "env", |
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47 | .offset = 0x030000, |
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48 | .size = 0x010000, |
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49 | .mask_flags = MTD_WRITEABLE, |
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50 | }, { |
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51 | .name = "linux", |
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52 | .offset = 0x040000, |
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53 | .size = 0x140000, |
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54 | }, { |
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55 | .name = "rootfs", |
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56 | .offset = 0x180000, |
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57 | .size = 0x630000, |
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58 | }, { |
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59 | .name = "nvram", |
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60 | .offset = 0x7b0000, |
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61 | .size = 0x010000, |
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62 | .mask_flags = MTD_WRITEABLE, |
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63 | }, { |
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64 | .name = "factory", |
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65 | .offset = 0x7c0000, |
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66 | .size = 0x010000, |
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67 | .mask_flags = MTD_WRITEABLE, |
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68 | }, { |
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69 | .name = "language", |
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70 | .offset = 0x7d0000, |
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71 | .size = 0x020000, |
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72 | .mask_flags = MTD_WRITEABLE, |
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73 | }, { |
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74 | .name = "caldata", |
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75 | .offset = 0x7f0000, |
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76 | .size = 0x010000, |
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77 | .mask_flags = MTD_WRITEABLE, |
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78 | }, { |
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79 | .name = "firmware", |
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80 | .offset = 0x040000, |
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81 | .size = 0x770000, |
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82 | } |
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83 | }; |
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84 | |||
85 | static struct flash_platform_data wrt400n_flash_data = { |
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86 | .parts = wrt400n_partitions, |
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87 | .nr_parts = ARRAY_SIZE(wrt400n_partitions), |
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88 | }; |
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89 | |||
90 | static struct gpio_led wrt400n_leds_gpio[] __initdata = { |
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91 | { |
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92 | .name = "wrt400n:blue:wps", |
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93 | .gpio = WRT400N_GPIO_LED_WPS_BLUE, |
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94 | .active_low = 1, |
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95 | }, { |
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96 | .name = "wrt400n:amber:wps", |
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97 | .gpio = WRT400N_GPIO_LED_WPS_AMBER, |
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98 | .active_low = 1, |
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99 | }, { |
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100 | .name = "wrt400n:blue:wlan", |
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101 | .gpio = WRT400N_GPIO_LED_WLAN, |
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102 | .active_low = 1, |
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103 | }, { |
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104 | .name = "wrt400n:blue:power", |
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105 | .gpio = WRT400N_GPIO_LED_POWER, |
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106 | .active_low = 0, |
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107 | .default_trigger = "default-on", |
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108 | } |
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109 | }; |
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110 | |||
111 | static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = { |
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112 | { |
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113 | .desc = "reset", |
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114 | .type = EV_KEY, |
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115 | .code = KEY_RESTART, |
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116 | .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, |
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117 | .gpio = WRT400N_GPIO_BTN_RESET, |
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118 | .active_low = 1, |
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119 | }, { |
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120 | .desc = "wlsec", |
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121 | .type = EV_KEY, |
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122 | .code = KEY_WPS_BUTTON, |
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123 | .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, |
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124 | .gpio = WRT400N_GPIO_BTN_WLSEC, |
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125 | .active_low = 1, |
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126 | } |
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127 | }; |
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128 | |||
129 | static void __init wrt400n_setup(void) |
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130 | { |
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131 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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132 | u8 *mac = art + WRT400N_MAC_ADDR_OFFSET; |
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133 | |||
134 | ath79_register_mdio(0, 0x0); |
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135 | |||
136 | ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); |
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137 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
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138 | ath79_eth0_data.speed = SPEED_100; |
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139 | ath79_eth0_data.duplex = DUPLEX_FULL; |
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140 | |||
141 | ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2); |
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142 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
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143 | ath79_eth1_data.phy_mask = 0x10; |
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144 | |||
145 | ath79_register_eth(0); |
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146 | ath79_register_eth(1); |
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147 | |||
148 | ath79_register_m25p80(&wrt400n_flash_data); |
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149 | |||
150 | ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), |
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151 | wrt400n_leds_gpio); |
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152 | |||
153 | ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL, |
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154 | ARRAY_SIZE(wrt400n_gpio_keys), |
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155 | wrt400n_gpio_keys); |
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156 | |||
157 | ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, |
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158 | art + WRT400N_CALDATA1_OFFSET, NULL); |
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159 | } |
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160 | |||
161 | MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); |