OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Compex WPJ342 board support |
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3 | * |
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4 | * Copyright (c) 2011 Qualcomm Atheros |
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5 | * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> |
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6 | * |
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7 | * Permission to use, copy, modify, and/or distribute this software for any |
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8 | * purpose with or without fee is hereby granted, provided that the above |
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9 | * copyright notice and this permission notice appear in all copies. |
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10 | * |
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11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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18 | * |
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19 | */ |
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20 | |||
21 | #include <linux/irq.h> |
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22 | #include <linux/pci.h> |
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23 | #include <linux/phy.h> |
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24 | #include <linux/platform_device.h> |
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25 | #include <linux/ath9k_platform.h> |
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26 | #include <linux/ar8216_platform.h> |
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27 | #include <linux/export.h> |
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28 | |||
29 | #include <asm/mach-ath79/ar71xx_regs.h> |
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30 | |||
31 | #include "pci.h" |
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32 | #include "common.h" |
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33 | #include "dev-ap9x-pci.h" |
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34 | #include "dev-eth.h" |
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35 | #include "dev-gpio-buttons.h" |
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36 | #include "dev-leds-gpio.h" |
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37 | #include "dev-m25p80.h" |
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38 | #include "dev-nfc.h" |
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39 | #include "dev-spi.h" |
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40 | #include "dev-usb.h" |
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41 | #include "dev-wmac.h" |
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42 | #include "machtypes.h" |
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43 | |||
44 | #define WPJ342_GPIO_LED_STATUS 11 |
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45 | #define WPJ342_GPIO_LED_SIG1 14 |
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46 | #define WPJ342_GPIO_LED_SIG2 13 |
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47 | #define WPJ342_GPIO_LED_SIG3 12 |
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48 | #define WPJ342_GPIO_LED_SIG4 11 |
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49 | #define WPJ342_GPIO_BUZZER 15 |
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50 | |||
51 | #define WPJ342_GPIO_BTN_RESET 17 |
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52 | |||
53 | #define WPJ342_KEYS_POLL_INTERVAL 20 /* msecs */ |
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54 | #define WPJ342_KEYS_DEBOUNCE_INTERVAL (3 * WPJ342_KEYS_POLL_INTERVAL) |
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55 | |||
56 | #define WPJ342_MAC0_OFFSET 0x10 |
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57 | #define WPJ342_MAC1_OFFSET 0x18 |
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58 | #define WPJ342_WMAC_CALDATA_OFFSET 0x1000 |
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59 | #define WPJ342_PCIE_CALDATA_OFFSET 0x5000 |
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60 | |||
61 | #define WPJ342_ART_SIZE 0x8000 |
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62 | |||
63 | static struct gpio_led wpj342_leds_gpio[] __initdata = { |
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64 | { |
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65 | .name = "wpj342:red:sig1", |
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66 | .gpio = WPJ342_GPIO_LED_SIG1, |
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67 | .active_low = 1, |
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68 | }, |
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69 | { |
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70 | .name = "wpj342:yellow:sig2", |
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71 | .gpio = WPJ342_GPIO_LED_SIG2, |
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72 | .active_low = 1, |
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73 | }, |
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74 | { |
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75 | .name = "wpj342:green:sig3", |
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76 | .gpio = WPJ342_GPIO_LED_SIG3, |
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77 | .active_low = 1, |
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78 | }, |
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79 | { |
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80 | .name = "wpj342:green:sig4", |
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81 | .gpio = WPJ342_GPIO_LED_SIG4, |
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82 | .active_low = 1, |
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83 | }, |
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84 | { |
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85 | .name = "wpj342:buzzer", |
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86 | .gpio = WPJ342_GPIO_BUZZER, |
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87 | .active_low = 0, |
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88 | } |
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89 | }; |
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90 | |||
91 | static struct gpio_keys_button wpj342_gpio_keys[] __initdata = { |
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92 | { |
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93 | .desc = "reset", |
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94 | .type = EV_KEY, |
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95 | .code = KEY_RESTART, |
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96 | .debounce_interval = WPJ342_KEYS_DEBOUNCE_INTERVAL, |
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97 | .gpio = WPJ342_GPIO_BTN_RESET, |
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98 | .active_low = 1, |
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99 | }, |
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100 | }; |
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101 | |||
102 | static struct ar8327_pad_cfg wpj342_ar8327_pad0_cfg = { |
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103 | .mode = AR8327_PAD_MAC_RGMII, |
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104 | .txclk_delay_en = true, |
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105 | .rxclk_delay_en = true, |
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106 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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107 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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108 | }; |
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109 | |||
110 | static struct ar8327_led_cfg wpj342_ar8327_led_cfg = { |
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111 | .led_ctrl0 = 0x00000000, |
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112 | .led_ctrl1 = 0xc737c737, |
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113 | .led_ctrl2 = 0x00000000, |
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114 | .led_ctrl3 = 0x00c30c00, |
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115 | .open_drain = true, |
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116 | }; |
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117 | |||
118 | static struct ar8327_platform_data wpj342_ar8327_data = { |
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119 | .pad0_cfg = &wpj342_ar8327_pad0_cfg, |
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120 | .port0_cfg = { |
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121 | .force_link = 1, |
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122 | .speed = AR8327_PORT_SPEED_1000, |
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123 | .duplex = 1, |
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124 | .txpause = 1, |
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125 | .rxpause = 1, |
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126 | }, |
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127 | .led_cfg = &wpj342_ar8327_led_cfg, |
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128 | }; |
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129 | |||
130 | static struct mdio_board_info wpj342_mdio0_info[] = { |
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131 | { |
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132 | .bus_id = "ag71xx-mdio.0", |
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133 | .mdio_addr = 0, |
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134 | .platform_data = &wpj342_ar8327_data, |
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135 | }, |
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136 | }; |
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137 | |||
138 | |||
139 | static void __init wpj342_setup(void) |
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140 | { |
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141 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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142 | u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000); |
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143 | |||
144 | ath79_register_m25p80(NULL); |
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145 | ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio), |
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146 | wpj342_leds_gpio); |
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147 | |||
148 | ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL, |
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149 | ARRAY_SIZE(wpj342_gpio_keys), |
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150 | wpj342_gpio_keys); |
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151 | |||
152 | ath79_register_usb(); |
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153 | |||
154 | ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL); |
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155 | |||
156 | ath79_register_pci(); |
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157 | |||
158 | mdiobus_register_board_info(wpj342_mdio0_info, |
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159 | ARRAY_SIZE(wpj342_mdio0_info)); |
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160 | |||
161 | ath79_register_mdio(1, 0x0); |
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162 | ath79_register_mdio(0, 0x0); |
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163 | |||
164 | ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0); |
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165 | ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0); |
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166 | |||
167 | ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0); |
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168 | |||
169 | /* GMAC0 is connected to an AR8236 switch */ |
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170 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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171 | ath79_eth0_data.phy_mask = BIT(0); |
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172 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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173 | ath79_eth0_pll_data.pll_1000 = 0x06000000; |
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174 | |||
175 | ath79_register_eth(0); |
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176 | } |
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177 | |||
178 | MIPS_MACHINE(ATH79_MACH_WPJ342, "WPJ342", "Compex WPJ342", wpj342_setup); |