OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * DomyWifi DW33D support |
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3 | * |
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4 | * Copyright (c) 2012 Qualcomm Atheros |
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5 | * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org> |
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6 | * |
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7 | * Permission to use, copy, modify, and/or distribute this software for any |
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8 | * purpose with or without fee is hereby granted, provided that the above |
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9 | * copyright notice and this permission notice appear in all copies. |
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10 | * |
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11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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18 | * |
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19 | */ |
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20 | |||
21 | #include <linux/version.h> |
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22 | #include <linux/platform_device.h> |
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23 | #include <linux/ar8216_platform.h> |
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24 | #include <linux/mtd/mtd.h> |
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25 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0) |
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26 | #include <linux/mtd/nand.h> |
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27 | #else |
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28 | #include <linux/mtd/rawnand.h> |
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29 | #endif |
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30 | #include <linux/platform/ar934x_nfc.h> |
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31 | |||
32 | #include <asm/mach-ath79/ar71xx_regs.h> |
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33 | |||
34 | #include "common.h" |
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35 | #include "pci.h" |
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36 | #include "dev-ap9x-pci.h" |
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37 | #include "dev-gpio-buttons.h" |
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38 | #include "dev-eth.h" |
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39 | #include "dev-leds-gpio.h" |
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40 | #include "dev-m25p80.h" |
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41 | #include "dev-nfc.h" |
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42 | #include "dev-usb.h" |
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43 | #include "dev-wmac.h" |
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44 | #include "machtypes.h" |
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45 | |||
46 | #define DW33D_GPIO_LED_MMC 4 |
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47 | #define DW33D_GPIO_LED_WLAN_2G 13 |
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48 | #define DW33D_GPIO_LED_STATUS 14 |
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49 | #define DW33D_GPIO_LED_USB 15 |
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50 | #define DW33D_GPIO_LED_INTERNET 22 |
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51 | |||
52 | #define DW33D_GPIO_BTN_RESET 17 |
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53 | |||
54 | #define DW33D_KEYS_POLL_INTERVAL 20 /* msecs */ |
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55 | #define DW33D_KEYS_DEBOUNCE_INTERVAL (3 * DW33D_KEYS_POLL_INTERVAL) |
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56 | |||
57 | #define DW33D_MAC0_OFFSET 0 |
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58 | #define DW33D_MAC1_OFFSET 6 |
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59 | #define DW33D_WMAC_OFFSET 12 |
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60 | #define DW33D_WMAC_CALDATA_OFFSET 0x1000 |
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61 | #define DW33D_PCIE_CALDATA_OFFSET 0x5000 |
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62 | |||
63 | static struct gpio_led dw33d_leds_gpio[] __initdata = { |
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64 | { |
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65 | .name = "dw33d:blue:status", |
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66 | .gpio = DW33D_GPIO_LED_STATUS, |
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67 | .active_low = 1, |
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68 | }, |
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69 | { |
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70 | .name = "dw33d:blue:mmc", |
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71 | .gpio = DW33D_GPIO_LED_MMC, |
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72 | .active_low = 1, |
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73 | }, |
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74 | { |
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75 | .name = "dw33d:blue:usb", |
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76 | .gpio = DW33D_GPIO_LED_USB, |
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77 | .active_low = 1, |
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78 | }, |
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79 | { |
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80 | .name = "dw33d:blue:wlan-2g", |
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81 | .gpio = DW33D_GPIO_LED_WLAN_2G, |
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82 | .active_low = 1, |
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83 | }, |
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84 | { |
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85 | .name = "dw33d:blue:internet", |
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86 | .gpio = DW33D_GPIO_LED_INTERNET, |
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87 | .active_low = 1, |
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88 | } |
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89 | }; |
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90 | |||
91 | static struct gpio_keys_button dw33d_gpio_keys[] __initdata = { |
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92 | { |
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93 | .desc = "Reset button", |
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94 | .type = EV_KEY, |
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95 | .code = KEY_RESTART, |
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96 | .debounce_interval = DW33D_KEYS_DEBOUNCE_INTERVAL, |
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97 | .gpio = DW33D_GPIO_BTN_RESET, |
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98 | .active_low = 1, |
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99 | } |
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100 | }; |
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101 | |||
102 | /* GMAC6 of the QCA8337 switch is connected to the QCA9558 SoC via SGMII */ |
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103 | static struct ar8327_pad_cfg dw33d_qca8337_pad6_cfg = { |
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104 | .mode = AR8327_PAD_MAC_SGMII, |
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105 | .sgmii_delay_en = true, |
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106 | }; |
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107 | |||
108 | /* GMAC0 of the QCA8337 switch is connected to the QCA9558 SoC via RGMII */ |
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109 | static struct ar8327_pad_cfg dw33d_qca8337_pad0_cfg = { |
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110 | .mode = AR8327_PAD_MAC_RGMII, |
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111 | .txclk_delay_en = true, |
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112 | .rxclk_delay_en = true, |
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113 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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114 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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115 | }; |
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116 | |||
117 | static struct ar8327_platform_data dw33d_qca8337_data = { |
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118 | .pad0_cfg = &dw33d_qca8337_pad0_cfg, |
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119 | .pad6_cfg = &dw33d_qca8337_pad6_cfg, |
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120 | .port0_cfg = { |
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121 | .force_link = 1, |
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122 | .speed = AR8327_PORT_SPEED_1000, |
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123 | .duplex = 1, |
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124 | .txpause = 1, |
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125 | .rxpause = 1, |
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126 | }, |
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127 | .port6_cfg = { |
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128 | .force_link = 1, |
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129 | .speed = AR8327_PORT_SPEED_1000, |
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130 | .duplex = 1, |
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131 | .txpause = 1, |
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132 | .rxpause = 1, |
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133 | }, |
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134 | }; |
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135 | |||
136 | static struct mdio_board_info dw33d_mdio0_info[] = { |
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137 | { |
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138 | .bus_id = "ag71xx-mdio.0", |
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139 | .mdio_addr = 0, |
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140 | .platform_data = &dw33d_qca8337_data, |
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141 | }, |
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142 | }; |
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143 | |||
144 | static void __init dw33d_setup(void) |
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145 | { |
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146 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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147 | |||
148 | ath79_register_m25p80(NULL); |
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149 | |||
150 | ath79_register_leds_gpio(-1, ARRAY_SIZE(dw33d_leds_gpio), |
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151 | dw33d_leds_gpio); |
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152 | ath79_register_gpio_keys_polled(-1, DW33D_KEYS_POLL_INTERVAL, |
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153 | ARRAY_SIZE(dw33d_gpio_keys), |
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154 | dw33d_gpio_keys); |
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155 | |||
156 | ath79_register_usb(); |
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157 | ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW); |
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158 | ath79_register_nfc(); |
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159 | ath79_register_pci(); |
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160 | |||
161 | ath79_register_wmac(art + DW33D_WMAC_CALDATA_OFFSET, art + DW33D_WMAC_OFFSET); |
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162 | |||
163 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
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164 | |||
165 | ath79_register_mdio(0, 0x0); |
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166 | |||
167 | ath79_init_mac(ath79_eth0_data.mac_addr, art + DW33D_MAC0_OFFSET, 0); |
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168 | ath79_init_mac(ath79_eth1_data.mac_addr, art + DW33D_MAC1_OFFSET, 0); |
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169 | |||
170 | mdiobus_register_board_info(dw33d_mdio0_info, |
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171 | ARRAY_SIZE(dw33d_mdio0_info)); |
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172 | |||
173 | /* GMAC0 is connected to the RMGII interface */ |
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174 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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175 | ath79_eth0_data.phy_mask = BIT(0); |
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176 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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177 | ath79_eth0_pll_data.pll_1000 = 0x56000000; |
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178 | |||
179 | ath79_register_eth(0); |
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180 | |||
181 | /* GMAC1 is connected tot eh SGMII interface */ |
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182 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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183 | ath79_eth1_data.speed = SPEED_1000; |
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184 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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185 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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186 | |||
187 | ath79_register_eth(1); |
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188 | } |
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189 | |||
190 | MIPS_MACHINE(ATH79_MACH_DOMYWIFI_DW33D, "DW33D", |
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191 | "DomyWifi DW33D", |
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192 | dw33d_setup); |