OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- /dev/null |
2 | +++ b/board/arcadyan/vgv7510kw22/Makefile |
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3 | @@ -0,0 +1,27 @@ |
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4 | +# |
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5 | +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de |
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6 | +# |
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7 | +# SPDX-License-Identifier: GPL-2.0+ |
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8 | +# |
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9 | + |
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10 | +include $(TOPDIR)/config.mk |
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11 | + |
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12 | +LIB = $(obj)lib$(BOARD).o |
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13 | + |
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14 | +COBJS = $(BOARD).o |
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15 | + |
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16 | +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) |
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17 | +OBJS := $(addprefix $(obj),$(COBJS)) |
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18 | +SOBJS := $(addprefix $(obj),$(SOBJS)) |
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19 | + |
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20 | +$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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21 | + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) |
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22 | + |
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23 | +######################################################################### |
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24 | + |
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25 | +# defines $(obj).depend target |
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26 | +include $(SRCTREE)/rules.mk |
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27 | + |
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28 | +sinclude $(obj).depend |
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29 | + |
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30 | +######################################################################### |
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31 | --- /dev/null |
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32 | +++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c |
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33 | @@ -0,0 +1,116 @@ |
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34 | +/* |
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35 | + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
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36 | + * |
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37 | + * SPDX-License-Identifier: GPL-2.0+ |
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38 | + */ |
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39 | + |
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40 | +#include <common.h> |
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41 | +#include <asm/gpio.h> |
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42 | +#include <asm/lantiq/eth.h> |
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43 | +#include <asm/lantiq/chipid.h> |
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44 | +#include <asm/lantiq/cpu.h> |
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45 | +#include <asm/arch/gphy.h> |
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46 | + |
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47 | +#if defined(CONFIG_SYS_BOOT_RAM) |
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48 | +#define do_gpio_init 1 |
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49 | +#define do_pll_init 0 |
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50 | +#define do_dcdc_init 1 |
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51 | +#elif defined(CONFIG_SYS_BOOT_NOR) |
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52 | +#define do_gpio_init 1 |
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53 | +#define do_pll_init 1 |
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54 | +#define do_dcdc_init 1 |
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55 | +#else |
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56 | +#define do_gpio_init 0 |
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57 | +#define do_pll_init 0 |
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58 | +#define do_dcdc_init 1 |
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59 | +#endif |
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60 | + |
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61 | +#define GPIO_POWER_GREEN 14 |
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62 | +#define GPIO_POWER_RED 28 |
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63 | + |
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64 | +static void gpio_init(void) |
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65 | +{ |
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66 | + /* Turn on the green power LED */ |
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67 | + gpio_direction_output(GPIO_POWER_GREEN, 0); |
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68 | + |
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69 | + /* Turn off the red power LED */ |
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70 | + gpio_direction_output(GPIO_POWER_RED, 1); |
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71 | +} |
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72 | + |
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73 | +int board_early_init_f(void) |
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74 | +{ |
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75 | + if (do_gpio_init) |
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76 | + gpio_init(); |
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77 | + |
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78 | + if (do_pll_init) |
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79 | + ltq_pll_init(); |
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80 | + |
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81 | + if (do_dcdc_init) |
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82 | + ltq_dcdc_init(0x7F); |
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83 | + |
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84 | + return 0; |
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85 | +} |
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86 | + |
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87 | +int checkboard(void) |
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88 | +{ |
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89 | + puts("Board: " CONFIG_BOARD_NAME "\n"); |
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90 | + ltq_chip_print_info(); |
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91 | + |
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92 | + return 0; |
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93 | +} |
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94 | + |
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95 | +void show_boot_progress(int arg) |
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96 | +{ |
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97 | + if (!do_gpio_init) |
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98 | + return 0; |
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99 | + |
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100 | + if (arg >= 0) { |
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101 | + /* Success - turn off the red power LED and turn on the green power LED */ |
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102 | + gpio_set_value(GPIO_POWER_RED, 1); |
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103 | + gpio_set_value(GPIO_POWER_GREEN, 0); |
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104 | + } else { |
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105 | + /* Failure - turn off green power LED and turn on red power LED */ |
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106 | + gpio_set_value(GPIO_POWER_GREEN, 1); |
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107 | + gpio_set_value(GPIO_POWER_RED, 0); |
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108 | + } |
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109 | + |
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110 | + return 0; |
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111 | +} |
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112 | + |
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113 | +static const struct ltq_eth_port_config eth_port_config[] = { |
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114 | + /* unused */ |
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115 | + { 0, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, |
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116 | + /* unused */ |
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117 | + { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, |
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118 | + /* Internal GPHY0 with 10/100 firmware for LAN port 2 */ |
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119 | + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, |
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120 | + /* Internal GPHY0 with 10/100 firmware for LAN port 1 */ |
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121 | + { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, |
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122 | + /* Internal GPHY1 with 10/100 firmware for LAN port 4 */ |
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123 | + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, |
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124 | + /* Internal GPHY1 with 10/100 firmware for LAN port 3 */ |
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125 | + { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, |
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126 | +}; |
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127 | + |
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128 | +static const struct ltq_eth_board_config eth_board_config = { |
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129 | + .ports = eth_port_config, |
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130 | + .num_ports = ARRAY_SIZE(eth_port_config), |
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131 | +}; |
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132 | + |
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133 | +int board_eth_init(bd_t * bis) |
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134 | +{ |
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135 | + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; |
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136 | + const ulong fw_addr = 0x80FF0000; |
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137 | + |
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138 | + if (ltq_chip_version_get() == 1) |
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139 | + ltq_gphy_phy22f_a1x_load(fw_addr); |
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140 | + else |
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141 | + ltq_gphy_phy22f_a2x_load(fw_addr); |
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142 | + |
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143 | + ltq_cgu_gphy_clk_src(clk); |
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144 | + |
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145 | + ltq_rcu_gphy_boot(0, fw_addr); |
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146 | + ltq_rcu_gphy_boot(1, fw_addr); |
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147 | + |
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148 | + return ltq_eth_initialize(ð_board_config); |
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149 | +} |
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150 | --- /dev/null |
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151 | +++ b/board/arcadyan/vgv7510kw22/config.mk |
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152 | @@ -0,0 +1,7 @@ |
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153 | +# |
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154 | +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com |
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155 | +# |
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156 | +# SPDX-License-Identifier: GPL-2.0+ |
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157 | +# |
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158 | + |
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159 | +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) |
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160 | --- /dev/null |
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161 | +++ b/board/arcadyan/vgv7510kw22/ddr_settings.h |
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162 | @@ -0,0 +1,71 @@ |
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163 | +/* |
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164 | + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
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165 | + * Copyright (C) 2016 Mathias Kresin <dev@kresin.me> |
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166 | + * |
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167 | + * The values have been extracted from original brnboot. |
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168 | + * |
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169 | + * SPDX-License-Identifier: GPL-2.0+ |
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170 | + */ |
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171 | + |
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172 | +#define MC_CCR00_VALUE 0x101 |
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173 | +#define MC_CCR01_VALUE 0x1000100 |
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174 | +#define MC_CCR02_VALUE 0x1010000 |
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175 | +#define MC_CCR03_VALUE 0x100 |
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176 | +#define MC_CCR04_VALUE 0x1000000 |
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177 | +#define MC_CCR05_VALUE 0x1000101 |
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178 | +#define MC_CCR06_VALUE 0x1000100 |
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179 | +#define MC_CCR07_VALUE 0x1010000 |
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180 | +#define MC_CCR08_VALUE 0x1000101 |
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181 | +#define MC_CCR09_VALUE 0x0 |
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182 | +#define MC_CCR10_VALUE 0x2000100 |
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183 | +#define MC_CCR11_VALUE 0x2000401 |
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184 | +#define MC_CCR12_VALUE 0x30000 |
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185 | +#define MC_CCR13_VALUE 0x202 |
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186 | +#define MC_CCR14_VALUE 0x7080A0F |
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187 | +#define MC_CCR15_VALUE 0x2040F |
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188 | +#define MC_CCR16_VALUE 0x40000 |
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189 | +#define MC_CCR17_VALUE 0x70102 |
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190 | +#define MC_CCR18_VALUE 0x4020002 |
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191 | +#define MC_CCR19_VALUE 0x30302 |
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192 | +#define MC_CCR20_VALUE 0x8000700 |
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193 | +#define MC_CCR21_VALUE 0x40F020A |
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194 | +#define MC_CCR22_VALUE 0x0 |
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195 | +#define MC_CCR23_VALUE 0xC020000 |
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196 | +#define MC_CCR24_VALUE 0x4401B04 |
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197 | +#define MC_CCR25_VALUE 0x0 |
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198 | +#define MC_CCR26_VALUE 0x0 |
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199 | +#define MC_CCR27_VALUE 0x6420000 |
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200 | +#define MC_CCR28_VALUE 0x0 |
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201 | +#define MC_CCR29_VALUE 0x0 |
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202 | +#define MC_CCR30_VALUE 0x798 |
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203 | +#define MC_CCR31_VALUE 0x2040F |
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204 | +#define MC_CCR32_VALUE 0x0 |
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205 | +#define MC_CCR33_VALUE 0x650000 |
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206 | +#define MC_CCR34_VALUE 0x200C8 |
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207 | +#define MC_CCR35_VALUE 0x1D445D |
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208 | +#define MC_CCR36_VALUE 0xC8 |
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209 | +#define MC_CCR37_VALUE 0xC351 |
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210 | +#define MC_CCR38_VALUE 0x0 |
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211 | +#define MC_CCR39_VALUE 0x141F04 |
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212 | +#define MC_CCR40_VALUE 0x142704 |
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213 | +#define MC_CCR41_VALUE 0x141B42 |
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214 | +#define MC_CCR42_VALUE 0x141B42 |
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215 | +#define MC_CCR43_VALUE 0x566504 |
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216 | +#define MC_CCR44_VALUE 0x566504 |
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217 | +#define MC_CCR45_VALUE 0x565F17 |
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218 | +#define MC_CCR46_VALUE 0x565F17 |
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219 | +#define MC_CCR47_VALUE 0x2040F |
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220 | +#define MC_CCR48_VALUE 0x0 |
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221 | +#define MC_CCR49_VALUE 0x0 |
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222 | +#define MC_CCR50_VALUE 0x0 |
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223 | +#define MC_CCR51_VALUE 0x0 |
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224 | +#define MC_CCR52_VALUE 0x133 |
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225 | +#define MC_CCR53_VALUE 0xF3014B27 |
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226 | +#define MC_CCR54_VALUE 0xF3014B27 |
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227 | +#define MC_CCR55_VALUE 0xF3014B27 |
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228 | +#define MC_CCR56_VALUE 0xF3014B27 |
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229 | +#define MC_CCR57_VALUE 0x7800301 |
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230 | +#define MC_CCR58_VALUE 0x7800301 |
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231 | +#define MC_CCR59_VALUE 0x7800301 |
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232 | +#define MC_CCR60_VALUE 0x7800301 |
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233 | +#define MC_CCR61_VALUE 0x4 |
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234 | --- a/boards.cfg |
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235 | +++ b/boards.cfg |
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236 | @@ -531,6 +531,9 @@ Active mips mips32 incai |
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237 | Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> |
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238 | Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> |
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239 | Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> |
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240 | +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
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241 | +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
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242 | +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
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243 | Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
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244 | Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
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245 | Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
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246 | --- /dev/null |
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247 | +++ b/include/configs/vgv7510kw22.h |
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248 | @@ -0,0 +1,59 @@ |
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249 | +/* |
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250 | + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com> |
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251 | + * |
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252 | + * SPDX-License-Identifier: GPL-2.0+ |
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253 | + */ |
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254 | + |
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255 | +#ifndef __CONFIG_H |
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256 | +#define __CONFIG_H |
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257 | + |
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258 | +#define CONFIG_MACH_TYPE "VGV7510KW22" |
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259 | +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE |
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260 | +#define CONFIG_BOARD_NAME "Arcadyan VGV7510KW22" |
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261 | + |
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262 | +/* Configure SoC */ |
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263 | +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ |
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264 | + |
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265 | +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ |
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266 | + |
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267 | +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ |
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268 | + |
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269 | +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */ |
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270 | + |
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271 | +#if defined(CONFIG_SYS_BOOT_BRN) |
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272 | +#define CONFIG_SYS_TEXT_BASE 0x80002000 |
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273 | +#define CONFIG_SKIP_LOWLEVEL_INIT |
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274 | +#define CONFIG_SYS_DISABLE_CACHE |
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275 | +#define CONFIG_ENV_IS_NOWHERE |
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276 | +#define CONFIG_ENV_OVERWRITE 1 |
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277 | +#elif defined(CONFIG_SYS_BOOT_NOR) |
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278 | +#define CONFIG_ENV_IS_IN_FLASH |
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279 | +#define CONFIG_ENV_OVERWRITE |
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280 | +#define CONFIG_ENV_OFFSET (384 * 1024) |
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281 | +#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
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282 | +#else |
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283 | +#define CONFIG_ENV_IS_NOWHERE |
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284 | +#endif |
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285 | + |
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286 | +#define CONFIG_ENV_SIZE (128 * 1024) |
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287 | + |
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288 | +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR |
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289 | + |
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290 | +/* Console */ |
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291 | +#define CONFIG_LTQ_ADVANCED_CONSOLE |
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292 | +#define CONFIG_BAUDRATE 115200 |
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293 | +#define CONFIG_CONSOLE_ASC 1 |
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294 | +#define CONFIG_CONSOLE_DEV "ttyLTQ1" |
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295 | + |
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296 | +/* Pull in default board configs for Lantiq XWAY VRX200 */ |
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297 | +#include <asm/lantiq/config.h> |
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298 | +#include <asm/arch/config.h> |
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299 | + |
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300 | +/* Pull in default OpenWrt configs for Lantiq SoC */ |
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301 | +#include "openwrt-lantiq-common.h" |
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302 | + |
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303 | +#define CONFIG_EXTRA_ENV_SETTINGS \ |
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304 | + CONFIG_ENV_LANTIQ_DEFAULTS \ |
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305 | + "kernel_addr=0xB0080000\0" |
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306 | + |
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307 | +#endif /* __CONFIG_H */ |