OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 927c736a1a169713cd59140db5e82f8ed11dad60 Mon Sep 17 00:00:00 2001 |
2 | From: Sean Wang <sean.wang@mediatek.com> |
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3 | Date: Fri, 29 Dec 2017 11:06:52 +0800 |
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4 | Subject: [PATCH 212/224] arm64: dts: mt7622: add pinctrl related device nodes |
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5 | |||
6 | add pinctrl device nodes and rfb1 board, additionally include all pin |
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7 | groups possible being used on rfb1 board and available gpio keys. |
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8 | |||
9 | Signed-off-by: Sean Wang <sean.wang@mediatek.com> |
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10 | Cc: Matthias Brugger <matthias.bgg@gmail.com> |
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11 | --- |
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12 | arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 200 +++++++++++++++++++++++++++ |
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13 | arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 + |
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14 | 2 files changed, 207 insertions(+) |
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15 | |||
16 | --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |
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17 | +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |
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18 | @@ -7,6 +7,8 @@ |
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19 | */ |
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20 | |||
21 | /dts-v1/; |
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22 | +#include <dt-bindings/input/input.h> |
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23 | + |
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24 | #include "mt7622.dtsi" |
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25 | |||
26 | / { |
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27 | @@ -17,11 +19,209 @@ |
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28 | bootargs = "console=ttyS0,115200n1"; |
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29 | }; |
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30 | |||
31 | + gpio-keys { |
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32 | + compatible = "gpio-keys-polled"; |
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33 | + poll-interval = <100>; |
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34 | + |
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35 | + factory { |
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36 | + label = "factory"; |
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37 | + linux,code = <BTN_0>; |
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38 | + gpios = <&pio 0 0>; |
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39 | + }; |
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40 | + |
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41 | + wps { |
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42 | + label = "wps"; |
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43 | + linux,code = <KEY_WPS_BUTTON>; |
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44 | + gpios = <&pio 102 0>; |
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45 | + }; |
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46 | + }; |
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47 | + |
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48 | memory { |
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49 | reg = <0 0x40000000 0 0x3F000000>; |
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50 | }; |
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51 | }; |
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52 | |||
53 | +&pio { |
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54 | + /* eMMC is shared pin with parallel NAND */ |
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55 | + emmc_pins_default: emmc-pins-default { |
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56 | + mux { |
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57 | + function = "emmc", "emmc_rst"; |
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58 | + groups = "emmc"; |
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59 | + }; |
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60 | + }; |
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61 | + |
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62 | + emmc_pins_uhs: emmc-pins-uhs { |
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63 | + mux { |
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64 | + function = "emmc"; |
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65 | + groups = "emmc"; |
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66 | + }; |
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67 | + }; |
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68 | + |
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69 | + eth_pins: eth-pins { |
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70 | + mux { |
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71 | + function = "eth"; |
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72 | + groups = "mdc_mdio", "rgmii_via_gmac2"; |
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73 | + }; |
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74 | + }; |
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75 | + |
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76 | + i2c1_pins: i2c1-pins { |
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77 | + mux { |
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78 | + function = "i2c"; |
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79 | + groups = "i2c1_0"; |
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80 | + }; |
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81 | + }; |
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82 | + |
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83 | + i2c2_pins: i2c2-pins { |
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84 | + mux { |
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85 | + function = "i2c"; |
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86 | + groups = "i2c2_0"; |
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87 | + }; |
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88 | + }; |
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89 | + |
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90 | + i2s1_pins: i2s1-pins { |
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91 | + mux { |
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92 | + function = "i2s"; |
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93 | + groups = "i2s_out_bclk_ws_mclk", |
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94 | + "i2s1_in_data", |
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95 | + "i2s1_out_data"; |
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96 | + }; |
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97 | + }; |
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98 | + |
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99 | + irrx_pins: irrx-pins { |
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100 | + mux { |
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101 | + function = "ir"; |
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102 | + groups = "ir_1_rx"; |
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103 | + }; |
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104 | + }; |
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105 | + |
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106 | + irtx_pins: irtx-pins { |
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107 | + mux { |
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108 | + function = "ir"; |
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109 | + groups = "ir_1_tx"; |
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110 | + }; |
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111 | + }; |
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112 | + |
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113 | + /* Parallel nand is shared pin with eMMC */ |
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114 | + parallel_nand_pins: parallel-nand-pins { |
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115 | + mux { |
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116 | + function = "flash"; |
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117 | + groups = "par_nand"; |
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118 | + }; |
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119 | + }; |
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120 | + |
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121 | + pcie0_pins: pcie0-pins { |
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122 | + mux { |
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123 | + function = "pcie"; |
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124 | + groups = "pcie0_pad_perst", |
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125 | + "pcie0_1_waken", |
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126 | + "pcie0_1_clkreq"; |
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127 | + }; |
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128 | + }; |
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129 | + |
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130 | + pcie1_pins: pcie1-pins { |
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131 | + mux { |
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132 | + function = "pcie"; |
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133 | + groups = "pcie1_pad_perst", |
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134 | + "pcie1_0_waken", |
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135 | + "pcie1_0_clkreq"; |
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136 | + }; |
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137 | + }; |
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138 | + |
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139 | + pmic_bus_pins: pmic-bus-pins { |
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140 | + mux { |
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141 | + function = "pmic"; |
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142 | + groups = "pmic_bus"; |
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143 | + }; |
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144 | + }; |
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145 | + |
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146 | + pwm7_pins: pwm1-2-pins { |
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147 | + mux { |
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148 | + function = "pwm"; |
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149 | + groups = "pwm_ch7_2"; |
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150 | + }; |
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151 | + }; |
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152 | + |
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153 | + wled_pins: wled-pins { |
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154 | + mux { |
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155 | + function = "led"; |
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156 | + groups = "wled"; |
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157 | + }; |
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158 | + }; |
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159 | + |
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160 | + sd0_pins_default: sd0-pins-default { |
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161 | + mux { |
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162 | + function = "sd"; |
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163 | + groups = "sd_0"; |
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164 | + }; |
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165 | + }; |
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166 | + |
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167 | + sd0_pins_uhs: sd0-pins-uhs { |
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168 | + mux { |
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169 | + function = "sd"; |
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170 | + groups = "sd_0"; |
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171 | + }; |
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172 | + }; |
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173 | + |
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174 | + /* Serial NAND is shared pin with SPI-NOR */ |
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175 | + serial_nand_pins: serial-nand-pins { |
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176 | + mux { |
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177 | + function = "flash"; |
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178 | + groups = "snfi"; |
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179 | + }; |
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180 | + }; |
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181 | + |
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182 | + spic0_pins: spic0-pins { |
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183 | + mux { |
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184 | + function = "spi"; |
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185 | + groups = "spic0_0"; |
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186 | + }; |
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187 | + }; |
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188 | + |
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189 | + spic1_pins: spic1-pins { |
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190 | + mux { |
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191 | + function = "spi"; |
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192 | + groups = "spic1_0"; |
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193 | + }; |
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194 | + }; |
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195 | + |
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196 | + /* SPI-NOR is shared pin with serial NAND */ |
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197 | + spi_nor_pins: spi-nor-pins { |
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198 | + mux { |
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199 | + function = "flash"; |
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200 | + groups = "spi_nor"; |
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201 | + }; |
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202 | + }; |
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203 | + |
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204 | + /* serial NAND is shared pin with SPI-NOR */ |
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205 | + serial_nand_pins: serial-nand-pins { |
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206 | + mux { |
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207 | + function = "flash"; |
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208 | + groups = "snfi"; |
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209 | + }; |
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210 | + }; |
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211 | + |
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212 | + uart0_pins: uart0-pins { |
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213 | + mux { |
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214 | + function = "uart"; |
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215 | + groups = "uart0_0_tx_rx" ; |
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216 | + }; |
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217 | + }; |
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218 | + |
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219 | + uart2_pins: uart2-pins { |
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220 | + mux { |
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221 | + function = "uart"; |
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222 | + groups = "uart2_1_tx_rx" ; |
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223 | + }; |
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224 | + }; |
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225 | + |
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226 | + watchdog_pins: watchdog-pins { |
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227 | + mux { |
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228 | + function = "watchdog"; |
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229 | + groups = "watchdog"; |
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230 | + }; |
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231 | + }; |
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232 | +}; |
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233 | + |
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234 | &uart0 { |
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235 | status = "okay"; |
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236 | }; |
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237 | --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
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238 | +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi |
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239 | @@ -147,6 +147,13 @@ |
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240 | #clock-cells = <1>; |
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241 | }; |
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242 | |||
243 | + pio: pinctrl@10211000 { |
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244 | + compatible = "mediatek,mt7622-pinctrl"; |
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245 | + reg = <0 0x10211000 0 0x1000>; |
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246 | + gpio-controller; |
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247 | + #gpio-cells = <2>; |
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248 | + }; |
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249 | + |
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250 | gic: interrupt-controller@10300000 { |
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251 | compatible = "arm,gic-400"; |
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252 | interrupt-controller; |