OpenWrt – Blame information for rev 4
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Rev | Author | Line No. | Line |
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4 | office | 1 | From 4e4c2d695a5daf6dc55b8713af720ef15b52c0e7 Mon Sep 17 00:00:00 2001 |
2 | From: Sean Wang <sean.wang@mediatek.com> |
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3 | Date: Tue, 12 Dec 2017 14:24:18 +0800 |
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4 | Subject: [PATCH 169/224] dt-bindings: pinctrl: add bindings for MediaTek |
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5 | MT7622 SoC |
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6 | |||
7 | Add devicetree bindings for MediaTek MT7622 pinctrl driver. |
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8 | |||
9 | Signed-off-by: Sean Wang <sean.wang@mediatek.com> |
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10 | Reviewed-by: Biao Huang <biao.huang@mediatek.com> |
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11 | Acked-by: Rob Herring <robh@kernel.org> |
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12 | Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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13 | --- |
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14 | .../devicetree/bindings/pinctrl/pinctrl-mt7622.txt | 351 +++++++++++++++++++++ |
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15 | 1 file changed, 351 insertions(+) |
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16 | create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt |
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17 | |||
18 | --- /dev/null |
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19 | +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt |
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20 | @@ -0,0 +1,351 @@ |
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21 | +== MediaTek MT7622 pinctrl controller == |
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22 | + |
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23 | +Required properties for the root node: |
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24 | + - compatible: Should be one of the following |
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25 | + "mediatek,mt7622-pinctrl" for MT7622 SoC |
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26 | + - reg: offset and length of the pinctrl space |
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27 | + |
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28 | + - gpio-controller: Marks the device node as a GPIO controller. |
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29 | + - #gpio-cells: Should be two. The first cell is the pin number and the |
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30 | + second is the GPIO flags. |
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31 | + |
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32 | +Please refer to pinctrl-bindings.txt in this directory for details of the |
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33 | +common pinctrl bindings used by client devices, including the meaning of the |
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34 | +phrase "pin configuration node". |
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35 | + |
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36 | +MT7622 pin configuration nodes act as a container for an arbitrary number of |
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37 | +subnodes. Each of these subnodes represents some desired configuration for a |
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38 | +pin, a group, or a list of pins or groups. This configuration can include the |
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39 | +mux function to select on those pin(s)/group(s), and various pin configuration |
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40 | +parameters, such as pull-up, slew rate, etc. |
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41 | + |
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42 | +We support 2 types of configuration nodes. Those nodes can be either pinmux |
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43 | +nodes or pinconf nodes. Each configuration node can consist of multiple nodes |
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44 | +describing the pinmux and pinconf options. |
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45 | + |
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46 | +The name of each subnode doesn't matter as long as it is unique; all subnodes |
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47 | +should be enumerated and processed purely based on their content. |
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48 | + |
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49 | +== pinmux nodes content == |
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50 | + |
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51 | +The following generic properties as defined in pinctrl-bindings.txt are valid |
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52 | +to specify in a pinmux subnode: |
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53 | + |
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54 | +Required properties are: |
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55 | + - groups: An array of strings. Each string contains the name of a group. |
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56 | + Valid values for these names are listed below. |
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57 | + - function: A string containing the name of the function to mux to the |
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58 | + group. Valid values for function names are listed below. |
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59 | + |
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60 | +== pinconf nodes content == |
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61 | + |
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62 | +The following generic properties as defined in pinctrl-bindings.txt are valid |
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63 | +to specify in a pinconf subnode: |
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64 | + |
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65 | +Required properties are: |
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66 | + - pins: An array of strings. Each string contains the name of a pin. |
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67 | + Valid values for these names are listed below. |
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68 | + - groups: An array of strings. Each string contains the name of a group. |
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69 | + Valid values for these names are listed below. |
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70 | + |
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71 | +Optional properies are: |
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72 | + bias-disable, bias-pull, bias-pull-down, input-enable, |
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73 | + input-schmitt-enable, input-schmitt-disable, output-enable |
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74 | + output-low, output-high, drive-strength, slew-rate |
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75 | + |
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76 | + Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for |
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77 | + slower slew rate respectively. |
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78 | + Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA. |
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79 | + |
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80 | +The following specific properties as defined are valid to specify in a pinconf |
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81 | +subnode: |
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82 | + |
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83 | +Optional properties are: |
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84 | + - mediatek,tdsel: An integer describing the steps for output level shifter duty |
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85 | + cycle when asserted (high pulse width adjustment). Valid arguments are from 0 |
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86 | + to 15. |
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87 | + - mediatek,rdsel: An integer describing the steps for input level shifter duty |
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88 | + cycle when asserted (high pulse width adjustment). Valid arguments are from 0 |
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89 | + to 63. |
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90 | + |
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91 | +== Valid values for pins, function and groups on MT7622 == |
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92 | + |
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93 | +Valid values for pins are: |
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94 | +pins can be referenced via the pin names as the below table shown and the |
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95 | +related physical number is also put ahead of those names which helps cross |
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96 | +references to pins between groups to know whether pins assignment conflict |
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97 | +happens among devices try to acquire those available pins. |
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98 | + |
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99 | + Pin #: Valid values for pins |
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100 | + ----------------------------- |
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101 | + PIN 0: "GPIO_A" |
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102 | + PIN 1: "I2S1_IN" |
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103 | + PIN 2: "I2S1_OUT" |
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104 | + PIN 3: "I2S_BCLK" |
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105 | + PIN 4: "I2S_WS" |
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106 | + PIN 5: "I2S_MCLK" |
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107 | + PIN 6: "TXD0" |
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108 | + PIN 7: "RXD0" |
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109 | + PIN 8: "SPI_WP" |
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110 | + PIN 9: "SPI_HOLD" |
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111 | + PIN 10: "SPI_CLK" |
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112 | + PIN 11: "SPI_MOSI" |
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113 | + PIN 12: "SPI_MISO" |
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114 | + PIN 13: "SPI_CS" |
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115 | + PIN 14: "I2C_SDA" |
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116 | + PIN 15: "I2C_SCL" |
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117 | + PIN 16: "I2S2_IN" |
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118 | + PIN 17: "I2S3_IN" |
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119 | + PIN 18: "I2S4_IN" |
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120 | + PIN 19: "I2S2_OUT" |
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121 | + PIN 20: "I2S3_OUT" |
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122 | + PIN 21: "I2S4_OUT" |
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123 | + PIN 22: "GPIO_B" |
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124 | + PIN 23: "MDC" |
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125 | + PIN 24: "MDIO" |
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126 | + PIN 25: "G2_TXD0" |
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127 | + PIN 26: "G2_TXD1" |
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128 | + PIN 27: "G2_TXD2" |
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129 | + PIN 28: "G2_TXD3" |
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130 | + PIN 29: "G2_TXEN" |
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131 | + PIN 30: "G2_TXC" |
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132 | + PIN 31: "G2_RXD0" |
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133 | + PIN 32: "G2_RXD1" |
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134 | + PIN 33: "G2_RXD2" |
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135 | + PIN 34: "G2_RXD3" |
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136 | + PIN 35: "G2_RXDV" |
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137 | + PIN 36: "G2_RXC" |
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138 | + PIN 37: "NCEB" |
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139 | + PIN 38: "NWEB" |
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140 | + PIN 39: "NREB" |
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141 | + PIN 40: "NDL4" |
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142 | + PIN 41: "NDL5" |
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143 | + PIN 42: "NDL6" |
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144 | + PIN 43: "NDL7" |
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145 | + PIN 44: "NRB" |
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146 | + PIN 45: "NCLE" |
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147 | + PIN 46: "NALE" |
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148 | + PIN 47: "NDL0" |
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149 | + PIN 48: "NDL1" |
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150 | + PIN 49: "NDL2" |
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151 | + PIN 50: "NDL3" |
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152 | + PIN 51: "MDI_TP_P0" |
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153 | + PIN 52: "MDI_TN_P0" |
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154 | + PIN 53: "MDI_RP_P0" |
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155 | + PIN 54: "MDI_RN_P0" |
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156 | + PIN 55: "MDI_TP_P1" |
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157 | + PIN 56: "MDI_TN_P1" |
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158 | + PIN 57: "MDI_RP_P1" |
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159 | + PIN 58: "MDI_RN_P1" |
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160 | + PIN 59: "MDI_RP_P2" |
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161 | + PIN 60: "MDI_RN_P2" |
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162 | + PIN 61: "MDI_TP_P2" |
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163 | + PIN 62: "MDI_TN_P2" |
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164 | + PIN 63: "MDI_TP_P3" |
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165 | + PIN 64: "MDI_TN_P3" |
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166 | + PIN 65: "MDI_RP_P3" |
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167 | + PIN 66: "MDI_RN_P3" |
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168 | + PIN 67: "MDI_RP_P4" |
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169 | + PIN 68: "MDI_RN_P4" |
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170 | + PIN 69: "MDI_TP_P4" |
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171 | + PIN 70: "MDI_TN_P4" |
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172 | + PIN 71: "PMIC_SCL" |
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173 | + PIN 72: "PMIC_SDA" |
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174 | + PIN 73: "SPIC1_CLK" |
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175 | + PIN 74: "SPIC1_MOSI" |
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176 | + PIN 75: "SPIC1_MISO" |
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177 | + PIN 76: "SPIC1_CS" |
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178 | + PIN 77: "GPIO_D" |
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179 | + PIN 78: "WATCHDOG" |
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180 | + PIN 79: "RTS3_N" |
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181 | + PIN 80: "CTS3_N" |
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182 | + PIN 81: "TXD3" |
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183 | + PIN 82: "RXD3" |
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184 | + PIN 83: "PERST0_N" |
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185 | + PIN 84: "PERST1_N" |
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186 | + PIN 85: "WLED_N" |
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187 | + PIN 86: "EPHY_LED0_N" |
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188 | + PIN 87: "AUXIN0" |
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189 | + PIN 88: "AUXIN1" |
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190 | + PIN 89: "AUXIN2" |
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191 | + PIN 90: "AUXIN3" |
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192 | + PIN 91: "TXD4" |
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193 | + PIN 92: "RXD4" |
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194 | + PIN 93: "RTS4_N" |
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195 | + PIN 94: "CST4_N" |
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196 | + PIN 95: "PWM1" |
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197 | + PIN 96: "PWM2" |
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198 | + PIN 97: "PWM3" |
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199 | + PIN 98: "PWM4" |
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200 | + PIN 99: "PWM5" |
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201 | + PIN 100: "PWM6" |
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202 | + PIN 101: "PWM7" |
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203 | + PIN 102: "GPIO_E" |
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204 | + |
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205 | +Valid values for function are: |
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206 | + "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie", |
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207 | + "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog" |
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208 | + |
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209 | +Valid values for groups are: |
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210 | +additional data is put followingly with valid value allowing us to know which |
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211 | +applicable function and which relevant pins (in pin#) are able applied for that |
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212 | +group. |
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213 | + |
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214 | + Valid value function pins (in pin#) |
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215 | + ------------------------------------------------------------------------- |
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216 | + "emmc" "emmc" 40, 41, 42, 43, 44, 45, |
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217 | + 47, 48, 49, 50 |
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218 | + "emmc_rst" "emmc" 37 |
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219 | + "esw" "eth" 51, 52, 53, 54, 55, 56, |
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220 | + 57, 58, 59, 60, 61, 62, |
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221 | + 63, 64, 65, 66, 67, 68, |
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222 | + 69, 70 |
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223 | + "esw_p0_p1" "eth" 51, 52, 53, 54, 55, 56, |
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224 | + 57, 58 |
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225 | + "esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64, |
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226 | + 65, 66, 67, 68, 69, 70 |
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227 | + "rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64, |
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228 | + 65, 66, 67, 68, 69, 70 |
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229 | + "rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64, |
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230 | + 65, 66, 67, 68, 69, 70 |
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231 | + "rgmii_via_gmac2" "eth" 25, 26, 27, 28, 29, 30, |
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232 | + 31, 32, 33, 34, 35, 36 |
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233 | + "mdc_mdio" "eth" 23, 24 |
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234 | + "i2c0" "i2c" 14, 15 |
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235 | + "i2c1_0" "i2c" 55, 56 |
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236 | + "i2c1_1" "i2c" 73, 74 |
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237 | + "i2c1_2" "i2c" 87, 88 |
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238 | + "i2c2_0" "i2c" 57, 58 |
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239 | + "i2c2_1" "i2c" 75, 76 |
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240 | + "i2c2_2" "i2c" 89, 90 |
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241 | + "i2s_in_mclk_bclk_ws" "i2s" 3, 4, 5 |
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242 | + "i2s1_in_data" "i2s" 1 |
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243 | + "i2s2_in_data" "i2s" 16 |
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244 | + "i2s3_in_data" "i2s" 17 |
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245 | + "i2s4_in_data" "i2s" 18 |
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246 | + "i2s_out_mclk_bclk_ws" "i2s" 3, 4, 5 |
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247 | + "i2s1_out_data" "i2s" 2 |
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248 | + "i2s2_out_data" "i2s" 19 |
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249 | + "i2s3_out_data" "i2s" 20 |
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250 | + "i2s4_out_data" "i2s" 21 |
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251 | + "ir_0_tx" "ir" 16 |
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252 | + "ir_1_tx" "ir" 59 |
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253 | + "ir_2_tx" "ir" 99 |
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254 | + "ir_0_rx" "ir" 17 |
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255 | + "ir_1_rx" "ir" 60 |
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256 | + "ir_2_rx" "ir" 100 |
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257 | + "ephy_leds" "led" 86, 91, 92, 93, 94 |
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258 | + "ephy0_led" "led" 86 |
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259 | + "ephy1_led" "led" 91 |
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260 | + "ephy2_led" "led" 92 |
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261 | + "ephy3_led" "led" 93 |
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262 | + "ephy4_led" "led" 94 |
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263 | + "wled" "led" 85 |
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264 | + "par_nand" "flash" 37, 38, 39, 40, 41, 42, |
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265 | + 43, 44, 45, 46, 47, 48, |
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266 | + 49, 50 |
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267 | + "snfi" "flash" 8, 9, 10, 11, 12, 13 |
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268 | + "spi_nor" "flash" 8, 9, 10, 11, 12, 13 |
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269 | + "pcie0_0_waken" "pcie" 14 |
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270 | + "pcie0_1_waken" "pcie" 79 |
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271 | + "pcie1_0_waken" "pcie" 14 |
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272 | + "pcie0_0_clkreq" "pcie" 15 |
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273 | + "pcie0_1_clkreq" "pcie" 80 |
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274 | + "pcie1_0_clkreq" "pcie" 15 |
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275 | + "pcie0_pad_perst" "pcie" 83 |
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276 | + "pcie1_pad_perst" "pcie" 84 |
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277 | + "pmic_bus" "pmic" 71, 72 |
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278 | + "pwm_ch1_0" "pwm" 51 |
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279 | + "pwm_ch1_1" "pwm" 73 |
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280 | + "pwm_ch1_2" "pwm" 95 |
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281 | + "pwm_ch2_0" "pwm" 52 |
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282 | + "pwm_ch2_1" "pwm" 74 |
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283 | + "pwm_ch2_2" "pwm" 96 |
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284 | + "pwm_ch3_0" "pwm" 53 |
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285 | + "pwm_ch3_1" "pwm" 75 |
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286 | + "pwm_ch3_2" "pwm" 97 |
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287 | + "pwm_ch4_0" "pwm" 54 |
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288 | + "pwm_ch4_1" "pwm" 67 |
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289 | + "pwm_ch4_2" "pwm" 76 |
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290 | + "pwm_ch4_3" "pwm" 98 |
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291 | + "pwm_ch5_0" "pwm" 68 |
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292 | + "pwm_ch5_1" "pwm" 77 |
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293 | + "pwm_ch5_2" "pwm" 99 |
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294 | + "pwm_ch6_0" "pwm" 69 |
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295 | + "pwm_ch6_1" "pwm" 78 |
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296 | + "pwm_ch6_2" "pwm" 81 |
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297 | + "pwm_ch6_3" "pwm" 100 |
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298 | + "pwm_ch7_0" "pwm" 70 |
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299 | + "pwm_ch7_1" "pwm" 82 |
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300 | + "pwm_ch7_2" "pwm" 101 |
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301 | + "sd_0" "sd" 16, 17, 18, 19, 20, 21 |
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302 | + "sd_1" "sd" 25, 26, 27, 28, 29, 30 |
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303 | + "spic0_0" "spi" 63, 64, 65, 66 |
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304 | + "spic0_1" "spi" 79, 80, 81, 82 |
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305 | + "spic1_0" "spi" 67, 68, 69, 70 |
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306 | + "spic1_1" "spi" 73, 74, 75, 76 |
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307 | + "spic2_0_wp_hold" "spi" 8, 9 |
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308 | + "spic2_0" "spi" 10, 11, 12, 13 |
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309 | + "tdm_0_out_mclk_bclk_ws" "tdm" 8, 9, 10 |
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310 | + "tdm_0_in_mclk_bclk_ws" "tdm" 11, 12, 13 |
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311 | + "tdm_0_out_data" "tdm" 20 |
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312 | + "tdm_0_in_data" "tdm" 21 |
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313 | + "tdm_1_out_mclk_bclk_ws" "tdm" 57, 58, 59 |
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314 | + "tdm_1_in_mclk_bclk_ws" "tdm" 60, 61, 62 |
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315 | + "tdm_1_out_data" "tdm" 55 |
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316 | + "tdm_1_in_data" "tdm" 56 |
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317 | + "uart0_0_tx_rx" "uart" 6, 7 |
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318 | + "uart1_0_tx_rx" "uart" 55, 56 |
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319 | + "uart1_0_rts_cts" "uart" 57, 58 |
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320 | + "uart1_1_tx_rx" "uart" 73, 74 |
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321 | + "uart1_1_rts_cts" "uart" 75, 76 |
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322 | + "uart2_0_tx_rx" "uart" 3, 4 |
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323 | + "uart2_0_rts_cts" "uart" 1, 2 |
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324 | + "uart2_1_tx_rx" "uart" 51, 52 |
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325 | + "uart2_1_rts_cts" "uart" 53, 54 |
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326 | + "uart2_2_tx_rx" "uart" 59, 60 |
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327 | + "uart2_2_rts_cts" "uart" 61, 62 |
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328 | + "uart2_3_tx_rx" "uart" 95, 96 |
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329 | + "uart3_0_tx_rx" "uart" 57, 58 |
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330 | + "uart3_1_tx_rx" "uart" 81, 82 |
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331 | + "uart3_1_rts_cts" "uart" 79, 80 |
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332 | + "uart4_0_tx_rx" "uart" 61, 62 |
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333 | + "uart4_1_tx_rx" "uart" 91, 92 |
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334 | + "uart4_1_rts_cts" "uart" 93, 94 |
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335 | + "uart4_2_tx_rx" "uart" 97, 98 |
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336 | + "uart4_2_rts_cts" "uart" 95, 96 |
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337 | + "watchdog" "watchdog" 78 |
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338 | + |
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339 | +Example: |
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340 | + |
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341 | + pio: pinctrl@10211000 { |
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342 | + compatible = "mediatek,mt7622-pinctrl"; |
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343 | + reg = <0 0x10211000 0 0x1000>; |
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344 | + gpio-controller; |
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345 | + #gpio-cells = <2>; |
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346 | + |
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347 | + pinctrl_eth_default: eth-default { |
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348 | + mux-mdio { |
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349 | + groups = "mdc_mdio"; |
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350 | + function = "eth"; |
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351 | + drive-strength = <12>; |
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352 | + }; |
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353 | + |
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354 | + mux-gmac2 { |
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355 | + groups = "gmac2"; |
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356 | + function = "eth"; |
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357 | + drive-strength = <12>; |
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358 | + }; |
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359 | + |
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360 | + mux-esw { |
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361 | + groups = "esw"; |
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362 | + function = "eth"; |
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363 | + drive-strength = <8>; |
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364 | + }; |
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365 | + |
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366 | + conf-mdio { |
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367 | + pins = "MDC"; |
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368 | + bias-pull-up; |
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369 | + }; |
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370 | + }; |
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371 | + }; |